1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2500"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&vic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 serial0 = &uart1; 28 serial1 = &uart2; 29 serial2 = &uart3; 30 serial3 = &uart4; 31 serial4 = &uart5; 32 serial5 = &vuart; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,arm1176jzf-s"; 41 device_type = "cpu"; 42 reg = <0>; 43 }; 44 }; 45 46 memory@80000000 { 47 device_type = "memory"; 48 reg = <0x80000000 0>; 49 }; 50 51 ahb { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges; 56 57 fmc: spi@1e620000 { 58 reg = < 0x1e620000 0xc4 59 0x20000000 0x10000000 >; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 compatible = "aspeed,ast2500-fmc"; 63 clocks = <&syscon ASPEED_CLK_AHB>; 64 status = "disabled"; 65 interrupts = <19>; 66 flash@0 { 67 reg = < 0 >; 68 compatible = "jedec,spi-nor"; 69 spi-max-frequency = <50000000>; 70 status = "disabled"; 71 }; 72 flash@1 { 73 reg = < 1 >; 74 compatible = "jedec,spi-nor"; 75 spi-max-frequency = <50000000>; 76 status = "disabled"; 77 }; 78 flash@2 { 79 reg = < 2 >; 80 compatible = "jedec,spi-nor"; 81 spi-max-frequency = <50000000>; 82 status = "disabled"; 83 }; 84 }; 85 86 spi1: spi@1e630000 { 87 reg = < 0x1e630000 0xc4 88 0x30000000 0x08000000 >; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 compatible = "aspeed,ast2500-spi"; 92 clocks = <&syscon ASPEED_CLK_AHB>; 93 status = "disabled"; 94 flash@0 { 95 reg = < 0 >; 96 compatible = "jedec,spi-nor"; 97 spi-max-frequency = <50000000>; 98 status = "disabled"; 99 }; 100 flash@1 { 101 reg = < 1 >; 102 compatible = "jedec,spi-nor"; 103 spi-max-frequency = <50000000>; 104 status = "disabled"; 105 }; 106 }; 107 108 spi2: spi@1e631000 { 109 reg = < 0x1e631000 0xc4 110 0x38000000 0x08000000 >; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 compatible = "aspeed,ast2500-spi"; 114 clocks = <&syscon ASPEED_CLK_AHB>; 115 status = "disabled"; 116 flash@0 { 117 reg = < 0 >; 118 compatible = "jedec,spi-nor"; 119 spi-max-frequency = <50000000>; 120 status = "disabled"; 121 }; 122 flash@1 { 123 reg = < 1 >; 124 compatible = "jedec,spi-nor"; 125 spi-max-frequency = <50000000>; 126 status = "disabled"; 127 }; 128 }; 129 130 vic: interrupt-controller@1e6c0080 { 131 compatible = "aspeed,ast2400-vic"; 132 interrupt-controller; 133 #interrupt-cells = <1>; 134 valid-sources = <0xfefff7ff 0x0807ffff>; 135 reg = <0x1e6c0080 0x80>; 136 }; 137 138 cvic: copro-interrupt-controller@1e6c2000 { 139 compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; 140 valid-sources = <0xffffffff>; 141 copro-sw-interrupts = <1>; 142 reg = <0x1e6c2000 0x80>; 143 }; 144 145 mac0: ethernet@1e660000 { 146 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 147 reg = <0x1e660000 0x180>; 148 interrupts = <2>; 149 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 150 status = "disabled"; 151 }; 152 153 mac1: ethernet@1e680000 { 154 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 155 reg = <0x1e680000 0x180>; 156 interrupts = <3>; 157 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 158 status = "disabled"; 159 }; 160 161 ehci0: usb@1e6a1000 { 162 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 163 reg = <0x1e6a1000 0x100>; 164 interrupts = <5>; 165 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_usb2ah_default>; 168 status = "disabled"; 169 }; 170 171 ehci1: usb@1e6a3000 { 172 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 173 reg = <0x1e6a3000 0x100>; 174 interrupts = <13>; 175 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_usb2bh_default>; 178 status = "disabled"; 179 }; 180 181 uhci: usb@1e6b0000 { 182 compatible = "aspeed,ast2500-uhci", "generic-uhci"; 183 reg = <0x1e6b0000 0x100>; 184 interrupts = <14>; 185 #ports = <2>; 186 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 187 status = "disabled"; 188 /* 189 * No default pinmux, it will follow EHCI, use an explicit pinmux 190 * override if you don't enable EHCI 191 */ 192 }; 193 194 vhub: usb-vhub@1e6a0000 { 195 compatible = "aspeed,ast2500-usb-vhub"; 196 reg = <0x1e6a0000 0x300>; 197 interrupts = <5>; 198 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 199 aspeed,vhub-downstream-ports = <5>; 200 aspeed,vhub-generic-endpoints = <15>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_usb2ad_default>; 203 status = "disabled"; 204 }; 205 206 apb { 207 compatible = "simple-bus"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 edac: memory-controller@1e6e0000 { 213 compatible = "aspeed,ast2500-sdram-edac"; 214 reg = <0x1e6e0000 0x174>; 215 interrupts = <0>; 216 status = "disabled"; 217 }; 218 219 syscon: syscon@1e6e2000 { 220 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; 221 reg = <0x1e6e2000 0x1a8>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0x1e6e2000 0x1000>; 225 #clock-cells = <1>; 226 #reset-cells = <1>; 227 228 scu_ic: interrupt-controller@18 { 229 #interrupt-cells = <1>; 230 compatible = "aspeed,ast2500-scu-ic"; 231 reg = <0x18 0x4>; 232 interrupts = <21>; 233 interrupt-controller; 234 }; 235 236 p2a: p2a-control@2c { 237 compatible = "aspeed,ast2500-p2a-ctrl"; 238 reg = <0x2c 0x4>; 239 status = "disabled"; 240 }; 241 242 pinctrl: pinctrl@80 { 243 compatible = "aspeed,ast2500-pinctrl"; 244 reg = <0x80 0x18>, <0xa0 0x10>; 245 aspeed,external-nodes = <&gfx>, <&lhc>; 246 }; 247 }; 248 249 rng: hwrng@1e6e2078 { 250 compatible = "timeriomem_rng"; 251 reg = <0x1e6e2078 0x4>; 252 period = <1>; 253 quality = <100>; 254 }; 255 256 gfx: display@1e6e6000 { 257 compatible = "aspeed,ast2500-gfx", "syscon"; 258 reg = <0x1e6e6000 0x1000>; 259 reg-io-width = <4>; 260 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; 261 resets = <&syscon ASPEED_RESET_CRT1>; 262 status = "disabled"; 263 interrupts = <0x19>; 264 }; 265 266 xdma: xdma@1e6e7000 { 267 compatible = "aspeed,ast2500-xdma"; 268 reg = <0x1e6e7000 0x100>; 269 clocks = <&syscon ASPEED_CLK_GATE_BCLK>; 270 resets = <&syscon ASPEED_RESET_XDMA>; 271 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; 272 aspeed,pcie-device = "bmc"; 273 aspeed,scu = <&syscon>; 274 status = "disabled"; 275 }; 276 277 adc: adc@1e6e9000 { 278 compatible = "aspeed,ast2500-adc"; 279 reg = <0x1e6e9000 0xb0>; 280 clocks = <&syscon ASPEED_CLK_APB>; 281 resets = <&syscon ASPEED_RESET_ADC>; 282 #io-channel-cells = <1>; 283 status = "disabled"; 284 }; 285 286 video: video@1e700000 { 287 compatible = "aspeed,ast2500-video-engine"; 288 reg = <0x1e700000 0x1000>; 289 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 290 <&syscon ASPEED_CLK_GATE_ECLK>; 291 clock-names = "vclk", "eclk"; 292 interrupts = <7>; 293 status = "disabled"; 294 }; 295 296 sram: sram@1e720000 { 297 compatible = "mmio-sram"; 298 reg = <0x1e720000 0x9000>; // 36K 299 }; 300 301 sdmmc: sd-controller@1e740000 { 302 compatible = "aspeed,ast2500-sd-controller"; 303 reg = <0x1e740000 0x100>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 ranges = <0 0x1e740000 0x10000>; 307 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 308 status = "disabled"; 309 310 sdhci0: sdhci@100 { 311 compatible = "aspeed,ast2500-sdhci"; 312 reg = <0x100 0x100>; 313 interrupts = <26>; 314 sdhci,auto-cmd12; 315 clocks = <&syscon ASPEED_CLK_SDIO>; 316 status = "disabled"; 317 }; 318 319 sdhci1: sdhci@200 { 320 compatible = "aspeed,ast2500-sdhci"; 321 reg = <0x200 0x100>; 322 interrupts = <26>; 323 sdhci,auto-cmd12; 324 clocks = <&syscon ASPEED_CLK_SDIO>; 325 status = "disabled"; 326 }; 327 }; 328 329 gpio: gpio@1e780000 { 330 #gpio-cells = <2>; 331 gpio-controller; 332 compatible = "aspeed,ast2500-gpio"; 333 reg = <0x1e780000 0x200>; 334 interrupts = <20>; 335 gpio-ranges = <&pinctrl 0 0 232>; 336 clocks = <&syscon ASPEED_CLK_APB>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 }; 340 341 sgpio: sgpio@1e780200 { 342 #gpio-cells = <2>; 343 compatible = "aspeed,ast2500-sgpio"; 344 gpio-controller; 345 interrupts = <40>; 346 reg = <0x1e780200 0x0100>; 347 clocks = <&syscon ASPEED_CLK_APB>; 348 interrupt-controller; 349 ngpios = <8>; 350 bus-frequency = <12000000>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_sgpm_default>; 353 status = "disabled"; 354 }; 355 356 rtc: rtc@1e781000 { 357 compatible = "aspeed,ast2500-rtc"; 358 reg = <0x1e781000 0x18>; 359 status = "disabled"; 360 }; 361 362 timer: timer@1e782000 { 363 /* This timer is a Faraday FTTMR010 derivative */ 364 compatible = "aspeed,ast2400-timer"; 365 reg = <0x1e782000 0x90>; 366 interrupts = <16 17 18 35 36 37 38 39>; 367 clocks = <&syscon ASPEED_CLK_APB>; 368 clock-names = "PCLK"; 369 }; 370 371 uart1: serial@1e783000 { 372 compatible = "ns16550a"; 373 reg = <0x1e783000 0x20>; 374 reg-shift = <2>; 375 interrupts = <9>; 376 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 377 resets = <&lpc_reset 4>; 378 no-loopback-test; 379 status = "disabled"; 380 }; 381 382 uart5: serial@1e784000 { 383 compatible = "ns16550a"; 384 reg = <0x1e784000 0x20>; 385 reg-shift = <2>; 386 interrupts = <10>; 387 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 388 no-loopback-test; 389 status = "disabled"; 390 }; 391 392 wdt1: watchdog@1e785000 { 393 compatible = "aspeed,ast2500-wdt"; 394 reg = <0x1e785000 0x20>; 395 clocks = <&syscon ASPEED_CLK_APB>; 396 }; 397 398 wdt2: watchdog@1e785020 { 399 compatible = "aspeed,ast2500-wdt"; 400 reg = <0x1e785020 0x20>; 401 clocks = <&syscon ASPEED_CLK_APB>; 402 }; 403 404 wdt3: watchdog@1e785040 { 405 compatible = "aspeed,ast2500-wdt"; 406 reg = <0x1e785040 0x20>; 407 clocks = <&syscon ASPEED_CLK_APB>; 408 status = "disabled"; 409 }; 410 411 pwm_tacho: pwm-tacho-controller@1e786000 { 412 compatible = "aspeed,ast2500-pwm-tacho"; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 reg = <0x1e786000 0x1000>; 416 clocks = <&syscon ASPEED_CLK_24M>; 417 resets = <&syscon ASPEED_RESET_PWM>; 418 status = "disabled"; 419 }; 420 421 vuart: serial@1e787000 { 422 compatible = "aspeed,ast2500-vuart"; 423 reg = <0x1e787000 0x40>; 424 reg-shift = <2>; 425 interrupts = <8>; 426 clocks = <&syscon ASPEED_CLK_APB>; 427 no-loopback-test; 428 status = "disabled"; 429 }; 430 431 lpc: lpc@1e789000 { 432 compatible = "aspeed,ast2500-lpc", "simple-mfd"; 433 reg = <0x1e789000 0x1000>; 434 435 #address-cells = <1>; 436 #size-cells = <1>; 437 ranges = <0x0 0x1e789000 0x1000>; 438 439 lpc_bmc: lpc-bmc@0 { 440 compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon"; 441 reg = <0x0 0x80>; 442 reg-io-width = <4>; 443 444 #address-cells = <1>; 445 #size-cells = <1>; 446 ranges = <0x0 0x0 0x80>; 447 448 kcs1: kcs@24 { 449 compatible = "aspeed,ast2500-kcs-bmc-v2"; 450 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; 451 interrupts = <8>; 452 status = "disabled"; 453 }; 454 kcs2: kcs@28 { 455 compatible = "aspeed,ast2500-kcs-bmc-v2"; 456 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; 457 interrupts = <8>; 458 status = "disabled"; 459 }; 460 kcs3: kcs@2c { 461 compatible = "aspeed,ast2500-kcs-bmc-v2"; 462 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; 463 interrupts = <8>; 464 status = "disabled"; 465 }; 466 }; 467 468 lpc_host: lpc-host@80 { 469 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; 470 reg = <0x80 0x1e0>; 471 reg-io-width = <4>; 472 473 #address-cells = <1>; 474 #size-cells = <1>; 475 ranges = <0x0 0x80 0x1e0>; 476 477 kcs4: kcs@94 { 478 compatible = "aspeed,ast2500-kcs-bmc-v2"; 479 reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>; 480 interrupts = <8>; 481 status = "disabled"; 482 }; 483 484 lpc_ctrl: lpc-ctrl@0 { 485 compatible = "aspeed,ast2500-lpc-ctrl"; 486 reg = <0x0 0x10>; 487 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 488 status = "disabled"; 489 }; 490 491 lpc_snoop: lpc-snoop@10 { 492 compatible = "aspeed,ast2500-lpc-snoop"; 493 reg = <0x10 0x8>; 494 interrupts = <8>; 495 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 496 status = "disabled"; 497 }; 498 499 lpc_reset: reset-controller@18 { 500 compatible = "aspeed,ast2500-lpc-reset"; 501 reg = <0x18 0x4>; 502 #reset-cells = <1>; 503 }; 504 505 lhc: lhc@20 { 506 compatible = "aspeed,ast2500-lhc"; 507 reg = <0x20 0x24 0x48 0x8>; 508 }; 509 510 511 ibt: ibt@c0 { 512 compatible = "aspeed,ast2500-ibt-bmc"; 513 reg = <0xc0 0x18>; 514 interrupts = <8>; 515 status = "disabled"; 516 }; 517 }; 518 }; 519 520 uart2: serial@1e78d000 { 521 compatible = "ns16550a"; 522 reg = <0x1e78d000 0x20>; 523 reg-shift = <2>; 524 interrupts = <32>; 525 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 526 resets = <&lpc_reset 5>; 527 no-loopback-test; 528 status = "disabled"; 529 }; 530 531 uart3: serial@1e78e000 { 532 compatible = "ns16550a"; 533 reg = <0x1e78e000 0x20>; 534 reg-shift = <2>; 535 interrupts = <33>; 536 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 537 resets = <&lpc_reset 6>; 538 no-loopback-test; 539 status = "disabled"; 540 }; 541 542 uart4: serial@1e78f000 { 543 compatible = "ns16550a"; 544 reg = <0x1e78f000 0x20>; 545 reg-shift = <2>; 546 interrupts = <34>; 547 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 548 resets = <&lpc_reset 7>; 549 no-loopback-test; 550 status = "disabled"; 551 }; 552 553 i2c: bus@1e78a000 { 554 compatible = "simple-bus"; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 ranges = <0 0x1e78a000 0x1000>; 558 }; 559 }; 560 }; 561}; 562 563&i2c { 564 i2c_ic: interrupt-controller@0 { 565 #interrupt-cells = <1>; 566 compatible = "aspeed,ast2500-i2c-ic"; 567 reg = <0x0 0x40>; 568 interrupts = <12>; 569 interrupt-controller; 570 }; 571 572 i2c0: i2c-bus@40 { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 #interrupt-cells = <1>; 576 577 reg = <0x40 0x40>; 578 compatible = "aspeed,ast2500-i2c-bus"; 579 clocks = <&syscon ASPEED_CLK_APB>; 580 resets = <&syscon ASPEED_RESET_I2C>; 581 bus-frequency = <100000>; 582 interrupts = <0>; 583 interrupt-parent = <&i2c_ic>; 584 status = "disabled"; 585 /* Does not need pinctrl properties */ 586 }; 587 588 i2c1: i2c-bus@80 { 589 #address-cells = <1>; 590 #size-cells = <0>; 591 #interrupt-cells = <1>; 592 593 reg = <0x80 0x40>; 594 compatible = "aspeed,ast2500-i2c-bus"; 595 clocks = <&syscon ASPEED_CLK_APB>; 596 resets = <&syscon ASPEED_RESET_I2C>; 597 bus-frequency = <100000>; 598 interrupts = <1>; 599 interrupt-parent = <&i2c_ic>; 600 status = "disabled"; 601 /* Does not need pinctrl properties */ 602 }; 603 604 i2c2: i2c-bus@c0 { 605 #address-cells = <1>; 606 #size-cells = <0>; 607 #interrupt-cells = <1>; 608 609 reg = <0xc0 0x40>; 610 compatible = "aspeed,ast2500-i2c-bus"; 611 clocks = <&syscon ASPEED_CLK_APB>; 612 resets = <&syscon ASPEED_RESET_I2C>; 613 bus-frequency = <100000>; 614 interrupts = <2>; 615 interrupt-parent = <&i2c_ic>; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&pinctrl_i2c3_default>; 618 status = "disabled"; 619 }; 620 621 i2c3: i2c-bus@100 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 #interrupt-cells = <1>; 625 626 reg = <0x100 0x40>; 627 compatible = "aspeed,ast2500-i2c-bus"; 628 clocks = <&syscon ASPEED_CLK_APB>; 629 resets = <&syscon ASPEED_RESET_I2C>; 630 bus-frequency = <100000>; 631 interrupts = <3>; 632 interrupt-parent = <&i2c_ic>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&pinctrl_i2c4_default>; 635 status = "disabled"; 636 }; 637 638 i2c4: i2c-bus@140 { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 #interrupt-cells = <1>; 642 643 reg = <0x140 0x40>; 644 compatible = "aspeed,ast2500-i2c-bus"; 645 clocks = <&syscon ASPEED_CLK_APB>; 646 resets = <&syscon ASPEED_RESET_I2C>; 647 bus-frequency = <100000>; 648 interrupts = <4>; 649 interrupt-parent = <&i2c_ic>; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&pinctrl_i2c5_default>; 652 status = "disabled"; 653 }; 654 655 i2c5: i2c-bus@180 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 #interrupt-cells = <1>; 659 660 reg = <0x180 0x40>; 661 compatible = "aspeed,ast2500-i2c-bus"; 662 clocks = <&syscon ASPEED_CLK_APB>; 663 resets = <&syscon ASPEED_RESET_I2C>; 664 bus-frequency = <100000>; 665 interrupts = <5>; 666 interrupt-parent = <&i2c_ic>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pinctrl_i2c6_default>; 669 status = "disabled"; 670 }; 671 672 i2c6: i2c-bus@1c0 { 673 #address-cells = <1>; 674 #size-cells = <0>; 675 #interrupt-cells = <1>; 676 677 reg = <0x1c0 0x40>; 678 compatible = "aspeed,ast2500-i2c-bus"; 679 clocks = <&syscon ASPEED_CLK_APB>; 680 resets = <&syscon ASPEED_RESET_I2C>; 681 bus-frequency = <100000>; 682 interrupts = <6>; 683 interrupt-parent = <&i2c_ic>; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&pinctrl_i2c7_default>; 686 status = "disabled"; 687 }; 688 689 i2c7: i2c-bus@300 { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 #interrupt-cells = <1>; 693 694 reg = <0x300 0x40>; 695 compatible = "aspeed,ast2500-i2c-bus"; 696 clocks = <&syscon ASPEED_CLK_APB>; 697 resets = <&syscon ASPEED_RESET_I2C>; 698 bus-frequency = <100000>; 699 interrupts = <7>; 700 interrupt-parent = <&i2c_ic>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&pinctrl_i2c8_default>; 703 status = "disabled"; 704 }; 705 706 i2c8: i2c-bus@340 { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 #interrupt-cells = <1>; 710 711 reg = <0x340 0x40>; 712 compatible = "aspeed,ast2500-i2c-bus"; 713 clocks = <&syscon ASPEED_CLK_APB>; 714 resets = <&syscon ASPEED_RESET_I2C>; 715 bus-frequency = <100000>; 716 interrupts = <8>; 717 interrupt-parent = <&i2c_ic>; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&pinctrl_i2c9_default>; 720 status = "disabled"; 721 }; 722 723 i2c9: i2c-bus@380 { 724 #address-cells = <1>; 725 #size-cells = <0>; 726 #interrupt-cells = <1>; 727 728 reg = <0x380 0x40>; 729 compatible = "aspeed,ast2500-i2c-bus"; 730 clocks = <&syscon ASPEED_CLK_APB>; 731 resets = <&syscon ASPEED_RESET_I2C>; 732 bus-frequency = <100000>; 733 interrupts = <9>; 734 interrupt-parent = <&i2c_ic>; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&pinctrl_i2c10_default>; 737 status = "disabled"; 738 }; 739 740 i2c10: i2c-bus@3c0 { 741 #address-cells = <1>; 742 #size-cells = <0>; 743 #interrupt-cells = <1>; 744 745 reg = <0x3c0 0x40>; 746 compatible = "aspeed,ast2500-i2c-bus"; 747 clocks = <&syscon ASPEED_CLK_APB>; 748 resets = <&syscon ASPEED_RESET_I2C>; 749 bus-frequency = <100000>; 750 interrupts = <10>; 751 interrupt-parent = <&i2c_ic>; 752 pinctrl-names = "default"; 753 pinctrl-0 = <&pinctrl_i2c11_default>; 754 status = "disabled"; 755 }; 756 757 i2c11: i2c-bus@400 { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 #interrupt-cells = <1>; 761 762 reg = <0x400 0x40>; 763 compatible = "aspeed,ast2500-i2c-bus"; 764 clocks = <&syscon ASPEED_CLK_APB>; 765 resets = <&syscon ASPEED_RESET_I2C>; 766 bus-frequency = <100000>; 767 interrupts = <11>; 768 interrupt-parent = <&i2c_ic>; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&pinctrl_i2c12_default>; 771 status = "disabled"; 772 }; 773 774 i2c12: i2c-bus@440 { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 #interrupt-cells = <1>; 778 779 reg = <0x440 0x40>; 780 compatible = "aspeed,ast2500-i2c-bus"; 781 clocks = <&syscon ASPEED_CLK_APB>; 782 resets = <&syscon ASPEED_RESET_I2C>; 783 bus-frequency = <100000>; 784 interrupts = <12>; 785 interrupt-parent = <&i2c_ic>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&pinctrl_i2c13_default>; 788 status = "disabled"; 789 }; 790 791 i2c13: i2c-bus@480 { 792 #address-cells = <1>; 793 #size-cells = <0>; 794 #interrupt-cells = <1>; 795 796 reg = <0x480 0x40>; 797 compatible = "aspeed,ast2500-i2c-bus"; 798 clocks = <&syscon ASPEED_CLK_APB>; 799 resets = <&syscon ASPEED_RESET_I2C>; 800 bus-frequency = <100000>; 801 interrupts = <13>; 802 interrupt-parent = <&i2c_ic>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&pinctrl_i2c14_default>; 805 status = "disabled"; 806 }; 807}; 808 809&pinctrl { 810 pinctrl_acpi_default: acpi_default { 811 function = "ACPI"; 812 groups = "ACPI"; 813 }; 814 815 pinctrl_adc0_default: adc0_default { 816 function = "ADC0"; 817 groups = "ADC0"; 818 }; 819 820 pinctrl_adc1_default: adc1_default { 821 function = "ADC1"; 822 groups = "ADC1"; 823 }; 824 825 pinctrl_adc10_default: adc10_default { 826 function = "ADC10"; 827 groups = "ADC10"; 828 }; 829 830 pinctrl_adc11_default: adc11_default { 831 function = "ADC11"; 832 groups = "ADC11"; 833 }; 834 835 pinctrl_adc12_default: adc12_default { 836 function = "ADC12"; 837 groups = "ADC12"; 838 }; 839 840 pinctrl_adc13_default: adc13_default { 841 function = "ADC13"; 842 groups = "ADC13"; 843 }; 844 845 pinctrl_adc14_default: adc14_default { 846 function = "ADC14"; 847 groups = "ADC14"; 848 }; 849 850 pinctrl_adc15_default: adc15_default { 851 function = "ADC15"; 852 groups = "ADC15"; 853 }; 854 855 pinctrl_adc2_default: adc2_default { 856 function = "ADC2"; 857 groups = "ADC2"; 858 }; 859 860 pinctrl_adc3_default: adc3_default { 861 function = "ADC3"; 862 groups = "ADC3"; 863 }; 864 865 pinctrl_adc4_default: adc4_default { 866 function = "ADC4"; 867 groups = "ADC4"; 868 }; 869 870 pinctrl_adc5_default: adc5_default { 871 function = "ADC5"; 872 groups = "ADC5"; 873 }; 874 875 pinctrl_adc6_default: adc6_default { 876 function = "ADC6"; 877 groups = "ADC6"; 878 }; 879 880 pinctrl_adc7_default: adc7_default { 881 function = "ADC7"; 882 groups = "ADC7"; 883 }; 884 885 pinctrl_adc8_default: adc8_default { 886 function = "ADC8"; 887 groups = "ADC8"; 888 }; 889 890 pinctrl_adc9_default: adc9_default { 891 function = "ADC9"; 892 groups = "ADC9"; 893 }; 894 895 pinctrl_bmcint_default: bmcint_default { 896 function = "BMCINT"; 897 groups = "BMCINT"; 898 }; 899 900 pinctrl_ddcclk_default: ddcclk_default { 901 function = "DDCCLK"; 902 groups = "DDCCLK"; 903 }; 904 905 pinctrl_ddcdat_default: ddcdat_default { 906 function = "DDCDAT"; 907 groups = "DDCDAT"; 908 }; 909 910 pinctrl_espi_default: espi_default { 911 function = "ESPI"; 912 groups = "ESPI"; 913 }; 914 915 pinctrl_fwspics1_default: fwspics1_default { 916 function = "FWSPICS1"; 917 groups = "FWSPICS1"; 918 }; 919 920 pinctrl_fwspics2_default: fwspics2_default { 921 function = "FWSPICS2"; 922 groups = "FWSPICS2"; 923 }; 924 925 pinctrl_gpid0_default: gpid0_default { 926 function = "GPID0"; 927 groups = "GPID0"; 928 }; 929 930 pinctrl_gpid2_default: gpid2_default { 931 function = "GPID2"; 932 groups = "GPID2"; 933 }; 934 935 pinctrl_gpid4_default: gpid4_default { 936 function = "GPID4"; 937 groups = "GPID4"; 938 }; 939 940 pinctrl_gpid6_default: gpid6_default { 941 function = "GPID6"; 942 groups = "GPID6"; 943 }; 944 945 pinctrl_gpie0_default: gpie0_default { 946 function = "GPIE0"; 947 groups = "GPIE0"; 948 }; 949 950 pinctrl_gpie2_default: gpie2_default { 951 function = "GPIE2"; 952 groups = "GPIE2"; 953 }; 954 955 pinctrl_gpie4_default: gpie4_default { 956 function = "GPIE4"; 957 groups = "GPIE4"; 958 }; 959 960 pinctrl_gpie6_default: gpie6_default { 961 function = "GPIE6"; 962 groups = "GPIE6"; 963 }; 964 965 pinctrl_i2c10_default: i2c10_default { 966 function = "I2C10"; 967 groups = "I2C10"; 968 }; 969 970 pinctrl_i2c11_default: i2c11_default { 971 function = "I2C11"; 972 groups = "I2C11"; 973 }; 974 975 pinctrl_i2c12_default: i2c12_default { 976 function = "I2C12"; 977 groups = "I2C12"; 978 }; 979 980 pinctrl_i2c13_default: i2c13_default { 981 function = "I2C13"; 982 groups = "I2C13"; 983 }; 984 985 pinctrl_i2c14_default: i2c14_default { 986 function = "I2C14"; 987 groups = "I2C14"; 988 }; 989 990 pinctrl_i2c3_default: i2c3_default { 991 function = "I2C3"; 992 groups = "I2C3"; 993 }; 994 995 pinctrl_i2c4_default: i2c4_default { 996 function = "I2C4"; 997 groups = "I2C4"; 998 }; 999 1000 pinctrl_i2c5_default: i2c5_default { 1001 function = "I2C5"; 1002 groups = "I2C5"; 1003 }; 1004 1005 pinctrl_i2c6_default: i2c6_default { 1006 function = "I2C6"; 1007 groups = "I2C6"; 1008 }; 1009 1010 pinctrl_i2c7_default: i2c7_default { 1011 function = "I2C7"; 1012 groups = "I2C7"; 1013 }; 1014 1015 pinctrl_i2c8_default: i2c8_default { 1016 function = "I2C8"; 1017 groups = "I2C8"; 1018 }; 1019 1020 pinctrl_i2c9_default: i2c9_default { 1021 function = "I2C9"; 1022 groups = "I2C9"; 1023 }; 1024 1025 pinctrl_lad0_default: lad0_default { 1026 function = "LAD0"; 1027 groups = "LAD0"; 1028 }; 1029 1030 pinctrl_lad1_default: lad1_default { 1031 function = "LAD1"; 1032 groups = "LAD1"; 1033 }; 1034 1035 pinctrl_lad2_default: lad2_default { 1036 function = "LAD2"; 1037 groups = "LAD2"; 1038 }; 1039 1040 pinctrl_lad3_default: lad3_default { 1041 function = "LAD3"; 1042 groups = "LAD3"; 1043 }; 1044 1045 pinctrl_lclk_default: lclk_default { 1046 function = "LCLK"; 1047 groups = "LCLK"; 1048 }; 1049 1050 pinctrl_lframe_default: lframe_default { 1051 function = "LFRAME"; 1052 groups = "LFRAME"; 1053 }; 1054 1055 pinctrl_lpchc_default: lpchc_default { 1056 function = "LPCHC"; 1057 groups = "LPCHC"; 1058 }; 1059 1060 pinctrl_lpcpd_default: lpcpd_default { 1061 function = "LPCPD"; 1062 groups = "LPCPD"; 1063 }; 1064 1065 pinctrl_lpcplus_default: lpcplus_default { 1066 function = "LPCPLUS"; 1067 groups = "LPCPLUS"; 1068 }; 1069 1070 pinctrl_lpcpme_default: lpcpme_default { 1071 function = "LPCPME"; 1072 groups = "LPCPME"; 1073 }; 1074 1075 pinctrl_lpcrst_default: lpcrst_default { 1076 function = "LPCRST"; 1077 groups = "LPCRST"; 1078 }; 1079 1080 pinctrl_lpcsmi_default: lpcsmi_default { 1081 function = "LPCSMI"; 1082 groups = "LPCSMI"; 1083 }; 1084 1085 pinctrl_lsirq_default: lsirq_default { 1086 function = "LSIRQ"; 1087 groups = "LSIRQ"; 1088 }; 1089 1090 pinctrl_mac1link_default: mac1link_default { 1091 function = "MAC1LINK"; 1092 groups = "MAC1LINK"; 1093 }; 1094 1095 pinctrl_mac2link_default: mac2link_default { 1096 function = "MAC2LINK"; 1097 groups = "MAC2LINK"; 1098 }; 1099 1100 pinctrl_mdio1_default: mdio1_default { 1101 function = "MDIO1"; 1102 groups = "MDIO1"; 1103 }; 1104 1105 pinctrl_mdio2_default: mdio2_default { 1106 function = "MDIO2"; 1107 groups = "MDIO2"; 1108 }; 1109 1110 pinctrl_ncts1_default: ncts1_default { 1111 function = "NCTS1"; 1112 groups = "NCTS1"; 1113 }; 1114 1115 pinctrl_ncts2_default: ncts2_default { 1116 function = "NCTS2"; 1117 groups = "NCTS2"; 1118 }; 1119 1120 pinctrl_ncts3_default: ncts3_default { 1121 function = "NCTS3"; 1122 groups = "NCTS3"; 1123 }; 1124 1125 pinctrl_ncts4_default: ncts4_default { 1126 function = "NCTS4"; 1127 groups = "NCTS4"; 1128 }; 1129 1130 pinctrl_ndcd1_default: ndcd1_default { 1131 function = "NDCD1"; 1132 groups = "NDCD1"; 1133 }; 1134 1135 pinctrl_ndcd2_default: ndcd2_default { 1136 function = "NDCD2"; 1137 groups = "NDCD2"; 1138 }; 1139 1140 pinctrl_ndcd3_default: ndcd3_default { 1141 function = "NDCD3"; 1142 groups = "NDCD3"; 1143 }; 1144 1145 pinctrl_ndcd4_default: ndcd4_default { 1146 function = "NDCD4"; 1147 groups = "NDCD4"; 1148 }; 1149 1150 pinctrl_ndsr1_default: ndsr1_default { 1151 function = "NDSR1"; 1152 groups = "NDSR1"; 1153 }; 1154 1155 pinctrl_ndsr2_default: ndsr2_default { 1156 function = "NDSR2"; 1157 groups = "NDSR2"; 1158 }; 1159 1160 pinctrl_ndsr3_default: ndsr3_default { 1161 function = "NDSR3"; 1162 groups = "NDSR3"; 1163 }; 1164 1165 pinctrl_ndsr4_default: ndsr4_default { 1166 function = "NDSR4"; 1167 groups = "NDSR4"; 1168 }; 1169 1170 pinctrl_ndtr1_default: ndtr1_default { 1171 function = "NDTR1"; 1172 groups = "NDTR1"; 1173 }; 1174 1175 pinctrl_ndtr2_default: ndtr2_default { 1176 function = "NDTR2"; 1177 groups = "NDTR2"; 1178 }; 1179 1180 pinctrl_ndtr3_default: ndtr3_default { 1181 function = "NDTR3"; 1182 groups = "NDTR3"; 1183 }; 1184 1185 pinctrl_ndtr4_default: ndtr4_default { 1186 function = "NDTR4"; 1187 groups = "NDTR4"; 1188 }; 1189 1190 pinctrl_nri1_default: nri1_default { 1191 function = "NRI1"; 1192 groups = "NRI1"; 1193 }; 1194 1195 pinctrl_nri2_default: nri2_default { 1196 function = "NRI2"; 1197 groups = "NRI2"; 1198 }; 1199 1200 pinctrl_nri3_default: nri3_default { 1201 function = "NRI3"; 1202 groups = "NRI3"; 1203 }; 1204 1205 pinctrl_nri4_default: nri4_default { 1206 function = "NRI4"; 1207 groups = "NRI4"; 1208 }; 1209 1210 pinctrl_nrts1_default: nrts1_default { 1211 function = "NRTS1"; 1212 groups = "NRTS1"; 1213 }; 1214 1215 pinctrl_nrts2_default: nrts2_default { 1216 function = "NRTS2"; 1217 groups = "NRTS2"; 1218 }; 1219 1220 pinctrl_nrts3_default: nrts3_default { 1221 function = "NRTS3"; 1222 groups = "NRTS3"; 1223 }; 1224 1225 pinctrl_nrts4_default: nrts4_default { 1226 function = "NRTS4"; 1227 groups = "NRTS4"; 1228 }; 1229 1230 pinctrl_oscclk_default: oscclk_default { 1231 function = "OSCCLK"; 1232 groups = "OSCCLK"; 1233 }; 1234 1235 pinctrl_pewake_default: pewake_default { 1236 function = "PEWAKE"; 1237 groups = "PEWAKE"; 1238 }; 1239 1240 pinctrl_pnor_default: pnor_default { 1241 function = "PNOR"; 1242 groups = "PNOR"; 1243 }; 1244 1245 pinctrl_pwm0_default: pwm0_default { 1246 function = "PWM0"; 1247 groups = "PWM0"; 1248 }; 1249 1250 pinctrl_pwm1_default: pwm1_default { 1251 function = "PWM1"; 1252 groups = "PWM1"; 1253 }; 1254 1255 pinctrl_pwm2_default: pwm2_default { 1256 function = "PWM2"; 1257 groups = "PWM2"; 1258 }; 1259 1260 pinctrl_pwm3_default: pwm3_default { 1261 function = "PWM3"; 1262 groups = "PWM3"; 1263 }; 1264 1265 pinctrl_pwm4_default: pwm4_default { 1266 function = "PWM4"; 1267 groups = "PWM4"; 1268 }; 1269 1270 pinctrl_pwm5_default: pwm5_default { 1271 function = "PWM5"; 1272 groups = "PWM5"; 1273 }; 1274 1275 pinctrl_pwm6_default: pwm6_default { 1276 function = "PWM6"; 1277 groups = "PWM6"; 1278 }; 1279 1280 pinctrl_pwm7_default: pwm7_default { 1281 function = "PWM7"; 1282 groups = "PWM7"; 1283 }; 1284 1285 pinctrl_rgmii1_default: rgmii1_default { 1286 function = "RGMII1"; 1287 groups = "RGMII1"; 1288 }; 1289 1290 pinctrl_rgmii2_default: rgmii2_default { 1291 function = "RGMII2"; 1292 groups = "RGMII2"; 1293 }; 1294 1295 pinctrl_rmii1_default: rmii1_default { 1296 function = "RMII1"; 1297 groups = "RMII1"; 1298 }; 1299 1300 pinctrl_rmii2_default: rmii2_default { 1301 function = "RMII2"; 1302 groups = "RMII2"; 1303 }; 1304 1305 pinctrl_rxd1_default: rxd1_default { 1306 function = "RXD1"; 1307 groups = "RXD1"; 1308 }; 1309 1310 pinctrl_rxd2_default: rxd2_default { 1311 function = "RXD2"; 1312 groups = "RXD2"; 1313 }; 1314 1315 pinctrl_rxd3_default: rxd3_default { 1316 function = "RXD3"; 1317 groups = "RXD3"; 1318 }; 1319 1320 pinctrl_rxd4_default: rxd4_default { 1321 function = "RXD4"; 1322 groups = "RXD4"; 1323 }; 1324 1325 pinctrl_salt1_default: salt1_default { 1326 function = "SALT1"; 1327 groups = "SALT1"; 1328 }; 1329 1330 pinctrl_salt10_default: salt10_default { 1331 function = "SALT10"; 1332 groups = "SALT10"; 1333 }; 1334 1335 pinctrl_salt11_default: salt11_default { 1336 function = "SALT11"; 1337 groups = "SALT11"; 1338 }; 1339 1340 pinctrl_salt12_default: salt12_default { 1341 function = "SALT12"; 1342 groups = "SALT12"; 1343 }; 1344 1345 pinctrl_salt13_default: salt13_default { 1346 function = "SALT13"; 1347 groups = "SALT13"; 1348 }; 1349 1350 pinctrl_salt14_default: salt14_default { 1351 function = "SALT14"; 1352 groups = "SALT14"; 1353 }; 1354 1355 pinctrl_salt2_default: salt2_default { 1356 function = "SALT2"; 1357 groups = "SALT2"; 1358 }; 1359 1360 pinctrl_salt3_default: salt3_default { 1361 function = "SALT3"; 1362 groups = "SALT3"; 1363 }; 1364 1365 pinctrl_salt4_default: salt4_default { 1366 function = "SALT4"; 1367 groups = "SALT4"; 1368 }; 1369 1370 pinctrl_salt5_default: salt5_default { 1371 function = "SALT5"; 1372 groups = "SALT5"; 1373 }; 1374 1375 pinctrl_salt6_default: salt6_default { 1376 function = "SALT6"; 1377 groups = "SALT6"; 1378 }; 1379 1380 pinctrl_salt7_default: salt7_default { 1381 function = "SALT7"; 1382 groups = "SALT7"; 1383 }; 1384 1385 pinctrl_salt8_default: salt8_default { 1386 function = "SALT8"; 1387 groups = "SALT8"; 1388 }; 1389 1390 pinctrl_salt9_default: salt9_default { 1391 function = "SALT9"; 1392 groups = "SALT9"; 1393 }; 1394 1395 pinctrl_scl1_default: scl1_default { 1396 function = "SCL1"; 1397 groups = "SCL1"; 1398 }; 1399 1400 pinctrl_scl2_default: scl2_default { 1401 function = "SCL2"; 1402 groups = "SCL2"; 1403 }; 1404 1405 pinctrl_sd1_default: sd1_default { 1406 function = "SD1"; 1407 groups = "SD1"; 1408 }; 1409 1410 pinctrl_sd2_default: sd2_default { 1411 function = "SD2"; 1412 groups = "SD2"; 1413 }; 1414 1415 pinctrl_sda1_default: sda1_default { 1416 function = "SDA1"; 1417 groups = "SDA1"; 1418 }; 1419 1420 pinctrl_sda2_default: sda2_default { 1421 function = "SDA2"; 1422 groups = "SDA2"; 1423 }; 1424 1425 pinctrl_sgpm_default: sgpm_default { 1426 function = "SGPM"; 1427 groups = "SGPM"; 1428 }; 1429 1430 pinctrl_sgps1_default: sgps1_default { 1431 function = "SGPS1"; 1432 groups = "SGPS1"; 1433 }; 1434 1435 pinctrl_sgps2_default: sgps2_default { 1436 function = "SGPS2"; 1437 groups = "SGPS2"; 1438 }; 1439 1440 pinctrl_sioonctrl_default: sioonctrl_default { 1441 function = "SIOONCTRL"; 1442 groups = "SIOONCTRL"; 1443 }; 1444 1445 pinctrl_siopbi_default: siopbi_default { 1446 function = "SIOPBI"; 1447 groups = "SIOPBI"; 1448 }; 1449 1450 pinctrl_siopbo_default: siopbo_default { 1451 function = "SIOPBO"; 1452 groups = "SIOPBO"; 1453 }; 1454 1455 pinctrl_siopwreq_default: siopwreq_default { 1456 function = "SIOPWREQ"; 1457 groups = "SIOPWREQ"; 1458 }; 1459 1460 pinctrl_siopwrgd_default: siopwrgd_default { 1461 function = "SIOPWRGD"; 1462 groups = "SIOPWRGD"; 1463 }; 1464 1465 pinctrl_sios3_default: sios3_default { 1466 function = "SIOS3"; 1467 groups = "SIOS3"; 1468 }; 1469 1470 pinctrl_sios5_default: sios5_default { 1471 function = "SIOS5"; 1472 groups = "SIOS5"; 1473 }; 1474 1475 pinctrl_siosci_default: siosci_default { 1476 function = "SIOSCI"; 1477 groups = "SIOSCI"; 1478 }; 1479 1480 pinctrl_spi1_default: spi1_default { 1481 function = "SPI1"; 1482 groups = "SPI1"; 1483 }; 1484 1485 pinctrl_spi1cs1_default: spi1cs1_default { 1486 function = "SPI1CS1"; 1487 groups = "SPI1CS1"; 1488 }; 1489 1490 pinctrl_spi1debug_default: spi1debug_default { 1491 function = "SPI1DEBUG"; 1492 groups = "SPI1DEBUG"; 1493 }; 1494 1495 pinctrl_spi1passthru_default: spi1passthru_default { 1496 function = "SPI1PASSTHRU"; 1497 groups = "SPI1PASSTHRU"; 1498 }; 1499 1500 pinctrl_spi2ck_default: spi2ck_default { 1501 function = "SPI2CK"; 1502 groups = "SPI2CK"; 1503 }; 1504 1505 pinctrl_spi2cs0_default: spi2cs0_default { 1506 function = "SPI2CS0"; 1507 groups = "SPI2CS0"; 1508 }; 1509 1510 pinctrl_spi2cs1_default: spi2cs1_default { 1511 function = "SPI2CS1"; 1512 groups = "SPI2CS1"; 1513 }; 1514 1515 pinctrl_spi2miso_default: spi2miso_default { 1516 function = "SPI2MISO"; 1517 groups = "SPI2MISO"; 1518 }; 1519 1520 pinctrl_spi2mosi_default: spi2mosi_default { 1521 function = "SPI2MOSI"; 1522 groups = "SPI2MOSI"; 1523 }; 1524 1525 pinctrl_timer3_default: timer3_default { 1526 function = "TIMER3"; 1527 groups = "TIMER3"; 1528 }; 1529 1530 pinctrl_timer4_default: timer4_default { 1531 function = "TIMER4"; 1532 groups = "TIMER4"; 1533 }; 1534 1535 pinctrl_timer5_default: timer5_default { 1536 function = "TIMER5"; 1537 groups = "TIMER5"; 1538 }; 1539 1540 pinctrl_timer6_default: timer6_default { 1541 function = "TIMER6"; 1542 groups = "TIMER6"; 1543 }; 1544 1545 pinctrl_timer7_default: timer7_default { 1546 function = "TIMER7"; 1547 groups = "TIMER7"; 1548 }; 1549 1550 pinctrl_timer8_default: timer8_default { 1551 function = "TIMER8"; 1552 groups = "TIMER8"; 1553 }; 1554 1555 pinctrl_txd1_default: txd1_default { 1556 function = "TXD1"; 1557 groups = "TXD1"; 1558 }; 1559 1560 pinctrl_txd2_default: txd2_default { 1561 function = "TXD2"; 1562 groups = "TXD2"; 1563 }; 1564 1565 pinctrl_txd3_default: txd3_default { 1566 function = "TXD3"; 1567 groups = "TXD3"; 1568 }; 1569 1570 pinctrl_txd4_default: txd4_default { 1571 function = "TXD4"; 1572 groups = "TXD4"; 1573 }; 1574 1575 pinctrl_uart6_default: uart6_default { 1576 function = "UART6"; 1577 groups = "UART6"; 1578 }; 1579 1580 pinctrl_usbcki_default: usbcki_default { 1581 function = "USBCKI"; 1582 groups = "USBCKI"; 1583 }; 1584 1585 pinctrl_usb2ah_default: usb2ah_default { 1586 function = "USB2AH"; 1587 groups = "USB2AH"; 1588 }; 1589 1590 pinctrl_usb2ad_default: usb2ad_default { 1591 function = "USB2AD"; 1592 groups = "USB2AD"; 1593 }; 1594 1595 pinctrl_usb11bhid_default: usb11bhid_default { 1596 function = "USB11BHID"; 1597 groups = "USB11BHID"; 1598 }; 1599 1600 pinctrl_usb2bh_default: usb2bh_default { 1601 function = "USB2BH"; 1602 groups = "USB2BH"; 1603 }; 1604 1605 pinctrl_vgabiosrom_default: vgabiosrom_default { 1606 function = "VGABIOSROM"; 1607 groups = "VGABIOSROM"; 1608 }; 1609 1610 pinctrl_vgahs_default: vgahs_default { 1611 function = "VGAHS"; 1612 groups = "VGAHS"; 1613 }; 1614 1615 pinctrl_vgavs_default: vgavs_default { 1616 function = "VGAVS"; 1617 groups = "VGAVS"; 1618 }; 1619 1620 pinctrl_vpi24_default: vpi24_default { 1621 function = "VPI24"; 1622 groups = "VPI24"; 1623 }; 1624 1625 pinctrl_vpo_default: vpo_default { 1626 function = "VPO"; 1627 groups = "VPO"; 1628 }; 1629 1630 pinctrl_wdtrst1_default: wdtrst1_default { 1631 function = "WDTRST1"; 1632 groups = "WDTRST1"; 1633 }; 1634 1635 pinctrl_wdtrst2_default: wdtrst2_default { 1636 function = "WDTRST2"; 1637 groups = "WDTRST2"; 1638 }; 1639}; 1640