1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5/dts-v1/; 6 7#include "imx7d.dtsi" 8 9/ { 10 model = "Freescale i.MX7 SabreSD Board"; 11 compatible = "fsl,imx7d-sdb", "fsl,imx7d"; 12 13 chosen { 14 stdout-path = &uart1; 15 }; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x80000000 0x80000000>; 20 }; 21 22 gpio-keys { 23 compatible = "gpio-keys"; 24 pinctrl-names = "default"; 25 pinctrl-0 = <&pinctrl_gpio_keys>; 26 27 volume-up { 28 label = "Volume Up"; 29 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 30 linux,code = <KEY_VOLUMEUP>; 31 wakeup-source; 32 }; 33 34 volume-down { 35 label = "Volume Down"; 36 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; 37 linux,code = <KEY_VOLUMEDOWN>; 38 wakeup-source; 39 }; 40 }; 41 42 spi4 { 43 compatible = "spi-gpio"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_spi4>; 46 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; 47 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; 48 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 49 num-chipselects = <1>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 extended_io: gpio-expander@0 { 54 compatible = "fairchild,74hc595"; 55 gpio-controller; 56 #gpio-cells = <2>; 57 reg = <0>; 58 registers-number = <1>; 59 spi-max-frequency = <100000>; 60 }; 61 }; 62 63 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 64 compatible = "regulator-fixed"; 65 regulator-name = "usb_otg1_vbus"; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 69 enable-active-high; 70 }; 71 72 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 73 compatible = "regulator-fixed"; 74 regulator-name = "usb_otg2_vbus"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; 77 regulator-min-microvolt = <5000000>; 78 regulator-max-microvolt = <5000000>; 79 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 80 enable-active-high; 81 }; 82 83 reg_vref_1v8: regulator-vref-1v8 { 84 compatible = "regulator-fixed"; 85 regulator-name = "vref-1v8"; 86 regulator-min-microvolt = <1800000>; 87 regulator-max-microvolt = <1800000>; 88 }; 89 90 reg_brcm: regulator-brcm { 91 compatible = "regulator-fixed"; 92 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 regulator-name = "brcm_reg"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_brcm_reg>; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 startup-delay-us = <200000>; 100 }; 101 102 reg_lcd_3v3: regulator-lcd-3v3 { 103 compatible = "regulator-fixed"; 104 regulator-name = "lcd-3v3"; 105 regulator-min-microvolt = <3300000>; 106 regulator-max-microvolt = <3300000>; 107 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; 108 }; 109 110 reg_can2_3v3: regulator-can2-3v3 { 111 compatible = "regulator-fixed"; 112 regulator-name = "can2-3v3"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_flexcan2_reg>; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; 118 }; 119 120 reg_fec2_3v3: regulator-fec2-3v3 { 121 compatible = "regulator-fixed"; 122 regulator-name = "fec2-3v3"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_enet2_reg>; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; 128 }; 129 130 backlight: backlight { 131 compatible = "pwm-backlight"; 132 pwms = <&pwm1 0 5000000 0>; 133 brightness-levels = <0 4 8 16 32 64 128 255>; 134 default-brightness-level = <6>; 135 status = "okay"; 136 }; 137 138 panel { 139 compatible = "innolux,at043tn24"; 140 backlight = <&backlight>; 141 power-supply = <®_lcd_3v3>; 142 143 port { 144 panel_in: endpoint { 145 remote-endpoint = <&display_out>; 146 }; 147 }; 148 }; 149 150 sound { 151 compatible = "fsl,imx7d-evk-wm8960", 152 "fsl,imx-audio-wm8960"; 153 model = "wm8960-audio"; 154 audio-cpu = <&sai1>; 155 audio-codec = <&codec>; 156 hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; 157 audio-routing = 158 "Headphone Jack", "HP_L", 159 "Headphone Jack", "HP_R", 160 "Ext Spk", "SPK_LP", 161 "Ext Spk", "SPK_LN", 162 "Ext Spk", "SPK_RP", 163 "Ext Spk", "SPK_RN", 164 "LINPUT1", "AMIC", 165 "AMIC", "MICB"; 166 }; 167}; 168 169&adc1 { 170 vref-supply = <®_vref_1v8>; 171 status = "okay"; 172}; 173 174&adc2 { 175 vref-supply = <®_vref_1v8>; 176 status = "okay"; 177}; 178 179&cpu0 { 180 cpu-supply = <&sw1a_reg>; 181}; 182 183&cpu1 { 184 cpu-supply = <&sw1a_reg>; 185}; 186 187&ecspi3 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_ecspi3>; 190 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 191 status = "okay"; 192 193 tsc2046@0 { 194 compatible = "ti,tsc2046"; 195 reg = <0>; 196 spi-max-frequency = <1000000>; 197 pinctrl-names ="default"; 198 pinctrl-0 = <&pinctrl_tsc2046_pendown>; 199 interrupt-parent = <&gpio2>; 200 interrupts = <29 0>; 201 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; 202 touchscreen-max-pressure = <255>; 203 wakeup-source; 204 }; 205}; 206 207&fec1 { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_enet1>; 210 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 211 <&clks IMX7D_ENET1_TIME_ROOT_CLK>; 212 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 213 assigned-clock-rates = <0>, <100000000>; 214 phy-mode = "rgmii"; 215 phy-handle = <ðphy0>; 216 fsl,magic-packet; 217 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; 218 status = "okay"; 219 220 mdio { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 224 ethphy0: ethernet-phy@0 { 225 reg = <0>; 226 }; 227 228 ethphy1: ethernet-phy@1 { 229 reg = <1>; 230 }; 231 }; 232}; 233 234&fec2 { 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_enet2>; 237 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, 238 <&clks IMX7D_ENET2_TIME_ROOT_CLK>; 239 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 240 assigned-clock-rates = <0>, <100000000>; 241 phy-mode = "rgmii"; 242 phy-handle = <ðphy1>; 243 phy-supply = <®_fec2_3v3>; 244 fsl,magic-packet; 245 status = "okay"; 246}; 247 248&flexcan2 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_flexcan2>; 251 xceiver-supply = <®_can2_3v3>; 252 status = "okay"; 253}; 254 255&i2c1 { 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_i2c1>; 258 status = "okay"; 259 260 pmic: pfuze3000@8 { 261 compatible = "fsl,pfuze3000"; 262 reg = <0x08>; 263 264 regulators { 265 sw1a_reg: sw1a { 266 regulator-min-microvolt = <700000>; 267 regulator-max-microvolt = <1475000>; 268 regulator-boot-on; 269 regulator-always-on; 270 regulator-ramp-delay = <6250>; 271 }; 272 273 /* use sw1c_reg to align with pfuze100/pfuze200 */ 274 sw1c_reg: sw1b { 275 regulator-min-microvolt = <700000>; 276 regulator-max-microvolt = <1475000>; 277 regulator-boot-on; 278 regulator-always-on; 279 regulator-ramp-delay = <6250>; 280 }; 281 282 sw2_reg: sw2 { 283 regulator-min-microvolt = <1800000>; 284 regulator-max-microvolt = <1800000>; 285 regulator-boot-on; 286 regulator-always-on; 287 }; 288 289 sw3a_reg: sw3 { 290 regulator-min-microvolt = <900000>; 291 regulator-max-microvolt = <1650000>; 292 regulator-boot-on; 293 regulator-always-on; 294 }; 295 296 swbst_reg: swbst { 297 regulator-min-microvolt = <5000000>; 298 regulator-max-microvolt = <5150000>; 299 }; 300 301 snvs_reg: vsnvs { 302 regulator-min-microvolt = <1000000>; 303 regulator-max-microvolt = <3000000>; 304 regulator-boot-on; 305 regulator-always-on; 306 }; 307 308 vref_reg: vrefddr { 309 regulator-boot-on; 310 regulator-always-on; 311 }; 312 313 vgen1_reg: vldo1 { 314 regulator-min-microvolt = <1800000>; 315 regulator-max-microvolt = <3300000>; 316 regulator-always-on; 317 }; 318 319 vgen2_reg: vldo2 { 320 regulator-min-microvolt = <800000>; 321 regulator-max-microvolt = <1550000>; 322 }; 323 324 vgen3_reg: vccsd { 325 regulator-min-microvolt = <2850000>; 326 regulator-max-microvolt = <3300000>; 327 regulator-always-on; 328 }; 329 330 vgen4_reg: v33 { 331 regulator-min-microvolt = <2850000>; 332 regulator-max-microvolt = <3300000>; 333 regulator-always-on; 334 }; 335 336 vgen5_reg: vldo3 { 337 regulator-min-microvolt = <1800000>; 338 regulator-max-microvolt = <3300000>; 339 regulator-always-on; 340 }; 341 342 vgen6_reg: vldo4 { 343 regulator-min-microvolt = <2800000>; 344 regulator-max-microvolt = <2800000>; 345 regulator-always-on; 346 }; 347 }; 348 }; 349}; 350 351&i2c2 { 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_i2c2>; 354 status = "okay"; 355 356 mpl3115@60 { 357 compatible = "fsl,mpl3115"; 358 reg = <0x60>; 359 }; 360}; 361 362&i2c3 { 363 pinctrl-names = "default"; 364 pinctrl-0 = <&pinctrl_i2c3>; 365 status = "okay"; 366}; 367 368&i2c4 { 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_i2c4>; 371 status = "okay"; 372 373 codec: wm8960@1a { 374 compatible = "wlf,wm8960"; 375 reg = <0x1a>; 376 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 377 clock-names = "mclk"; 378 wlf,shared-lrclk; 379 wlf,hp-cfg = <2 2 3>; 380 wlf,gpio-cfg = <1 3>; 381 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, 382 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 383 <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 384 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 385 assigned-clock-rates = <0>, <884736000>, <12288000>; 386 }; 387}; 388 389&lcdif { 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_lcdif>; 392 status = "okay"; 393 394 port { 395 display_out: endpoint { 396 remote-endpoint = <&panel_in>; 397 }; 398 }; 399}; 400 401&pcie { 402 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; 403 status = "okay"; 404}; 405 406®_1p0d { 407 vin-supply = <&sw2_reg>; 408}; 409 410®_1p2 { 411 vin-supply = <&sw2_reg>; 412}; 413 414&sai1 { 415 pinctrl-names = "default"; 416 pinctrl-0 = <&pinctrl_sai1>; 417 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, 418 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 419 <&clks IMX7D_SAI1_ROOT_CLK>; 420 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 421 assigned-clock-rates = <0>, <884736000>, <36864000>; 422 status = "okay"; 423}; 424 425&sai3 { 426 pinctrl-names = "default"; 427 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; 428 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, 429 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 430 <&clks IMX7D_SAI3_ROOT_CLK>; 431 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 432 assigned-clock-rates = <0>, <884736000>, <36864000>; 433 status = "okay"; 434}; 435 436&snvs_pwrkey { 437 status = "okay"; 438}; 439 440&uart1 { 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pinctrl_uart1>; 443 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 444 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 445 status = "okay"; 446}; 447 448&uart6 { 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_uart6>; 451 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 452 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 453 uart-has-rtscts; 454 status = "okay"; 455}; 456 457&usbotg1 { 458 vbus-supply = <®_usb_otg1_vbus>; 459 status = "okay"; 460}; 461 462&usbotg2 { 463 vbus-supply = <®_usb_otg2_vbus>; 464 dr_mode = "host"; 465 status = "okay"; 466}; 467 468&usdhc1 { 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_usdhc1>; 471 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 472 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 473 wakeup-source; 474 keep-power-in-suspend; 475 status = "okay"; 476}; 477 478&usdhc2 { 479 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 480 pinctrl-0 = <&pinctrl_usdhc2>; 481 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 482 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 483 wakeup-source; 484 keep-power-in-suspend; 485 non-removable; 486 vmmc-supply = <®_brcm>; 487 fsl,tuning-step = <2>; 488 status = "okay"; 489}; 490 491&usdhc3 { 492 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 493 pinctrl-0 = <&pinctrl_usdhc3>; 494 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 495 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 496 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 497 assigned-clock-rates = <400000000>; 498 bus-width = <8>; 499 fsl,tuning-step = <2>; 500 non-removable; 501 status = "okay"; 502}; 503 504&wdog1 { 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pinctrl_wdog>; 507 fsl,ext-reset-output; 508}; 509 510&iomuxc { 511 pinctrl-names = "default"; 512 pinctrl-0 = <&pinctrl_hog>; 513 514 imx7d-sdb { 515 pinctrl_brcm_reg: brcmreggrp { 516 fsl,pins = < 517 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 518 >; 519 }; 520 521 pinctrl_ecspi3: ecspi3grp { 522 fsl,pins = < 523 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 524 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 525 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 526 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 527 >; 528 }; 529 530 pinctrl_enet1: enet1grp { 531 fsl,pins = < 532 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 533 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 534 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 535 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 536 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 537 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 538 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 539 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 540 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 541 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 542 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 543 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 544 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 545 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 546 >; 547 }; 548 549 pinctrl_enet2: enet2grp { 550 fsl,pins = < 551 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 552 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 553 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 554 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 555 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 556 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 557 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 558 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 559 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 560 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 561 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 562 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 563 >; 564 }; 565 566 pinctrl_enet2_reg: enet2reggrp { 567 fsl,pins = < 568 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 569 >; 570 }; 571 572 pinctrl_flexcan2: flexcan2grp { 573 fsl,pins = < 574 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 575 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 576 >; 577 }; 578 579 pinctrl_flexcan2_reg: flexcan2reggrp { 580 fsl,pins = < 581 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ 582 >; 583 }; 584 585 pinctrl_gpio_keys: gpio_keysgrp { 586 fsl,pins = < 587 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 588 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 589 >; 590 }; 591 592 pinctrl_hog: hoggrp { 593 fsl,pins = < 594 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ 595 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ 596 >; 597 }; 598 599 pinctrl_i2c1: i2c1grp { 600 fsl,pins = < 601 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 602 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 603 >; 604 }; 605 606 pinctrl_i2c2: i2c2grp { 607 fsl,pins = < 608 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 609 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 610 >; 611 }; 612 613 pinctrl_i2c3: i2c3grp { 614 fsl,pins = < 615 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 616 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 617 >; 618 }; 619 620 pinctrl_i2c4: i2c4grp { 621 fsl,pins = < 622 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 623 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 624 >; 625 }; 626 627 pinctrl_lcdif: lcdifgrp { 628 fsl,pins = < 629 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 630 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 631 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 632 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 633 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 634 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 635 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 636 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 637 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 638 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 639 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 640 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 641 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 642 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 643 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 644 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 645 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 646 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 647 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 648 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 649 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 650 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 651 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 652 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 653 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 654 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 655 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 656 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 657 MX7D_PAD_LCD_RESET__LCD_RESET 0x79 658 >; 659 }; 660 661 pinctrl_sai1: sai1grp { 662 fsl,pins = < 663 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f 664 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f 665 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f 666 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 667 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f 668 >; 669 }; 670 671 pinctrl_sai2: sai2grp { 672 fsl,pins = < 673 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f 674 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f 675 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 676 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f 677 >; 678 }; 679 680 pinctrl_sai3: sai3grp { 681 fsl,pins = < 682 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f 683 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f 684 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 685 >; 686 }; 687 688 pinctrl_spi4: spi4grp { 689 fsl,pins = < 690 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 691 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 692 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 693 >; 694 }; 695 696 pinctrl_tsc2046_pendown: tsc2046_pendown { 697 fsl,pins = < 698 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 699 >; 700 }; 701 702 pinctrl_uart1: uart1grp { 703 fsl,pins = < 704 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 705 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 706 >; 707 }; 708 709 pinctrl_uart5: uart5grp { 710 fsl,pins = < 711 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 712 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 713 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 714 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 715 >; 716 }; 717 718 pinctrl_uart6: uart6grp { 719 fsl,pins = < 720 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 721 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 722 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 723 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 724 >; 725 }; 726 727 pinctrl_usdhc1: usdhc1grp { 728 fsl,pins = < 729 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 730 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 731 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 732 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 733 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 734 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 735 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 736 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 737 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ 738 >; 739 }; 740 741 pinctrl_usdhc2: usdhc2grp { 742 fsl,pins = < 743 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 744 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 745 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 746 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 747 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 748 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 749 >; 750 }; 751 752 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 753 fsl,pins = < 754 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 755 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 756 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 757 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 758 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 759 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 760 >; 761 }; 762 763 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 764 fsl,pins = < 765 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 766 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 767 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 768 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 769 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 770 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 771 >; 772 }; 773 774 775 pinctrl_usdhc3: usdhc3grp { 776 fsl,pins = < 777 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 778 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 779 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 780 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 781 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 782 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 783 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 784 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 785 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 786 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 787 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 788 >; 789 }; 790 791 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 792 fsl,pins = < 793 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 794 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 795 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 796 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 797 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 798 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 799 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 800 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 801 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 802 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 803 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 804 >; 805 }; 806 807 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 808 fsl,pins = < 809 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 810 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 811 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 812 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 813 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 814 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 815 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 816 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 817 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 818 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 819 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 820 >; 821 }; 822 }; 823}; 824 825&pwm1 { 826 pinctrl-names = "default"; 827 pinctrl-0 = <&pinctrl_pwm1>; 828 status = "okay"; 829}; 830 831&iomuxc_lpsr { 832 pinctrl_wdog: wdoggrp { 833 fsl,pins = < 834 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 835 >; 836 }; 837 838 pinctrl_pwm1: pwm1grp { 839 fsl,pins = < 840 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 841 >; 842 }; 843 844 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { 845 fsl,pins = < 846 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 847 >; 848 }; 849 850 pinctrl_sai3_mclk: sai3grp_mclk { 851 fsl,pins = < 852 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f 853 >; 854 }; 855}; 856