1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/soc/rockchip,boot-mode.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 ethernet0 = &emac; 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 mshc0 = &emmc; 25 mshc1 = &mmc0; 26 mshc2 = &mmc1; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 spi0 = &spi0; 32 spi1 = &spi1; 33 }; 34 35 amba: bus { 36 compatible = "simple-bus"; 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges; 40 41 dmac1_s: dma-controller@20018000 { 42 compatible = "arm,pl330", "arm,primecell"; 43 reg = <0x20018000 0x4000>; 44 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 46 #dma-cells = <1>; 47 arm,pl330-broken-no-flushp; 48 arm,pl330-periph-burst; 49 clocks = <&cru ACLK_DMA1>; 50 clock-names = "apb_pclk"; 51 }; 52 53 dmac1_ns: dma-controller@2001c000 { 54 compatible = "arm,pl330", "arm,primecell"; 55 reg = <0x2001c000 0x4000>; 56 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 58 #dma-cells = <1>; 59 arm,pl330-broken-no-flushp; 60 arm,pl330-periph-burst; 61 clocks = <&cru ACLK_DMA1>; 62 clock-names = "apb_pclk"; 63 status = "disabled"; 64 }; 65 66 dmac2: dma-controller@20078000 { 67 compatible = "arm,pl330", "arm,primecell"; 68 reg = <0x20078000 0x4000>; 69 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 71 #dma-cells = <1>; 72 arm,pl330-broken-no-flushp; 73 arm,pl330-periph-burst; 74 clocks = <&cru ACLK_DMA2>; 75 clock-names = "apb_pclk"; 76 }; 77 }; 78 79 xin24m: oscillator { 80 compatible = "fixed-clock"; 81 clock-frequency = <24000000>; 82 #clock-cells = <0>; 83 clock-output-names = "xin24m"; 84 }; 85 86 gpu: gpu@10090000 { 87 compatible = "arm,mali-400"; 88 reg = <0x10090000 0x10000>; 89 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 90 clock-names = "bus", "core"; 91 assigned-clocks = <&cru ACLK_GPU>; 92 assigned-clock-rates = <100000000>; 93 resets = <&cru SRST_GPU>; 94 status = "disabled"; 95 }; 96 97 L2: cache-controller@10138000 { 98 compatible = "arm,pl310-cache"; 99 reg = <0x10138000 0x1000>; 100 cache-unified; 101 cache-level = <2>; 102 }; 103 104 scu@1013c000 { 105 compatible = "arm,cortex-a9-scu"; 106 reg = <0x1013c000 0x100>; 107 }; 108 109 global_timer: global-timer@1013c200 { 110 compatible = "arm,cortex-a9-global-timer"; 111 reg = <0x1013c200 0x20>; 112 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 113 clocks = <&cru CORE_PERI>; 114 status = "disabled"; 115 /* The clock source and the sched_clock provided by the arm_global_timer 116 * on Rockchip rk3066a/rk3188 are quite unstable because their rates 117 * depend on the CPU frequency. 118 * Keep the arm_global_timer disabled in order to have the 119 * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default. 120 */ 121 }; 122 123 local_timer: local-timer@1013c600 { 124 compatible = "arm,cortex-a9-twd-timer"; 125 reg = <0x1013c600 0x20>; 126 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 127 clocks = <&cru CORE_PERI>; 128 }; 129 130 gic: interrupt-controller@1013d000 { 131 compatible = "arm,cortex-a9-gic"; 132 interrupt-controller; 133 #interrupt-cells = <3>; 134 reg = <0x1013d000 0x1000>, 135 <0x1013c100 0x0100>; 136 }; 137 138 uart0: serial@10124000 { 139 compatible = "snps,dw-apb-uart"; 140 reg = <0x10124000 0x400>; 141 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 142 reg-shift = <2>; 143 reg-io-width = <1>; 144 clock-names = "baudclk", "apb_pclk"; 145 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 146 status = "disabled"; 147 }; 148 149 uart1: serial@10126000 { 150 compatible = "snps,dw-apb-uart"; 151 reg = <0x10126000 0x400>; 152 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 153 reg-shift = <2>; 154 reg-io-width = <1>; 155 clock-names = "baudclk", "apb_pclk"; 156 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 157 status = "disabled"; 158 }; 159 160 qos_gpu: qos@1012d000 { 161 compatible = "syscon"; 162 reg = <0x1012d000 0x20>; 163 }; 164 165 qos_vpu: qos@1012e000 { 166 compatible = "syscon"; 167 reg = <0x1012e000 0x20>; 168 }; 169 170 qos_lcdc0: qos@1012f000 { 171 compatible = "syscon"; 172 reg = <0x1012f000 0x20>; 173 }; 174 175 qos_cif0: qos@1012f080 { 176 compatible = "syscon"; 177 reg = <0x1012f080 0x20>; 178 }; 179 180 qos_ipp: qos@1012f100 { 181 compatible = "syscon"; 182 reg = <0x1012f100 0x20>; 183 }; 184 185 qos_lcdc1: qos@1012f180 { 186 compatible = "syscon"; 187 reg = <0x1012f180 0x20>; 188 }; 189 190 qos_cif1: qos@1012f200 { 191 compatible = "syscon"; 192 reg = <0x1012f200 0x20>; 193 }; 194 195 qos_rga: qos@1012f280 { 196 compatible = "syscon"; 197 reg = <0x1012f280 0x20>; 198 }; 199 200 usb_otg: usb@10180000 { 201 compatible = "rockchip,rk3066-usb", "snps,dwc2"; 202 reg = <0x10180000 0x40000>; 203 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&cru HCLK_OTG0>; 205 clock-names = "otg"; 206 dr_mode = "otg"; 207 g-np-tx-fifo-size = <16>; 208 g-rx-fifo-size = <275>; 209 g-tx-fifo-size = <256 128 128 64 64 32>; 210 phys = <&usbphy0>; 211 phy-names = "usb2-phy"; 212 status = "disabled"; 213 }; 214 215 usb_host: usb@101c0000 { 216 compatible = "snps,dwc2"; 217 reg = <0x101c0000 0x40000>; 218 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&cru HCLK_OTG1>; 220 clock-names = "otg"; 221 dr_mode = "host"; 222 phys = <&usbphy1>; 223 phy-names = "usb2-phy"; 224 status = "disabled"; 225 }; 226 227 emac: ethernet@10204000 { 228 compatible = "snps,arc-emac"; 229 reg = <0x10204000 0x3c>; 230 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 234 rockchip,grf = <&grf>; 235 236 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; 237 clock-names = "hclk", "macref"; 238 max-speed = <100>; 239 phy-mode = "rmii"; 240 241 status = "disabled"; 242 }; 243 244 mmc0: mmc@10214000 { 245 compatible = "rockchip,rk2928-dw-mshc"; 246 reg = <0x10214000 0x1000>; 247 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 249 clock-names = "biu", "ciu"; 250 dmas = <&dmac2 1>; 251 dma-names = "rx-tx"; 252 fifo-depth = <256>; 253 resets = <&cru SRST_SDMMC>; 254 reset-names = "reset"; 255 status = "disabled"; 256 }; 257 258 mmc1: mmc@10218000 { 259 compatible = "rockchip,rk2928-dw-mshc"; 260 reg = <0x10218000 0x1000>; 261 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 263 clock-names = "biu", "ciu"; 264 dmas = <&dmac2 3>; 265 dma-names = "rx-tx"; 266 fifo-depth = <256>; 267 resets = <&cru SRST_SDIO>; 268 reset-names = "reset"; 269 status = "disabled"; 270 }; 271 272 emmc: mmc@1021c000 { 273 compatible = "rockchip,rk2928-dw-mshc"; 274 reg = <0x1021c000 0x1000>; 275 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 277 clock-names = "biu", "ciu"; 278 dmas = <&dmac2 4>; 279 dma-names = "rx-tx"; 280 fifo-depth = <256>; 281 resets = <&cru SRST_EMMC>; 282 reset-names = "reset"; 283 status = "disabled"; 284 }; 285 286 pmu: pmu@20004000 { 287 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; 288 reg = <0x20004000 0x100>; 289 290 reboot-mode { 291 compatible = "syscon-reboot-mode"; 292 offset = <0x40>; 293 mode-normal = <BOOT_NORMAL>; 294 mode-recovery = <BOOT_RECOVERY>; 295 mode-bootloader = <BOOT_FASTBOOT>; 296 mode-loader = <BOOT_BL_DOWNLOAD>; 297 }; 298 }; 299 300 grf: grf@20008000 { 301 compatible = "syscon"; 302 reg = <0x20008000 0x200>; 303 }; 304 305 i2c0: i2c@2002d000 { 306 compatible = "rockchip,rk3066-i2c"; 307 reg = <0x2002d000 0x1000>; 308 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 312 rockchip,grf = <&grf>; 313 314 clock-names = "i2c"; 315 clocks = <&cru PCLK_I2C0>; 316 317 status = "disabled"; 318 }; 319 320 i2c1: i2c@2002f000 { 321 compatible = "rockchip,rk3066-i2c"; 322 reg = <0x2002f000 0x1000>; 323 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 327 rockchip,grf = <&grf>; 328 329 clocks = <&cru PCLK_I2C1>; 330 clock-names = "i2c"; 331 332 status = "disabled"; 333 }; 334 335 pwm0: pwm@20030000 { 336 compatible = "rockchip,rk2928-pwm"; 337 reg = <0x20030000 0x10>; 338 #pwm-cells = <2>; 339 clocks = <&cru PCLK_PWM01>; 340 status = "disabled"; 341 }; 342 343 pwm1: pwm@20030010 { 344 compatible = "rockchip,rk2928-pwm"; 345 reg = <0x20030010 0x10>; 346 #pwm-cells = <2>; 347 clocks = <&cru PCLK_PWM01>; 348 status = "disabled"; 349 }; 350 351 wdt: watchdog@2004c000 { 352 compatible = "snps,dw-wdt"; 353 reg = <0x2004c000 0x100>; 354 clocks = <&cru PCLK_WDT>; 355 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 356 status = "disabled"; 357 }; 358 359 pwm2: pwm@20050020 { 360 compatible = "rockchip,rk2928-pwm"; 361 reg = <0x20050020 0x10>; 362 #pwm-cells = <2>; 363 clocks = <&cru PCLK_PWM23>; 364 status = "disabled"; 365 }; 366 367 pwm3: pwm@20050030 { 368 compatible = "rockchip,rk2928-pwm"; 369 reg = <0x20050030 0x10>; 370 #pwm-cells = <2>; 371 clocks = <&cru PCLK_PWM23>; 372 status = "disabled"; 373 }; 374 375 i2c2: i2c@20056000 { 376 compatible = "rockchip,rk3066-i2c"; 377 reg = <0x20056000 0x1000>; 378 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 382 rockchip,grf = <&grf>; 383 384 clocks = <&cru PCLK_I2C2>; 385 clock-names = "i2c"; 386 387 status = "disabled"; 388 }; 389 390 i2c3: i2c@2005a000 { 391 compatible = "rockchip,rk3066-i2c"; 392 reg = <0x2005a000 0x1000>; 393 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 397 rockchip,grf = <&grf>; 398 399 clocks = <&cru PCLK_I2C3>; 400 clock-names = "i2c"; 401 402 status = "disabled"; 403 }; 404 405 i2c4: i2c@2005e000 { 406 compatible = "rockchip,rk3066-i2c"; 407 reg = <0x2005e000 0x1000>; 408 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 412 rockchip,grf = <&grf>; 413 414 clocks = <&cru PCLK_I2C4>; 415 clock-names = "i2c"; 416 417 status = "disabled"; 418 }; 419 420 uart2: serial@20064000 { 421 compatible = "snps,dw-apb-uart"; 422 reg = <0x20064000 0x400>; 423 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 424 reg-shift = <2>; 425 reg-io-width = <1>; 426 clock-names = "baudclk", "apb_pclk"; 427 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 428 status = "disabled"; 429 }; 430 431 uart3: serial@20068000 { 432 compatible = "snps,dw-apb-uart"; 433 reg = <0x20068000 0x400>; 434 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 435 reg-shift = <2>; 436 reg-io-width = <1>; 437 clock-names = "baudclk", "apb_pclk"; 438 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 439 status = "disabled"; 440 }; 441 442 saradc: saradc@2006c000 { 443 compatible = "rockchip,saradc"; 444 reg = <0x2006c000 0x100>; 445 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 446 #io-channel-cells = <1>; 447 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 448 clock-names = "saradc", "apb_pclk"; 449 resets = <&cru SRST_SARADC>; 450 reset-names = "saradc-apb"; 451 status = "disabled"; 452 }; 453 454 spi0: spi@20070000 { 455 compatible = "rockchip,rk3066-spi"; 456 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 457 clock-names = "spiclk", "apb_pclk"; 458 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 459 reg = <0x20070000 0x1000>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 dmas = <&dmac2 10>, <&dmac2 11>; 463 dma-names = "tx", "rx"; 464 status = "disabled"; 465 }; 466 467 spi1: spi@20074000 { 468 compatible = "rockchip,rk3066-spi"; 469 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 470 clock-names = "spiclk", "apb_pclk"; 471 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 472 reg = <0x20074000 0x1000>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 dmas = <&dmac2 12>, <&dmac2 13>; 476 dma-names = "tx", "rx"; 477 status = "disabled"; 478 }; 479}; 480