1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 bus@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42 #interrupt-cells = <2>; 43 interrupt-controller; 44 #gpio-cells = <2>; 45 gpio-controller; 46 }; 47 48 ethernet@2490000 { 49 compatible = "nvidia,tegra194-eqos", 50 "nvidia,tegra186-eqos", 51 "snps,dwc-qos-ethernet-4.10"; 52 reg = <0x02490000 0x10000>; 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55 <&bpmp TEGRA194_CLK_EQOS_AXI>, 56 <&bpmp TEGRA194_CLK_EQOS_RX>, 57 <&bpmp TEGRA194_CLK_EQOS_TX>, 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA194_RESET_EQOS>; 61 reset-names = "eqos"; 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64 interconnect-names = "dma-mem", "write"; 65 status = "disabled"; 66 67 snps,write-requests = <1>; 68 snps,read-requests = <3>; 69 snps,burst-map = <0x7>; 70 snps,txpbl = <16>; 71 snps,rxpbl = <8>; 72 }; 73 74 aconnect@2900000 { 75 compatible = "nvidia,tegra194-aconnect", 76 "nvidia,tegra210-aconnect"; 77 clocks = <&bpmp TEGRA194_CLK_APE>, 78 <&bpmp TEGRA194_CLK_APB2APE>; 79 clock-names = "ape", "apb2ape"; 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x02900000 0x02900000 0x200000>; 84 status = "disabled"; 85 86 adma: dma-controller@2930000 { 87 compatible = "nvidia,tegra194-adma", 88 "nvidia,tegra186-adma"; 89 reg = <0x02930000 0x20000>; 90 interrupt-parent = <&agic>; 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 123 #dma-cells = <1>; 124 clocks = <&bpmp TEGRA194_CLK_AHUB>; 125 clock-names = "d_audio"; 126 status = "disabled"; 127 }; 128 129 agic: interrupt-controller@2a40000 { 130 compatible = "nvidia,tegra194-agic", 131 "nvidia,tegra210-agic"; 132 #interrupt-cells = <3>; 133 interrupt-controller; 134 reg = <0x02a41000 0x1000>, 135 <0x02a42000 0x2000>; 136 interrupts = <GIC_SPI 145 137 (GIC_CPU_MASK_SIMPLE(4) | 138 IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA194_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 144 tegra_ahub: ahub@2900800 { 145 compatible = "nvidia,tegra194-ahub", 146 "nvidia,tegra186-ahub"; 147 reg = <0x02900800 0x800>; 148 clocks = <&bpmp TEGRA194_CLK_AHUB>; 149 clock-names = "ahub"; 150 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 151 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 ranges = <0x02900800 0x02900800 0x11800>; 155 status = "disabled"; 156 157 tegra_admaif: admaif@290f000 { 158 compatible = "nvidia,tegra194-admaif", 159 "nvidia,tegra186-admaif"; 160 reg = <0x0290f000 0x1000>; 161 dmas = <&adma 1>, <&adma 1>, 162 <&adma 2>, <&adma 2>, 163 <&adma 3>, <&adma 3>, 164 <&adma 4>, <&adma 4>, 165 <&adma 5>, <&adma 5>, 166 <&adma 6>, <&adma 6>, 167 <&adma 7>, <&adma 7>, 168 <&adma 8>, <&adma 8>, 169 <&adma 9>, <&adma 9>, 170 <&adma 10>, <&adma 10>, 171 <&adma 11>, <&adma 11>, 172 <&adma 12>, <&adma 12>, 173 <&adma 13>, <&adma 13>, 174 <&adma 14>, <&adma 14>, 175 <&adma 15>, <&adma 15>, 176 <&adma 16>, <&adma 16>, 177 <&adma 17>, <&adma 17>, 178 <&adma 18>, <&adma 18>, 179 <&adma 19>, <&adma 19>, 180 <&adma 20>, <&adma 20>; 181 dma-names = "rx1", "tx1", 182 "rx2", "tx2", 183 "rx3", "tx3", 184 "rx4", "tx4", 185 "rx5", "tx5", 186 "rx6", "tx6", 187 "rx7", "tx7", 188 "rx8", "tx8", 189 "rx9", "tx9", 190 "rx10", "tx10", 191 "rx11", "tx11", 192 "rx12", "tx12", 193 "rx13", "tx13", 194 "rx14", "tx14", 195 "rx15", "tx15", 196 "rx16", "tx16", 197 "rx17", "tx17", 198 "rx18", "tx18", 199 "rx19", "tx19", 200 "rx20", "tx20"; 201 status = "disabled"; 202 }; 203 204 tegra_i2s1: i2s@2901000 { 205 compatible = "nvidia,tegra194-i2s", 206 "nvidia,tegra210-i2s"; 207 reg = <0x2901000 0x100>; 208 clocks = <&bpmp TEGRA194_CLK_I2S1>, 209 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 210 clock-names = "i2s", "sync_input"; 211 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 212 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 213 assigned-clock-rates = <1536000>; 214 sound-name-prefix = "I2S1"; 215 status = "disabled"; 216 }; 217 218 tegra_i2s2: i2s@2901100 { 219 compatible = "nvidia,tegra194-i2s", 220 "nvidia,tegra210-i2s"; 221 reg = <0x2901100 0x100>; 222 clocks = <&bpmp TEGRA194_CLK_I2S2>, 223 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 224 clock-names = "i2s", "sync_input"; 225 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 226 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 227 assigned-clock-rates = <1536000>; 228 sound-name-prefix = "I2S2"; 229 status = "disabled"; 230 }; 231 232 tegra_i2s3: i2s@2901200 { 233 compatible = "nvidia,tegra194-i2s", 234 "nvidia,tegra210-i2s"; 235 reg = <0x2901200 0x100>; 236 clocks = <&bpmp TEGRA194_CLK_I2S3>, 237 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 238 clock-names = "i2s", "sync_input"; 239 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 240 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 241 assigned-clock-rates = <1536000>; 242 sound-name-prefix = "I2S3"; 243 status = "disabled"; 244 }; 245 246 tegra_i2s4: i2s@2901300 { 247 compatible = "nvidia,tegra194-i2s", 248 "nvidia,tegra210-i2s"; 249 reg = <0x2901300 0x100>; 250 clocks = <&bpmp TEGRA194_CLK_I2S4>, 251 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 252 clock-names = "i2s", "sync_input"; 253 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 254 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 255 assigned-clock-rates = <1536000>; 256 sound-name-prefix = "I2S4"; 257 status = "disabled"; 258 }; 259 260 tegra_i2s5: i2s@2901400 { 261 compatible = "nvidia,tegra194-i2s", 262 "nvidia,tegra210-i2s"; 263 reg = <0x2901400 0x100>; 264 clocks = <&bpmp TEGRA194_CLK_I2S5>, 265 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 266 clock-names = "i2s", "sync_input"; 267 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 268 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 269 assigned-clock-rates = <1536000>; 270 sound-name-prefix = "I2S5"; 271 status = "disabled"; 272 }; 273 274 tegra_i2s6: i2s@2901500 { 275 compatible = "nvidia,tegra194-i2s", 276 "nvidia,tegra210-i2s"; 277 reg = <0x2901500 0x100>; 278 clocks = <&bpmp TEGRA194_CLK_I2S6>, 279 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 280 clock-names = "i2s", "sync_input"; 281 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 282 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 283 assigned-clock-rates = <1536000>; 284 sound-name-prefix = "I2S6"; 285 status = "disabled"; 286 }; 287 288 tegra_dmic1: dmic@2904000 { 289 compatible = "nvidia,tegra194-dmic", 290 "nvidia,tegra210-dmic"; 291 reg = <0x2904000 0x100>; 292 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 293 clock-names = "dmic"; 294 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 295 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 296 assigned-clock-rates = <3072000>; 297 sound-name-prefix = "DMIC1"; 298 status = "disabled"; 299 }; 300 301 tegra_dmic2: dmic@2904100 { 302 compatible = "nvidia,tegra194-dmic", 303 "nvidia,tegra210-dmic"; 304 reg = <0x2904100 0x100>; 305 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 306 clock-names = "dmic"; 307 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 308 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 309 assigned-clock-rates = <3072000>; 310 sound-name-prefix = "DMIC2"; 311 status = "disabled"; 312 }; 313 314 tegra_dmic3: dmic@2904200 { 315 compatible = "nvidia,tegra194-dmic", 316 "nvidia,tegra210-dmic"; 317 reg = <0x2904200 0x100>; 318 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 319 clock-names = "dmic"; 320 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 321 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 322 assigned-clock-rates = <3072000>; 323 sound-name-prefix = "DMIC3"; 324 status = "disabled"; 325 }; 326 327 tegra_dmic4: dmic@2904300 { 328 compatible = "nvidia,tegra194-dmic", 329 "nvidia,tegra210-dmic"; 330 reg = <0x2904300 0x100>; 331 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 332 clock-names = "dmic"; 333 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 334 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 335 assigned-clock-rates = <3072000>; 336 sound-name-prefix = "DMIC4"; 337 status = "disabled"; 338 }; 339 340 tegra_dspk1: dspk@2905000 { 341 compatible = "nvidia,tegra194-dspk", 342 "nvidia,tegra186-dspk"; 343 reg = <0x2905000 0x100>; 344 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 345 clock-names = "dspk"; 346 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 347 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 348 assigned-clock-rates = <12288000>; 349 sound-name-prefix = "DSPK1"; 350 status = "disabled"; 351 }; 352 353 tegra_dspk2: dspk@2905100 { 354 compatible = "nvidia,tegra194-dspk", 355 "nvidia,tegra186-dspk"; 356 reg = <0x2905100 0x100>; 357 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 358 clock-names = "dspk"; 359 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 360 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 361 assigned-clock-rates = <12288000>; 362 sound-name-prefix = "DSPK2"; 363 status = "disabled"; 364 }; 365 }; 366 }; 367 368 pinmux: pinmux@2430000 { 369 compatible = "nvidia,tegra194-pinmux"; 370 reg = <0x2430000 0x17000>, 371 <0xc300000 0x4000>; 372 373 status = "okay"; 374 375 pex_rst_c5_out_state: pex_rst_c5_out { 376 pex_rst { 377 nvidia,pins = "pex_l5_rst_n_pgg1"; 378 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 379 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 380 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 381 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 382 nvidia,tristate = <TEGRA_PIN_DISABLE>; 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384 }; 385 }; 386 387 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 388 clkreq { 389 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 390 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 391 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 392 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 393 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 394 nvidia,tristate = <TEGRA_PIN_DISABLE>; 395 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 396 }; 397 }; 398 }; 399 400 mc: memory-controller@2c00000 { 401 compatible = "nvidia,tegra194-mc"; 402 reg = <0x02c00000 0x100000>, 403 <0x02b80000 0x040000>, 404 <0x01700000 0x100000>; 405 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 406 #interconnect-cells = <1>; 407 status = "disabled"; 408 409 #address-cells = <2>; 410 #size-cells = <2>; 411 412 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 413 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 414 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 415 416 /* 417 * Bit 39 of addresses passing through the memory 418 * controller selects the XBAR format used when memory 419 * is accessed. This is used to transparently access 420 * memory in the XBAR format used by the discrete GPU 421 * (bit 39 set) or Tegra (bit 39 clear). 422 * 423 * As a consequence, the operating system must ensure 424 * that bit 39 is never used implicitly, for example 425 * via an I/O virtual address mapping of an IOMMU. If 426 * devices require access to the XBAR switch, their 427 * drivers must set this bit explicitly. 428 * 429 * Limit the DMA range for memory clients to [38:0]. 430 */ 431 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 432 433 emc: external-memory-controller@2c60000 { 434 compatible = "nvidia,tegra194-emc"; 435 reg = <0x0 0x02c60000 0x0 0x90000>, 436 <0x0 0x01780000 0x0 0x80000>; 437 clocks = <&bpmp TEGRA194_CLK_EMC>; 438 clock-names = "emc"; 439 440 #interconnect-cells = <0>; 441 442 nvidia,bpmp = <&bpmp>; 443 }; 444 }; 445 446 uarta: serial@3100000 { 447 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 448 reg = <0x03100000 0x40>; 449 reg-shift = <2>; 450 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&bpmp TEGRA194_CLK_UARTA>; 452 clock-names = "serial"; 453 resets = <&bpmp TEGRA194_RESET_UARTA>; 454 reset-names = "serial"; 455 status = "disabled"; 456 }; 457 458 uartb: serial@3110000 { 459 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 460 reg = <0x03110000 0x40>; 461 reg-shift = <2>; 462 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&bpmp TEGRA194_CLK_UARTB>; 464 clock-names = "serial"; 465 resets = <&bpmp TEGRA194_RESET_UARTB>; 466 reset-names = "serial"; 467 status = "disabled"; 468 }; 469 470 uartd: serial@3130000 { 471 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 472 reg = <0x03130000 0x40>; 473 reg-shift = <2>; 474 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&bpmp TEGRA194_CLK_UARTD>; 476 clock-names = "serial"; 477 resets = <&bpmp TEGRA194_RESET_UARTD>; 478 reset-names = "serial"; 479 status = "disabled"; 480 }; 481 482 uarte: serial@3140000 { 483 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 484 reg = <0x03140000 0x40>; 485 reg-shift = <2>; 486 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&bpmp TEGRA194_CLK_UARTE>; 488 clock-names = "serial"; 489 resets = <&bpmp TEGRA194_RESET_UARTE>; 490 reset-names = "serial"; 491 status = "disabled"; 492 }; 493 494 uartf: serial@3150000 { 495 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 496 reg = <0x03150000 0x40>; 497 reg-shift = <2>; 498 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&bpmp TEGRA194_CLK_UARTF>; 500 clock-names = "serial"; 501 resets = <&bpmp TEGRA194_RESET_UARTF>; 502 reset-names = "serial"; 503 status = "disabled"; 504 }; 505 506 gen1_i2c: i2c@3160000 { 507 compatible = "nvidia,tegra194-i2c"; 508 reg = <0x03160000 0x10000>; 509 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 clocks = <&bpmp TEGRA194_CLK_I2C1>; 513 clock-names = "div-clk"; 514 resets = <&bpmp TEGRA194_RESET_I2C1>; 515 reset-names = "i2c"; 516 status = "disabled"; 517 }; 518 519 uarth: serial@3170000 { 520 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 521 reg = <0x03170000 0x40>; 522 reg-shift = <2>; 523 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&bpmp TEGRA194_CLK_UARTH>; 525 clock-names = "serial"; 526 resets = <&bpmp TEGRA194_RESET_UARTH>; 527 reset-names = "serial"; 528 status = "disabled"; 529 }; 530 531 cam_i2c: i2c@3180000 { 532 compatible = "nvidia,tegra194-i2c"; 533 reg = <0x03180000 0x10000>; 534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 clocks = <&bpmp TEGRA194_CLK_I2C3>; 538 clock-names = "div-clk"; 539 resets = <&bpmp TEGRA194_RESET_I2C3>; 540 reset-names = "i2c"; 541 status = "disabled"; 542 }; 543 544 /* shares pads with dpaux1 */ 545 dp_aux_ch1_i2c: i2c@3190000 { 546 compatible = "nvidia,tegra194-i2c"; 547 reg = <0x03190000 0x10000>; 548 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 clocks = <&bpmp TEGRA194_CLK_I2C4>; 552 clock-names = "div-clk"; 553 resets = <&bpmp TEGRA194_RESET_I2C4>; 554 reset-names = "i2c"; 555 pinctrl-0 = <&state_dpaux1_i2c>; 556 pinctrl-1 = <&state_dpaux1_off>; 557 pinctrl-names = "default", "idle"; 558 status = "disabled"; 559 }; 560 561 /* shares pads with dpaux0 */ 562 dp_aux_ch0_i2c: i2c@31b0000 { 563 compatible = "nvidia,tegra194-i2c"; 564 reg = <0x031b0000 0x10000>; 565 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&bpmp TEGRA194_CLK_I2C6>; 569 clock-names = "div-clk"; 570 resets = <&bpmp TEGRA194_RESET_I2C6>; 571 reset-names = "i2c"; 572 pinctrl-0 = <&state_dpaux0_i2c>; 573 pinctrl-1 = <&state_dpaux0_off>; 574 pinctrl-names = "default", "idle"; 575 status = "disabled"; 576 }; 577 578 /* shares pads with dpaux2 */ 579 dp_aux_ch2_i2c: i2c@31c0000 { 580 compatible = "nvidia,tegra194-i2c"; 581 reg = <0x031c0000 0x10000>; 582 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 clocks = <&bpmp TEGRA194_CLK_I2C7>; 586 clock-names = "div-clk"; 587 resets = <&bpmp TEGRA194_RESET_I2C7>; 588 reset-names = "i2c"; 589 pinctrl-0 = <&state_dpaux2_i2c>; 590 pinctrl-1 = <&state_dpaux2_off>; 591 pinctrl-names = "default", "idle"; 592 status = "disabled"; 593 }; 594 595 /* shares pads with dpaux3 */ 596 dp_aux_ch3_i2c: i2c@31e0000 { 597 compatible = "nvidia,tegra194-i2c"; 598 reg = <0x031e0000 0x10000>; 599 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 clocks = <&bpmp TEGRA194_CLK_I2C9>; 603 clock-names = "div-clk"; 604 resets = <&bpmp TEGRA194_RESET_I2C9>; 605 reset-names = "i2c"; 606 pinctrl-0 = <&state_dpaux3_i2c>; 607 pinctrl-1 = <&state_dpaux3_off>; 608 pinctrl-names = "default", "idle"; 609 status = "disabled"; 610 }; 611 612 pwm1: pwm@3280000 { 613 compatible = "nvidia,tegra194-pwm", 614 "nvidia,tegra186-pwm"; 615 reg = <0x3280000 0x10000>; 616 clocks = <&bpmp TEGRA194_CLK_PWM1>; 617 clock-names = "pwm"; 618 resets = <&bpmp TEGRA194_RESET_PWM1>; 619 reset-names = "pwm"; 620 status = "disabled"; 621 #pwm-cells = <2>; 622 }; 623 624 pwm2: pwm@3290000 { 625 compatible = "nvidia,tegra194-pwm", 626 "nvidia,tegra186-pwm"; 627 reg = <0x3290000 0x10000>; 628 clocks = <&bpmp TEGRA194_CLK_PWM2>; 629 clock-names = "pwm"; 630 resets = <&bpmp TEGRA194_RESET_PWM2>; 631 reset-names = "pwm"; 632 status = "disabled"; 633 #pwm-cells = <2>; 634 }; 635 636 pwm3: pwm@32a0000 { 637 compatible = "nvidia,tegra194-pwm", 638 "nvidia,tegra186-pwm"; 639 reg = <0x32a0000 0x10000>; 640 clocks = <&bpmp TEGRA194_CLK_PWM3>; 641 clock-names = "pwm"; 642 resets = <&bpmp TEGRA194_RESET_PWM3>; 643 reset-names = "pwm"; 644 status = "disabled"; 645 #pwm-cells = <2>; 646 }; 647 648 pwm5: pwm@32c0000 { 649 compatible = "nvidia,tegra194-pwm", 650 "nvidia,tegra186-pwm"; 651 reg = <0x32c0000 0x10000>; 652 clocks = <&bpmp TEGRA194_CLK_PWM5>; 653 clock-names = "pwm"; 654 resets = <&bpmp TEGRA194_RESET_PWM5>; 655 reset-names = "pwm"; 656 status = "disabled"; 657 #pwm-cells = <2>; 658 }; 659 660 pwm6: pwm@32d0000 { 661 compatible = "nvidia,tegra194-pwm", 662 "nvidia,tegra186-pwm"; 663 reg = <0x32d0000 0x10000>; 664 clocks = <&bpmp TEGRA194_CLK_PWM6>; 665 clock-names = "pwm"; 666 resets = <&bpmp TEGRA194_RESET_PWM6>; 667 reset-names = "pwm"; 668 status = "disabled"; 669 #pwm-cells = <2>; 670 }; 671 672 pwm7: pwm@32e0000 { 673 compatible = "nvidia,tegra194-pwm", 674 "nvidia,tegra186-pwm"; 675 reg = <0x32e0000 0x10000>; 676 clocks = <&bpmp TEGRA194_CLK_PWM7>; 677 clock-names = "pwm"; 678 resets = <&bpmp TEGRA194_RESET_PWM7>; 679 reset-names = "pwm"; 680 status = "disabled"; 681 #pwm-cells = <2>; 682 }; 683 684 pwm8: pwm@32f0000 { 685 compatible = "nvidia,tegra194-pwm", 686 "nvidia,tegra186-pwm"; 687 reg = <0x32f0000 0x10000>; 688 clocks = <&bpmp TEGRA194_CLK_PWM8>; 689 clock-names = "pwm"; 690 resets = <&bpmp TEGRA194_RESET_PWM8>; 691 reset-names = "pwm"; 692 status = "disabled"; 693 #pwm-cells = <2>; 694 }; 695 696 sdmmc1: mmc@3400000 { 697 compatible = "nvidia,tegra194-sdhci"; 698 reg = <0x03400000 0x10000>; 699 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 701 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 702 clock-names = "sdhci", "tmclk"; 703 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 704 reset-names = "sdhci"; 705 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 706 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 707 interconnect-names = "dma-mem", "write"; 708 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 709 <0x07>; 710 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 711 <0x07>; 712 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 713 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 714 <0x07>; 715 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 716 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 717 nvidia,default-tap = <0x9>; 718 nvidia,default-trim = <0x5>; 719 status = "disabled"; 720 }; 721 722 sdmmc3: mmc@3440000 { 723 compatible = "nvidia,tegra194-sdhci"; 724 reg = <0x03440000 0x10000>; 725 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 727 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 728 clock-names = "sdhci", "tmclk"; 729 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 730 reset-names = "sdhci"; 731 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 732 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 733 interconnect-names = "dma-mem", "write"; 734 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 735 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 736 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 737 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 738 <0x07>; 739 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 740 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 741 <0x07>; 742 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 743 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 744 nvidia,default-tap = <0x9>; 745 nvidia,default-trim = <0x5>; 746 status = "disabled"; 747 }; 748 749 sdmmc4: mmc@3460000 { 750 compatible = "nvidia,tegra194-sdhci"; 751 reg = <0x03460000 0x10000>; 752 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 754 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 755 clock-names = "sdhci", "tmclk"; 756 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 757 <&bpmp TEGRA194_CLK_PLLC4>; 758 assigned-clock-parents = 759 <&bpmp TEGRA194_CLK_PLLC4>; 760 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 761 reset-names = "sdhci"; 762 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 763 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 764 interconnect-names = "dma-mem", "write"; 765 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 766 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 767 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 768 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 769 <0x0a>; 770 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 771 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 772 <0x0a>; 773 nvidia,default-tap = <0x8>; 774 nvidia,default-trim = <0x14>; 775 nvidia,dqs-trim = <40>; 776 supports-cqe; 777 status = "disabled"; 778 }; 779 780 hda@3510000 { 781 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 782 reg = <0x3510000 0x10000>; 783 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&bpmp TEGRA194_CLK_HDA>, 785 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 786 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 787 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 788 resets = <&bpmp TEGRA194_RESET_HDA>, 789 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 790 reset-names = "hda", "hda2hdmi"; 791 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 792 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 793 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 794 interconnect-names = "dma-mem", "write"; 795 status = "disabled"; 796 }; 797 798 xusb_padctl: padctl@3520000 { 799 compatible = "nvidia,tegra194-xusb-padctl"; 800 reg = <0x03520000 0x1000>, 801 <0x03540000 0x1000>; 802 reg-names = "padctl", "ao"; 803 804 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 805 reset-names = "padctl"; 806 807 status = "disabled"; 808 809 pads { 810 usb2 { 811 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 812 clock-names = "trk"; 813 814 lanes { 815 usb2-0 { 816 nvidia,function = "xusb"; 817 status = "disabled"; 818 #phy-cells = <0>; 819 }; 820 821 usb2-1 { 822 nvidia,function = "xusb"; 823 status = "disabled"; 824 #phy-cells = <0>; 825 }; 826 827 usb2-2 { 828 nvidia,function = "xusb"; 829 status = "disabled"; 830 #phy-cells = <0>; 831 }; 832 833 usb2-3 { 834 nvidia,function = "xusb"; 835 status = "disabled"; 836 #phy-cells = <0>; 837 }; 838 }; 839 }; 840 841 usb3 { 842 lanes { 843 usb3-0 { 844 nvidia,function = "xusb"; 845 status = "disabled"; 846 #phy-cells = <0>; 847 }; 848 849 usb3-1 { 850 nvidia,function = "xusb"; 851 status = "disabled"; 852 #phy-cells = <0>; 853 }; 854 855 usb3-2 { 856 nvidia,function = "xusb"; 857 status = "disabled"; 858 #phy-cells = <0>; 859 }; 860 861 usb3-3 { 862 nvidia,function = "xusb"; 863 status = "disabled"; 864 #phy-cells = <0>; 865 }; 866 }; 867 }; 868 }; 869 870 ports { 871 usb2-0 { 872 status = "disabled"; 873 }; 874 875 usb2-1 { 876 status = "disabled"; 877 }; 878 879 usb2-2 { 880 status = "disabled"; 881 }; 882 883 usb2-3 { 884 status = "disabled"; 885 }; 886 887 usb3-0 { 888 status = "disabled"; 889 }; 890 891 usb3-1 { 892 status = "disabled"; 893 }; 894 895 usb3-2 { 896 status = "disabled"; 897 }; 898 899 usb3-3 { 900 status = "disabled"; 901 }; 902 }; 903 }; 904 905 usb@3550000 { 906 compatible = "nvidia,tegra194-xudc"; 907 reg = <0x03550000 0x8000>, 908 <0x03558000 0x1000>; 909 reg-names = "base", "fpci"; 910 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 912 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 913 <&bpmp TEGRA194_CLK_XUSB_SS>, 914 <&bpmp TEGRA194_CLK_XUSB_FS>; 915 clock-names = "dev", "ss", "ss_src", "fs_src"; 916 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 917 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 918 power-domain-names = "dev", "ss"; 919 nvidia,xusb-padctl = <&xusb_padctl>; 920 status = "disabled"; 921 }; 922 923 usb@3610000 { 924 compatible = "nvidia,tegra194-xusb"; 925 reg = <0x03610000 0x40000>, 926 <0x03600000 0x10000>; 927 reg-names = "hcd", "fpci"; 928 929 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 931 932 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 933 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 934 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 935 <&bpmp TEGRA194_CLK_XUSB_SS>, 936 <&bpmp TEGRA194_CLK_CLK_M>, 937 <&bpmp TEGRA194_CLK_XUSB_FS>, 938 <&bpmp TEGRA194_CLK_UTMIPLL>, 939 <&bpmp TEGRA194_CLK_CLK_M>, 940 <&bpmp TEGRA194_CLK_PLLE>; 941 clock-names = "xusb_host", "xusb_falcon_src", 942 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 943 "xusb_fs_src", "pll_u_480m", "clk_m", 944 "pll_e"; 945 946 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 947 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 948 power-domain-names = "xusb_host", "xusb_ss"; 949 950 nvidia,xusb-padctl = <&xusb_padctl>; 951 status = "disabled"; 952 }; 953 954 fuse@3820000 { 955 compatible = "nvidia,tegra194-efuse"; 956 reg = <0x03820000 0x10000>; 957 clocks = <&bpmp TEGRA194_CLK_FUSE>; 958 clock-names = "fuse"; 959 }; 960 961 gic: interrupt-controller@3881000 { 962 compatible = "arm,gic-400"; 963 #interrupt-cells = <3>; 964 interrupt-controller; 965 reg = <0x03881000 0x1000>, 966 <0x03882000 0x2000>, 967 <0x03884000 0x2000>, 968 <0x03886000 0x2000>; 969 interrupts = <GIC_PPI 9 970 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 971 interrupt-parent = <&gic>; 972 }; 973 974 cec@3960000 { 975 compatible = "nvidia,tegra194-cec"; 976 reg = <0x03960000 0x10000>; 977 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&bpmp TEGRA194_CLK_CEC>; 979 clock-names = "cec"; 980 status = "disabled"; 981 }; 982 983 hsp_top0: hsp@3c00000 { 984 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 985 reg = <0x03c00000 0xa0000>; 986 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 995 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 996 "shared3", "shared4", "shared5", "shared6", 997 "shared7"; 998 #mbox-cells = <2>; 999 }; 1000 1001 p2u_hsio_0: phy@3e10000 { 1002 compatible = "nvidia,tegra194-p2u"; 1003 reg = <0x03e10000 0x10000>; 1004 reg-names = "ctl"; 1005 1006 #phy-cells = <0>; 1007 }; 1008 1009 p2u_hsio_1: phy@3e20000 { 1010 compatible = "nvidia,tegra194-p2u"; 1011 reg = <0x03e20000 0x10000>; 1012 reg-names = "ctl"; 1013 1014 #phy-cells = <0>; 1015 }; 1016 1017 p2u_hsio_2: phy@3e30000 { 1018 compatible = "nvidia,tegra194-p2u"; 1019 reg = <0x03e30000 0x10000>; 1020 reg-names = "ctl"; 1021 1022 #phy-cells = <0>; 1023 }; 1024 1025 p2u_hsio_3: phy@3e40000 { 1026 compatible = "nvidia,tegra194-p2u"; 1027 reg = <0x03e40000 0x10000>; 1028 reg-names = "ctl"; 1029 1030 #phy-cells = <0>; 1031 }; 1032 1033 p2u_hsio_4: phy@3e50000 { 1034 compatible = "nvidia,tegra194-p2u"; 1035 reg = <0x03e50000 0x10000>; 1036 reg-names = "ctl"; 1037 1038 #phy-cells = <0>; 1039 }; 1040 1041 p2u_hsio_5: phy@3e60000 { 1042 compatible = "nvidia,tegra194-p2u"; 1043 reg = <0x03e60000 0x10000>; 1044 reg-names = "ctl"; 1045 1046 #phy-cells = <0>; 1047 }; 1048 1049 p2u_hsio_6: phy@3e70000 { 1050 compatible = "nvidia,tegra194-p2u"; 1051 reg = <0x03e70000 0x10000>; 1052 reg-names = "ctl"; 1053 1054 #phy-cells = <0>; 1055 }; 1056 1057 p2u_hsio_7: phy@3e80000 { 1058 compatible = "nvidia,tegra194-p2u"; 1059 reg = <0x03e80000 0x10000>; 1060 reg-names = "ctl"; 1061 1062 #phy-cells = <0>; 1063 }; 1064 1065 p2u_hsio_8: phy@3e90000 { 1066 compatible = "nvidia,tegra194-p2u"; 1067 reg = <0x03e90000 0x10000>; 1068 reg-names = "ctl"; 1069 1070 #phy-cells = <0>; 1071 }; 1072 1073 p2u_hsio_9: phy@3ea0000 { 1074 compatible = "nvidia,tegra194-p2u"; 1075 reg = <0x03ea0000 0x10000>; 1076 reg-names = "ctl"; 1077 1078 #phy-cells = <0>; 1079 }; 1080 1081 p2u_nvhs_0: phy@3eb0000 { 1082 compatible = "nvidia,tegra194-p2u"; 1083 reg = <0x03eb0000 0x10000>; 1084 reg-names = "ctl"; 1085 1086 #phy-cells = <0>; 1087 }; 1088 1089 p2u_nvhs_1: phy@3ec0000 { 1090 compatible = "nvidia,tegra194-p2u"; 1091 reg = <0x03ec0000 0x10000>; 1092 reg-names = "ctl"; 1093 1094 #phy-cells = <0>; 1095 }; 1096 1097 p2u_nvhs_2: phy@3ed0000 { 1098 compatible = "nvidia,tegra194-p2u"; 1099 reg = <0x03ed0000 0x10000>; 1100 reg-names = "ctl"; 1101 1102 #phy-cells = <0>; 1103 }; 1104 1105 p2u_nvhs_3: phy@3ee0000 { 1106 compatible = "nvidia,tegra194-p2u"; 1107 reg = <0x03ee0000 0x10000>; 1108 reg-names = "ctl"; 1109 1110 #phy-cells = <0>; 1111 }; 1112 1113 p2u_nvhs_4: phy@3ef0000 { 1114 compatible = "nvidia,tegra194-p2u"; 1115 reg = <0x03ef0000 0x10000>; 1116 reg-names = "ctl"; 1117 1118 #phy-cells = <0>; 1119 }; 1120 1121 p2u_nvhs_5: phy@3f00000 { 1122 compatible = "nvidia,tegra194-p2u"; 1123 reg = <0x03f00000 0x10000>; 1124 reg-names = "ctl"; 1125 1126 #phy-cells = <0>; 1127 }; 1128 1129 p2u_nvhs_6: phy@3f10000 { 1130 compatible = "nvidia,tegra194-p2u"; 1131 reg = <0x03f10000 0x10000>; 1132 reg-names = "ctl"; 1133 1134 #phy-cells = <0>; 1135 }; 1136 1137 p2u_nvhs_7: phy@3f20000 { 1138 compatible = "nvidia,tegra194-p2u"; 1139 reg = <0x03f20000 0x10000>; 1140 reg-names = "ctl"; 1141 1142 #phy-cells = <0>; 1143 }; 1144 1145 p2u_hsio_10: phy@3f30000 { 1146 compatible = "nvidia,tegra194-p2u"; 1147 reg = <0x03f30000 0x10000>; 1148 reg-names = "ctl"; 1149 1150 #phy-cells = <0>; 1151 }; 1152 1153 p2u_hsio_11: phy@3f40000 { 1154 compatible = "nvidia,tegra194-p2u"; 1155 reg = <0x03f40000 0x10000>; 1156 reg-names = "ctl"; 1157 1158 #phy-cells = <0>; 1159 }; 1160 1161 hsp_aon: hsp@c150000 { 1162 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1163 reg = <0x0c150000 0x90000>; 1164 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1168 /* 1169 * Shared interrupt 0 is routed only to AON/SPE, so 1170 * we only have 4 shared interrupts for the CCPLEX. 1171 */ 1172 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1173 #mbox-cells = <2>; 1174 }; 1175 1176 gen2_i2c: i2c@c240000 { 1177 compatible = "nvidia,tegra194-i2c"; 1178 reg = <0x0c240000 0x10000>; 1179 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1183 clock-names = "div-clk"; 1184 resets = <&bpmp TEGRA194_RESET_I2C2>; 1185 reset-names = "i2c"; 1186 status = "disabled"; 1187 }; 1188 1189 gen8_i2c: i2c@c250000 { 1190 compatible = "nvidia,tegra194-i2c"; 1191 reg = <0x0c250000 0x10000>; 1192 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1196 clock-names = "div-clk"; 1197 resets = <&bpmp TEGRA194_RESET_I2C8>; 1198 reset-names = "i2c"; 1199 status = "disabled"; 1200 }; 1201 1202 uartc: serial@c280000 { 1203 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1204 reg = <0x0c280000 0x40>; 1205 reg-shift = <2>; 1206 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1208 clock-names = "serial"; 1209 resets = <&bpmp TEGRA194_RESET_UARTC>; 1210 reset-names = "serial"; 1211 status = "disabled"; 1212 }; 1213 1214 uartg: serial@c290000 { 1215 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1216 reg = <0x0c290000 0x40>; 1217 reg-shift = <2>; 1218 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1220 clock-names = "serial"; 1221 resets = <&bpmp TEGRA194_RESET_UARTG>; 1222 reset-names = "serial"; 1223 status = "disabled"; 1224 }; 1225 1226 rtc: rtc@c2a0000 { 1227 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1228 reg = <0x0c2a0000 0x10000>; 1229 interrupt-parent = <&pmc>; 1230 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1232 clock-names = "rtc"; 1233 status = "disabled"; 1234 }; 1235 1236 gpio_aon: gpio@c2f0000 { 1237 compatible = "nvidia,tegra194-gpio-aon"; 1238 reg-names = "security", "gpio"; 1239 reg = <0xc2f0000 0x1000>, 1240 <0xc2f1000 0x1000>; 1241 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1242 gpio-controller; 1243 #gpio-cells = <2>; 1244 interrupt-controller; 1245 #interrupt-cells = <2>; 1246 }; 1247 1248 pwm4: pwm@c340000 { 1249 compatible = "nvidia,tegra194-pwm", 1250 "nvidia,tegra186-pwm"; 1251 reg = <0xc340000 0x10000>; 1252 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1253 clock-names = "pwm"; 1254 resets = <&bpmp TEGRA194_RESET_PWM4>; 1255 reset-names = "pwm"; 1256 status = "disabled"; 1257 #pwm-cells = <2>; 1258 }; 1259 1260 pmc: pmc@c360000 { 1261 compatible = "nvidia,tegra194-pmc"; 1262 reg = <0x0c360000 0x10000>, 1263 <0x0c370000 0x10000>, 1264 <0x0c380000 0x10000>, 1265 <0x0c390000 0x10000>, 1266 <0x0c3a0000 0x10000>; 1267 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1268 1269 #interrupt-cells = <2>; 1270 interrupt-controller; 1271 }; 1272 1273 host1x@13e00000 { 1274 compatible = "nvidia,tegra194-host1x"; 1275 reg = <0x13e00000 0x10000>, 1276 <0x13e10000 0x10000>; 1277 reg-names = "hypervisor", "vm"; 1278 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1280 interrupt-names = "syncpt", "host1x"; 1281 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1282 clock-names = "host1x"; 1283 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1284 reset-names = "host1x"; 1285 1286 #address-cells = <1>; 1287 #size-cells = <1>; 1288 1289 ranges = <0x15000000 0x15000000 0x01000000>; 1290 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1291 interconnect-names = "dma-mem"; 1292 1293 display-hub@15200000 { 1294 compatible = "nvidia,tegra194-display"; 1295 reg = <0x15200000 0x00040000>; 1296 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1297 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1298 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1299 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1300 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1301 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1302 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1303 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1304 "wgrp3", "wgrp4", "wgrp5"; 1305 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1306 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1307 clock-names = "disp", "hub"; 1308 status = "disabled"; 1309 1310 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1311 1312 #address-cells = <1>; 1313 #size-cells = <1>; 1314 1315 ranges = <0x15200000 0x15200000 0x40000>; 1316 1317 display@15200000 { 1318 compatible = "nvidia,tegra194-dc"; 1319 reg = <0x15200000 0x10000>; 1320 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1322 clock-names = "dc"; 1323 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1324 reset-names = "dc"; 1325 1326 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1327 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1328 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1329 interconnect-names = "dma-mem", "read-1"; 1330 1331 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1332 nvidia,head = <0>; 1333 }; 1334 1335 display@15210000 { 1336 compatible = "nvidia,tegra194-dc"; 1337 reg = <0x15210000 0x10000>; 1338 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1340 clock-names = "dc"; 1341 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1342 reset-names = "dc"; 1343 1344 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1345 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1346 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1347 interconnect-names = "dma-mem", "read-1"; 1348 1349 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1350 nvidia,head = <1>; 1351 }; 1352 1353 display@15220000 { 1354 compatible = "nvidia,tegra194-dc"; 1355 reg = <0x15220000 0x10000>; 1356 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1358 clock-names = "dc"; 1359 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1360 reset-names = "dc"; 1361 1362 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1363 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1364 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1365 interconnect-names = "dma-mem", "read-1"; 1366 1367 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1368 nvidia,head = <2>; 1369 }; 1370 1371 display@15230000 { 1372 compatible = "nvidia,tegra194-dc"; 1373 reg = <0x15230000 0x10000>; 1374 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1375 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1376 clock-names = "dc"; 1377 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1378 reset-names = "dc"; 1379 1380 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1381 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1382 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1383 interconnect-names = "dma-mem", "read-1"; 1384 1385 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1386 nvidia,head = <3>; 1387 }; 1388 }; 1389 1390 vic@15340000 { 1391 compatible = "nvidia,tegra194-vic"; 1392 reg = <0x15340000 0x00040000>; 1393 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1394 clocks = <&bpmp TEGRA194_CLK_VIC>; 1395 clock-names = "vic"; 1396 resets = <&bpmp TEGRA194_RESET_VIC>; 1397 reset-names = "vic"; 1398 1399 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1400 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1401 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1402 interconnect-names = "dma-mem", "write"; 1403 }; 1404 1405 dpaux0: dpaux@155c0000 { 1406 compatible = "nvidia,tegra194-dpaux"; 1407 reg = <0x155c0000 0x10000>; 1408 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1409 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1410 <&bpmp TEGRA194_CLK_PLLDP>; 1411 clock-names = "dpaux", "parent"; 1412 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1413 reset-names = "dpaux"; 1414 status = "disabled"; 1415 1416 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1417 1418 state_dpaux0_aux: pinmux-aux { 1419 groups = "dpaux-io"; 1420 function = "aux"; 1421 }; 1422 1423 state_dpaux0_i2c: pinmux-i2c { 1424 groups = "dpaux-io"; 1425 function = "i2c"; 1426 }; 1427 1428 state_dpaux0_off: pinmux-off { 1429 groups = "dpaux-io"; 1430 function = "off"; 1431 }; 1432 1433 i2c-bus { 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 }; 1437 }; 1438 1439 dpaux1: dpaux@155d0000 { 1440 compatible = "nvidia,tegra194-dpaux"; 1441 reg = <0x155d0000 0x10000>; 1442 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1443 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1444 <&bpmp TEGRA194_CLK_PLLDP>; 1445 clock-names = "dpaux", "parent"; 1446 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1447 reset-names = "dpaux"; 1448 status = "disabled"; 1449 1450 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1451 1452 state_dpaux1_aux: pinmux-aux { 1453 groups = "dpaux-io"; 1454 function = "aux"; 1455 }; 1456 1457 state_dpaux1_i2c: pinmux-i2c { 1458 groups = "dpaux-io"; 1459 function = "i2c"; 1460 }; 1461 1462 state_dpaux1_off: pinmux-off { 1463 groups = "dpaux-io"; 1464 function = "off"; 1465 }; 1466 1467 i2c-bus { 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 }; 1471 }; 1472 1473 dpaux2: dpaux@155e0000 { 1474 compatible = "nvidia,tegra194-dpaux"; 1475 reg = <0x155e0000 0x10000>; 1476 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1478 <&bpmp TEGRA194_CLK_PLLDP>; 1479 clock-names = "dpaux", "parent"; 1480 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1481 reset-names = "dpaux"; 1482 status = "disabled"; 1483 1484 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1485 1486 state_dpaux2_aux: pinmux-aux { 1487 groups = "dpaux-io"; 1488 function = "aux"; 1489 }; 1490 1491 state_dpaux2_i2c: pinmux-i2c { 1492 groups = "dpaux-io"; 1493 function = "i2c"; 1494 }; 1495 1496 state_dpaux2_off: pinmux-off { 1497 groups = "dpaux-io"; 1498 function = "off"; 1499 }; 1500 1501 i2c-bus { 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 }; 1505 }; 1506 1507 dpaux3: dpaux@155f0000 { 1508 compatible = "nvidia,tegra194-dpaux"; 1509 reg = <0x155f0000 0x10000>; 1510 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1511 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1512 <&bpmp TEGRA194_CLK_PLLDP>; 1513 clock-names = "dpaux", "parent"; 1514 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1515 reset-names = "dpaux"; 1516 status = "disabled"; 1517 1518 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1519 1520 state_dpaux3_aux: pinmux-aux { 1521 groups = "dpaux-io"; 1522 function = "aux"; 1523 }; 1524 1525 state_dpaux3_i2c: pinmux-i2c { 1526 groups = "dpaux-io"; 1527 function = "i2c"; 1528 }; 1529 1530 state_dpaux3_off: pinmux-off { 1531 groups = "dpaux-io"; 1532 function = "off"; 1533 }; 1534 1535 i2c-bus { 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 }; 1539 }; 1540 1541 sor0: sor@15b00000 { 1542 compatible = "nvidia,tegra194-sor"; 1543 reg = <0x15b00000 0x40000>; 1544 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1545 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1546 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1547 <&bpmp TEGRA194_CLK_PLLD>, 1548 <&bpmp TEGRA194_CLK_PLLDP>, 1549 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1550 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1551 clock-names = "sor", "out", "parent", "dp", "safe", 1552 "pad"; 1553 resets = <&bpmp TEGRA194_RESET_SOR0>; 1554 reset-names = "sor"; 1555 pinctrl-0 = <&state_dpaux0_aux>; 1556 pinctrl-1 = <&state_dpaux0_i2c>; 1557 pinctrl-2 = <&state_dpaux0_off>; 1558 pinctrl-names = "aux", "i2c", "off"; 1559 status = "disabled"; 1560 1561 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1562 nvidia,interface = <0>; 1563 }; 1564 1565 sor1: sor@15b40000 { 1566 compatible = "nvidia,tegra194-sor"; 1567 reg = <0x15b40000 0x40000>; 1568 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1569 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1570 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1571 <&bpmp TEGRA194_CLK_PLLD2>, 1572 <&bpmp TEGRA194_CLK_PLLDP>, 1573 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1574 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1575 clock-names = "sor", "out", "parent", "dp", "safe", 1576 "pad"; 1577 resets = <&bpmp TEGRA194_RESET_SOR1>; 1578 reset-names = "sor"; 1579 pinctrl-0 = <&state_dpaux1_aux>; 1580 pinctrl-1 = <&state_dpaux1_i2c>; 1581 pinctrl-2 = <&state_dpaux1_off>; 1582 pinctrl-names = "aux", "i2c", "off"; 1583 status = "disabled"; 1584 1585 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1586 nvidia,interface = <1>; 1587 }; 1588 1589 sor2: sor@15b80000 { 1590 compatible = "nvidia,tegra194-sor"; 1591 reg = <0x15b80000 0x40000>; 1592 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1593 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1594 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1595 <&bpmp TEGRA194_CLK_PLLD3>, 1596 <&bpmp TEGRA194_CLK_PLLDP>, 1597 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1598 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1599 clock-names = "sor", "out", "parent", "dp", "safe", 1600 "pad"; 1601 resets = <&bpmp TEGRA194_RESET_SOR2>; 1602 reset-names = "sor"; 1603 pinctrl-0 = <&state_dpaux2_aux>; 1604 pinctrl-1 = <&state_dpaux2_i2c>; 1605 pinctrl-2 = <&state_dpaux2_off>; 1606 pinctrl-names = "aux", "i2c", "off"; 1607 status = "disabled"; 1608 1609 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1610 nvidia,interface = <2>; 1611 }; 1612 1613 sor3: sor@15bc0000 { 1614 compatible = "nvidia,tegra194-sor"; 1615 reg = <0x15bc0000 0x40000>; 1616 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1617 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1618 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1619 <&bpmp TEGRA194_CLK_PLLD4>, 1620 <&bpmp TEGRA194_CLK_PLLDP>, 1621 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1622 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1623 clock-names = "sor", "out", "parent", "dp", "safe", 1624 "pad"; 1625 resets = <&bpmp TEGRA194_RESET_SOR3>; 1626 reset-names = "sor"; 1627 pinctrl-0 = <&state_dpaux3_aux>; 1628 pinctrl-1 = <&state_dpaux3_i2c>; 1629 pinctrl-2 = <&state_dpaux3_off>; 1630 pinctrl-names = "aux", "i2c", "off"; 1631 status = "disabled"; 1632 1633 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1634 nvidia,interface = <3>; 1635 }; 1636 }; 1637 1638 gpu@17000000 { 1639 compatible = "nvidia,gv11b"; 1640 reg = <0x17000000 0x1000000>, 1641 <0x18000000 0x1000000>; 1642 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1644 interrupt-names = "stall", "nonstall"; 1645 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 1646 <&bpmp TEGRA194_CLK_GPU_PWR>, 1647 <&bpmp TEGRA194_CLK_FUSE>; 1648 clock-names = "gpu", "pwr", "fuse"; 1649 resets = <&bpmp TEGRA194_RESET_GPU>; 1650 reset-names = "gpu"; 1651 dma-coherent; 1652 1653 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 1654 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 1655 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 1656 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 1657 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 1658 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 1659 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 1660 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 1661 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 1662 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 1663 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 1664 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 1665 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 1666 interconnect-names = "dma-mem", "read-0-hp", "write-0", 1667 "read-1", "read-1-hp", "write-1", 1668 "read-2", "read-2-hp", "write-2", 1669 "read-3", "read-3-hp", "write-3"; 1670 }; 1671 }; 1672 1673 pcie@14100000 { 1674 compatible = "nvidia,tegra194-pcie"; 1675 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1676 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1677 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1678 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1679 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1680 reg-names = "appl", "config", "atu_dma", "dbi"; 1681 1682 status = "disabled"; 1683 1684 #address-cells = <3>; 1685 #size-cells = <2>; 1686 device_type = "pci"; 1687 num-lanes = <1>; 1688 num-viewport = <8>; 1689 linux,pci-domain = <1>; 1690 1691 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1692 clock-names = "core"; 1693 1694 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1695 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1696 reset-names = "apb", "core"; 1697 1698 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1699 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1700 interrupt-names = "intr", "msi"; 1701 1702 #interrupt-cells = <1>; 1703 interrupt-map-mask = <0 0 0 0>; 1704 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1705 1706 nvidia,bpmp = <&bpmp 1>; 1707 1708 nvidia,aspm-cmrt-us = <60>; 1709 nvidia,aspm-pwr-on-t-us = <20>; 1710 nvidia,aspm-l0s-entrance-latency-us = <3>; 1711 1712 bus-range = <0x0 0xff>; 1713 1714 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1715 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1716 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1717 1718 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1719 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1720 interconnect-names = "read", "write"; 1721 }; 1722 1723 pcie@14120000 { 1724 compatible = "nvidia,tegra194-pcie"; 1725 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1726 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1727 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1728 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1729 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1730 reg-names = "appl", "config", "atu_dma", "dbi"; 1731 1732 status = "disabled"; 1733 1734 #address-cells = <3>; 1735 #size-cells = <2>; 1736 device_type = "pci"; 1737 num-lanes = <1>; 1738 num-viewport = <8>; 1739 linux,pci-domain = <2>; 1740 1741 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1742 clock-names = "core"; 1743 1744 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1745 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1746 reset-names = "apb", "core"; 1747 1748 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1749 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1750 interrupt-names = "intr", "msi"; 1751 1752 #interrupt-cells = <1>; 1753 interrupt-map-mask = <0 0 0 0>; 1754 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1755 1756 nvidia,bpmp = <&bpmp 2>; 1757 1758 nvidia,aspm-cmrt-us = <60>; 1759 nvidia,aspm-pwr-on-t-us = <20>; 1760 nvidia,aspm-l0s-entrance-latency-us = <3>; 1761 1762 bus-range = <0x0 0xff>; 1763 1764 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1765 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1766 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1767 1768 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1769 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1770 interconnect-names = "read", "write"; 1771 }; 1772 1773 pcie@14140000 { 1774 compatible = "nvidia,tegra194-pcie"; 1775 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1776 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1777 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1778 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1779 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1780 reg-names = "appl", "config", "atu_dma", "dbi"; 1781 1782 status = "disabled"; 1783 1784 #address-cells = <3>; 1785 #size-cells = <2>; 1786 device_type = "pci"; 1787 num-lanes = <1>; 1788 num-viewport = <8>; 1789 linux,pci-domain = <3>; 1790 1791 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1792 clock-names = "core"; 1793 1794 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1795 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1796 reset-names = "apb", "core"; 1797 1798 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1799 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1800 interrupt-names = "intr", "msi"; 1801 1802 #interrupt-cells = <1>; 1803 interrupt-map-mask = <0 0 0 0>; 1804 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1805 1806 nvidia,bpmp = <&bpmp 3>; 1807 1808 nvidia,aspm-cmrt-us = <60>; 1809 nvidia,aspm-pwr-on-t-us = <20>; 1810 nvidia,aspm-l0s-entrance-latency-us = <3>; 1811 1812 bus-range = <0x0 0xff>; 1813 1814 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1815 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 1816 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1817 1818 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1819 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1820 interconnect-names = "read", "write"; 1821 }; 1822 1823 pcie@14160000 { 1824 compatible = "nvidia,tegra194-pcie"; 1825 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1826 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1827 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1828 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1829 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1830 reg-names = "appl", "config", "atu_dma", "dbi"; 1831 1832 status = "disabled"; 1833 1834 #address-cells = <3>; 1835 #size-cells = <2>; 1836 device_type = "pci"; 1837 num-lanes = <4>; 1838 num-viewport = <8>; 1839 linux,pci-domain = <4>; 1840 1841 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1842 clock-names = "core"; 1843 1844 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1845 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1846 reset-names = "apb", "core"; 1847 1848 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1849 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1850 interrupt-names = "intr", "msi"; 1851 1852 #interrupt-cells = <1>; 1853 interrupt-map-mask = <0 0 0 0>; 1854 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1855 1856 nvidia,bpmp = <&bpmp 4>; 1857 1858 nvidia,aspm-cmrt-us = <60>; 1859 nvidia,aspm-pwr-on-t-us = <20>; 1860 nvidia,aspm-l0s-entrance-latency-us = <3>; 1861 1862 bus-range = <0x0 0xff>; 1863 1864 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1865 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1866 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1867 1868 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1869 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1870 interconnect-names = "read", "write"; 1871 }; 1872 1873 pcie@14180000 { 1874 compatible = "nvidia,tegra194-pcie"; 1875 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1876 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1877 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1878 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1879 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1880 reg-names = "appl", "config", "atu_dma", "dbi"; 1881 1882 status = "disabled"; 1883 1884 #address-cells = <3>; 1885 #size-cells = <2>; 1886 device_type = "pci"; 1887 num-lanes = <8>; 1888 num-viewport = <8>; 1889 linux,pci-domain = <0>; 1890 1891 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1892 clock-names = "core"; 1893 1894 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1895 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1896 reset-names = "apb", "core"; 1897 1898 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1899 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1900 interrupt-names = "intr", "msi"; 1901 1902 #interrupt-cells = <1>; 1903 interrupt-map-mask = <0 0 0 0>; 1904 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1905 1906 nvidia,bpmp = <&bpmp 0>; 1907 1908 nvidia,aspm-cmrt-us = <60>; 1909 nvidia,aspm-pwr-on-t-us = <20>; 1910 nvidia,aspm-l0s-entrance-latency-us = <3>; 1911 1912 bus-range = <0x0 0xff>; 1913 1914 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1915 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1916 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1917 1918 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1919 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1920 interconnect-names = "read", "write"; 1921 }; 1922 1923 pcie@141a0000 { 1924 compatible = "nvidia,tegra194-pcie"; 1925 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1926 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1927 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1928 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1929 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1930 reg-names = "appl", "config", "atu_dma", "dbi"; 1931 1932 status = "disabled"; 1933 1934 #address-cells = <3>; 1935 #size-cells = <2>; 1936 device_type = "pci"; 1937 num-lanes = <8>; 1938 num-viewport = <8>; 1939 linux,pci-domain = <5>; 1940 1941 pinctrl-names = "default"; 1942 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1943 1944 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1945 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1946 clock-names = "core", "core_m"; 1947 1948 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1949 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1950 reset-names = "apb", "core"; 1951 1952 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1953 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1954 interrupt-names = "intr", "msi"; 1955 1956 nvidia,bpmp = <&bpmp 5>; 1957 1958 #interrupt-cells = <1>; 1959 interrupt-map-mask = <0 0 0 0>; 1960 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1961 1962 nvidia,aspm-cmrt-us = <60>; 1963 nvidia,aspm-pwr-on-t-us = <20>; 1964 nvidia,aspm-l0s-entrance-latency-us = <3>; 1965 1966 bus-range = <0x0 0xff>; 1967 1968 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1969 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1970 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1971 1972 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1973 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1974 interconnect-names = "read", "write"; 1975 }; 1976 1977 pcie_ep@14160000 { 1978 compatible = "nvidia,tegra194-pcie-ep"; 1979 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1980 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1981 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1982 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1983 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1984 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1985 1986 status = "disabled"; 1987 1988 num-lanes = <4>; 1989 num-ib-windows = <2>; 1990 num-ob-windows = <8>; 1991 1992 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1993 clock-names = "core"; 1994 1995 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1996 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1997 reset-names = "apb", "core"; 1998 1999 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2000 interrupt-names = "intr"; 2001 2002 nvidia,bpmp = <&bpmp 4>; 2003 2004 nvidia,aspm-cmrt-us = <60>; 2005 nvidia,aspm-pwr-on-t-us = <20>; 2006 nvidia,aspm-l0s-entrance-latency-us = <3>; 2007 }; 2008 2009 pcie_ep@14180000 { 2010 compatible = "nvidia,tegra194-pcie-ep"; 2011 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2012 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2013 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2014 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2015 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2016 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2017 2018 status = "disabled"; 2019 2020 num-lanes = <8>; 2021 num-ib-windows = <2>; 2022 num-ob-windows = <8>; 2023 2024 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2025 clock-names = "core"; 2026 2027 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2028 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2029 reset-names = "apb", "core"; 2030 2031 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2032 interrupt-names = "intr"; 2033 2034 nvidia,bpmp = <&bpmp 0>; 2035 2036 nvidia,aspm-cmrt-us = <60>; 2037 nvidia,aspm-pwr-on-t-us = <20>; 2038 nvidia,aspm-l0s-entrance-latency-us = <3>; 2039 }; 2040 2041 pcie_ep@141a0000 { 2042 compatible = "nvidia,tegra194-pcie-ep"; 2043 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2044 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2045 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2046 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2047 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2048 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2049 2050 status = "disabled"; 2051 2052 num-lanes = <8>; 2053 num-ib-windows = <2>; 2054 num-ob-windows = <8>; 2055 2056 pinctrl-names = "default"; 2057 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2058 2059 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2060 clock-names = "core"; 2061 2062 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2063 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2064 reset-names = "apb", "core"; 2065 2066 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2067 interrupt-names = "intr"; 2068 2069 nvidia,bpmp = <&bpmp 5>; 2070 2071 nvidia,aspm-cmrt-us = <60>; 2072 nvidia,aspm-pwr-on-t-us = <20>; 2073 nvidia,aspm-l0s-entrance-latency-us = <3>; 2074 }; 2075 2076 sram@40000000 { 2077 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2078 reg = <0x0 0x40000000 0x0 0x50000>; 2079 #address-cells = <1>; 2080 #size-cells = <1>; 2081 ranges = <0x0 0x0 0x40000000 0x50000>; 2082 2083 cpu_bpmp_tx: sram@4e000 { 2084 reg = <0x4e000 0x1000>; 2085 label = "cpu-bpmp-tx"; 2086 pool; 2087 }; 2088 2089 cpu_bpmp_rx: sram@4f000 { 2090 reg = <0x4f000 0x1000>; 2091 label = "cpu-bpmp-rx"; 2092 pool; 2093 }; 2094 }; 2095 2096 bpmp: bpmp { 2097 compatible = "nvidia,tegra186-bpmp"; 2098 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2099 TEGRA_HSP_DB_MASTER_BPMP>; 2100 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 2101 #clock-cells = <1>; 2102 #reset-cells = <1>; 2103 #power-domain-cells = <1>; 2104 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2105 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2106 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2107 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2108 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2109 2110 bpmp_i2c: i2c { 2111 compatible = "nvidia,tegra186-bpmp-i2c"; 2112 nvidia,bpmp-bus-id = <5>; 2113 #address-cells = <1>; 2114 #size-cells = <0>; 2115 }; 2116 2117 bpmp_thermal: thermal { 2118 compatible = "nvidia,tegra186-bpmp-thermal"; 2119 #thermal-sensor-cells = <1>; 2120 }; 2121 }; 2122 2123 cpus { 2124 compatible = "nvidia,tegra194-ccplex"; 2125 nvidia,bpmp = <&bpmp>; 2126 #address-cells = <1>; 2127 #size-cells = <0>; 2128 2129 cpu0_0: cpu@0 { 2130 compatible = "nvidia,tegra194-carmel"; 2131 device_type = "cpu"; 2132 reg = <0x000>; 2133 enable-method = "psci"; 2134 i-cache-size = <131072>; 2135 i-cache-line-size = <64>; 2136 i-cache-sets = <512>; 2137 d-cache-size = <65536>; 2138 d-cache-line-size = <64>; 2139 d-cache-sets = <256>; 2140 next-level-cache = <&l2c_0>; 2141 }; 2142 2143 cpu0_1: cpu@1 { 2144 compatible = "nvidia,tegra194-carmel"; 2145 device_type = "cpu"; 2146 reg = <0x001>; 2147 enable-method = "psci"; 2148 i-cache-size = <131072>; 2149 i-cache-line-size = <64>; 2150 i-cache-sets = <512>; 2151 d-cache-size = <65536>; 2152 d-cache-line-size = <64>; 2153 d-cache-sets = <256>; 2154 next-level-cache = <&l2c_0>; 2155 }; 2156 2157 cpu1_0: cpu@100 { 2158 compatible = "nvidia,tegra194-carmel"; 2159 device_type = "cpu"; 2160 reg = <0x100>; 2161 enable-method = "psci"; 2162 i-cache-size = <131072>; 2163 i-cache-line-size = <64>; 2164 i-cache-sets = <512>; 2165 d-cache-size = <65536>; 2166 d-cache-line-size = <64>; 2167 d-cache-sets = <256>; 2168 next-level-cache = <&l2c_1>; 2169 }; 2170 2171 cpu1_1: cpu@101 { 2172 compatible = "nvidia,tegra194-carmel"; 2173 device_type = "cpu"; 2174 reg = <0x101>; 2175 enable-method = "psci"; 2176 i-cache-size = <131072>; 2177 i-cache-line-size = <64>; 2178 i-cache-sets = <512>; 2179 d-cache-size = <65536>; 2180 d-cache-line-size = <64>; 2181 d-cache-sets = <256>; 2182 next-level-cache = <&l2c_1>; 2183 }; 2184 2185 cpu2_0: cpu@200 { 2186 compatible = "nvidia,tegra194-carmel"; 2187 device_type = "cpu"; 2188 reg = <0x200>; 2189 enable-method = "psci"; 2190 i-cache-size = <131072>; 2191 i-cache-line-size = <64>; 2192 i-cache-sets = <512>; 2193 d-cache-size = <65536>; 2194 d-cache-line-size = <64>; 2195 d-cache-sets = <256>; 2196 next-level-cache = <&l2c_2>; 2197 }; 2198 2199 cpu2_1: cpu@201 { 2200 compatible = "nvidia,tegra194-carmel"; 2201 device_type = "cpu"; 2202 reg = <0x201>; 2203 enable-method = "psci"; 2204 i-cache-size = <131072>; 2205 i-cache-line-size = <64>; 2206 i-cache-sets = <512>; 2207 d-cache-size = <65536>; 2208 d-cache-line-size = <64>; 2209 d-cache-sets = <256>; 2210 next-level-cache = <&l2c_2>; 2211 }; 2212 2213 cpu3_0: cpu@300 { 2214 compatible = "nvidia,tegra194-carmel"; 2215 device_type = "cpu"; 2216 reg = <0x300>; 2217 enable-method = "psci"; 2218 i-cache-size = <131072>; 2219 i-cache-line-size = <64>; 2220 i-cache-sets = <512>; 2221 d-cache-size = <65536>; 2222 d-cache-line-size = <64>; 2223 d-cache-sets = <256>; 2224 next-level-cache = <&l2c_3>; 2225 }; 2226 2227 cpu3_1: cpu@301 { 2228 compatible = "nvidia,tegra194-carmel"; 2229 device_type = "cpu"; 2230 reg = <0x301>; 2231 enable-method = "psci"; 2232 i-cache-size = <131072>; 2233 i-cache-line-size = <64>; 2234 i-cache-sets = <512>; 2235 d-cache-size = <65536>; 2236 d-cache-line-size = <64>; 2237 d-cache-sets = <256>; 2238 next-level-cache = <&l2c_3>; 2239 }; 2240 2241 cpu-map { 2242 cluster0 { 2243 core0 { 2244 cpu = <&cpu0_0>; 2245 }; 2246 2247 core1 { 2248 cpu = <&cpu0_1>; 2249 }; 2250 }; 2251 2252 cluster1 { 2253 core0 { 2254 cpu = <&cpu1_0>; 2255 }; 2256 2257 core1 { 2258 cpu = <&cpu1_1>; 2259 }; 2260 }; 2261 2262 cluster2 { 2263 core0 { 2264 cpu = <&cpu2_0>; 2265 }; 2266 2267 core1 { 2268 cpu = <&cpu2_1>; 2269 }; 2270 }; 2271 2272 cluster3 { 2273 core0 { 2274 cpu = <&cpu3_0>; 2275 }; 2276 2277 core1 { 2278 cpu = <&cpu3_1>; 2279 }; 2280 }; 2281 }; 2282 2283 l2c_0: l2-cache0 { 2284 cache-size = <2097152>; 2285 cache-line-size = <64>; 2286 cache-sets = <2048>; 2287 next-level-cache = <&l3c>; 2288 }; 2289 2290 l2c_1: l2-cache1 { 2291 cache-size = <2097152>; 2292 cache-line-size = <64>; 2293 cache-sets = <2048>; 2294 next-level-cache = <&l3c>; 2295 }; 2296 2297 l2c_2: l2-cache2 { 2298 cache-size = <2097152>; 2299 cache-line-size = <64>; 2300 cache-sets = <2048>; 2301 next-level-cache = <&l3c>; 2302 }; 2303 2304 l2c_3: l2-cache3 { 2305 cache-size = <2097152>; 2306 cache-line-size = <64>; 2307 cache-sets = <2048>; 2308 next-level-cache = <&l3c>; 2309 }; 2310 2311 l3c: l3-cache { 2312 cache-size = <4194304>; 2313 cache-line-size = <64>; 2314 cache-sets = <4096>; 2315 }; 2316 }; 2317 2318 psci { 2319 compatible = "arm,psci-1.0"; 2320 status = "okay"; 2321 method = "smc"; 2322 }; 2323 2324 tcu: tcu { 2325 compatible = "nvidia,tegra194-tcu"; 2326 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2327 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2328 mbox-names = "rx", "tx"; 2329 }; 2330 2331 thermal-zones { 2332 cpu { 2333 thermal-sensors = <&{/bpmp/thermal} 2334 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2335 status = "disabled"; 2336 }; 2337 2338 gpu { 2339 thermal-sensors = <&{/bpmp/thermal} 2340 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2341 status = "disabled"; 2342 }; 2343 2344 aux { 2345 thermal-sensors = <&{/bpmp/thermal} 2346 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2347 status = "disabled"; 2348 }; 2349 2350 pllx { 2351 thermal-sensors = <&{/bpmp/thermal} 2352 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2353 status = "disabled"; 2354 }; 2355 2356 ao { 2357 thermal-sensors = <&{/bpmp/thermal} 2358 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2359 status = "disabled"; 2360 }; 2361 2362 tj { 2363 thermal-sensors = <&{/bpmp/thermal} 2364 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2365 status = "disabled"; 2366 }; 2367 }; 2368 2369 timer { 2370 compatible = "arm,armv8-timer"; 2371 interrupts = <GIC_PPI 13 2372 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2373 <GIC_PPI 14 2374 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2375 <GIC_PPI 11 2376 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2377 <GIC_PPI 10 2378 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2379 interrupt-parent = <&gic>; 2380 always-on; 2381 }; 2382}; 2383