1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Single-step support.
4 *
5 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
6 */
7 #include <linux/kernel.h>
8 #include <linux/kprobes.h>
9 #include <linux/ptrace.h>
10 #include <linux/prefetch.h>
11 #include <asm/sstep.h>
12 #include <asm/processor.h>
13 #include <linux/uaccess.h>
14 #include <asm/cpu_has_feature.h>
15 #include <asm/cputable.h>
16 #include <asm/disassemble.h>
17
18 extern char system_call_common[];
19 extern char system_call_vectored_emulate[];
20
21 #ifdef CONFIG_PPC64
22 /* Bits in SRR1 that are copied from MSR */
23 #define MSR_MASK 0xffffffff87c0ffffUL
24 #else
25 #define MSR_MASK 0x87c0ffff
26 #endif
27
28 /* Bits in XER */
29 #define XER_SO 0x80000000U
30 #define XER_OV 0x40000000U
31 #define XER_CA 0x20000000U
32 #define XER_OV32 0x00080000U
33 #define XER_CA32 0x00040000U
34
35 #ifdef CONFIG_PPC_FPU
36 /*
37 * Functions in ldstfp.S
38 */
39 extern void get_fpr(int rn, double *p);
40 extern void put_fpr(int rn, const double *p);
41 extern void get_vr(int rn, __vector128 *p);
42 extern void put_vr(int rn, __vector128 *p);
43 extern void load_vsrn(int vsr, const void *p);
44 extern void store_vsrn(int vsr, void *p);
45 extern void conv_sp_to_dp(const float *sp, double *dp);
46 extern void conv_dp_to_sp(const double *dp, float *sp);
47 #endif
48
49 #ifdef __powerpc64__
50 /*
51 * Functions in quad.S
52 */
53 extern int do_lq(unsigned long ea, unsigned long *regs);
54 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
55 extern int do_lqarx(unsigned long ea, unsigned long *regs);
56 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
57 unsigned int *crp);
58 #endif
59
60 #ifdef __LITTLE_ENDIAN__
61 #define IS_LE 1
62 #define IS_BE 0
63 #else
64 #define IS_LE 0
65 #define IS_BE 1
66 #endif
67
68 /*
69 * Emulate the truncation of 64 bit values in 32-bit mode.
70 */
truncate_if_32bit(unsigned long msr,unsigned long val)71 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
72 unsigned long val)
73 {
74 #ifdef __powerpc64__
75 if ((msr & MSR_64BIT) == 0)
76 val &= 0xffffffffUL;
77 #endif
78 return val;
79 }
80
81 /*
82 * Determine whether a conditional branch instruction would branch.
83 */
branch_taken(unsigned int instr,const struct pt_regs * regs,struct instruction_op * op)84 static nokprobe_inline int branch_taken(unsigned int instr,
85 const struct pt_regs *regs,
86 struct instruction_op *op)
87 {
88 unsigned int bo = (instr >> 21) & 0x1f;
89 unsigned int bi;
90
91 if ((bo & 4) == 0) {
92 /* decrement counter */
93 op->type |= DECCTR;
94 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
95 return 0;
96 }
97 if ((bo & 0x10) == 0) {
98 /* check bit from CR */
99 bi = (instr >> 16) & 0x1f;
100 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
101 return 0;
102 }
103 return 1;
104 }
105
address_ok(struct pt_regs * regs,unsigned long ea,int nb)106 static nokprobe_inline long address_ok(struct pt_regs *regs,
107 unsigned long ea, int nb)
108 {
109 if (!user_mode(regs))
110 return 1;
111 if (access_ok((void __user *)ea, nb))
112 return 1;
113 if (access_ok((void __user *)ea, 1))
114 /* Access overlaps the end of the user region */
115 regs->dar = TASK_SIZE_MAX - 1;
116 else
117 regs->dar = ea;
118 return 0;
119 }
120
121 /*
122 * Calculate effective address for a D-form instruction
123 */
dform_ea(unsigned int instr,const struct pt_regs * regs)124 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
125 const struct pt_regs *regs)
126 {
127 int ra;
128 unsigned long ea;
129
130 ra = (instr >> 16) & 0x1f;
131 ea = (signed short) instr; /* sign-extend */
132 if (ra)
133 ea += regs->gpr[ra];
134
135 return ea;
136 }
137
138 #ifdef __powerpc64__
139 /*
140 * Calculate effective address for a DS-form instruction
141 */
dsform_ea(unsigned int instr,const struct pt_regs * regs)142 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
143 const struct pt_regs *regs)
144 {
145 int ra;
146 unsigned long ea;
147
148 ra = (instr >> 16) & 0x1f;
149 ea = (signed short) (instr & ~3); /* sign-extend */
150 if (ra)
151 ea += regs->gpr[ra];
152
153 return ea;
154 }
155
156 /*
157 * Calculate effective address for a DQ-form instruction
158 */
dqform_ea(unsigned int instr,const struct pt_regs * regs)159 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
160 const struct pt_regs *regs)
161 {
162 int ra;
163 unsigned long ea;
164
165 ra = (instr >> 16) & 0x1f;
166 ea = (signed short) (instr & ~0xf); /* sign-extend */
167 if (ra)
168 ea += regs->gpr[ra];
169
170 return ea;
171 }
172 #endif /* __powerpc64 */
173
174 /*
175 * Calculate effective address for an X-form instruction
176 */
xform_ea(unsigned int instr,const struct pt_regs * regs)177 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
178 const struct pt_regs *regs)
179 {
180 int ra, rb;
181 unsigned long ea;
182
183 ra = (instr >> 16) & 0x1f;
184 rb = (instr >> 11) & 0x1f;
185 ea = regs->gpr[rb];
186 if (ra)
187 ea += regs->gpr[ra];
188
189 return ea;
190 }
191
192 /*
193 * Calculate effective address for a MLS:D-form / 8LS:D-form
194 * prefixed instruction
195 */
mlsd_8lsd_ea(unsigned int instr,unsigned int suffix,const struct pt_regs * regs)196 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
197 unsigned int suffix,
198 const struct pt_regs *regs)
199 {
200 int ra, prefix_r;
201 unsigned int dd;
202 unsigned long ea, d0, d1, d;
203
204 prefix_r = GET_PREFIX_R(instr);
205 ra = GET_PREFIX_RA(suffix);
206
207 d0 = instr & 0x3ffff;
208 d1 = suffix & 0xffff;
209 d = (d0 << 16) | d1;
210
211 /*
212 * sign extend a 34 bit number
213 */
214 dd = (unsigned int)(d >> 2);
215 ea = (signed int)dd;
216 ea = (ea << 2) | (d & 0x3);
217
218 if (!prefix_r && ra)
219 ea += regs->gpr[ra];
220 else if (!prefix_r && !ra)
221 ; /* Leave ea as is */
222 else if (prefix_r)
223 ea += regs->nip;
224
225 /*
226 * (prefix_r && ra) is an invalid form. Should already be
227 * checked for by caller!
228 */
229
230 return ea;
231 }
232
233 /*
234 * Return the largest power of 2, not greater than sizeof(unsigned long),
235 * such that x is a multiple of it.
236 */
max_align(unsigned long x)237 static nokprobe_inline unsigned long max_align(unsigned long x)
238 {
239 x |= sizeof(unsigned long);
240 return x & -x; /* isolates rightmost bit */
241 }
242
byterev_2(unsigned long x)243 static nokprobe_inline unsigned long byterev_2(unsigned long x)
244 {
245 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
246 }
247
byterev_4(unsigned long x)248 static nokprobe_inline unsigned long byterev_4(unsigned long x)
249 {
250 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
251 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
252 }
253
254 #ifdef __powerpc64__
byterev_8(unsigned long x)255 static nokprobe_inline unsigned long byterev_8(unsigned long x)
256 {
257 return (byterev_4(x) << 32) | byterev_4(x >> 32);
258 }
259 #endif
260
do_byte_reverse(void * ptr,int nb)261 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
262 {
263 switch (nb) {
264 case 2:
265 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
266 break;
267 case 4:
268 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
269 break;
270 #ifdef __powerpc64__
271 case 8:
272 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
273 break;
274 case 16: {
275 unsigned long *up = (unsigned long *)ptr;
276 unsigned long tmp;
277 tmp = byterev_8(up[0]);
278 up[0] = byterev_8(up[1]);
279 up[1] = tmp;
280 break;
281 }
282 #endif
283 default:
284 WARN_ON_ONCE(1);
285 }
286 }
287
read_mem_aligned(unsigned long * dest,unsigned long ea,int nb,struct pt_regs * regs)288 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
289 unsigned long ea, int nb,
290 struct pt_regs *regs)
291 {
292 int err = 0;
293 unsigned long x = 0;
294
295 switch (nb) {
296 case 1:
297 err = __get_user(x, (unsigned char __user *) ea);
298 break;
299 case 2:
300 err = __get_user(x, (unsigned short __user *) ea);
301 break;
302 case 4:
303 err = __get_user(x, (unsigned int __user *) ea);
304 break;
305 #ifdef __powerpc64__
306 case 8:
307 err = __get_user(x, (unsigned long __user *) ea);
308 break;
309 #endif
310 }
311 if (!err)
312 *dest = x;
313 else
314 regs->dar = ea;
315 return err;
316 }
317
318 /*
319 * Copy from userspace to a buffer, using the largest possible
320 * aligned accesses, up to sizeof(long).
321 */
copy_mem_in(u8 * dest,unsigned long ea,int nb,struct pt_regs * regs)322 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
323 struct pt_regs *regs)
324 {
325 int err = 0;
326 int c;
327
328 for (; nb > 0; nb -= c) {
329 c = max_align(ea);
330 if (c > nb)
331 c = max_align(nb);
332 switch (c) {
333 case 1:
334 err = __get_user(*dest, (unsigned char __user *) ea);
335 break;
336 case 2:
337 err = __get_user(*(u16 *)dest,
338 (unsigned short __user *) ea);
339 break;
340 case 4:
341 err = __get_user(*(u32 *)dest,
342 (unsigned int __user *) ea);
343 break;
344 #ifdef __powerpc64__
345 case 8:
346 err = __get_user(*(unsigned long *)dest,
347 (unsigned long __user *) ea);
348 break;
349 #endif
350 }
351 if (err) {
352 regs->dar = ea;
353 return err;
354 }
355 dest += c;
356 ea += c;
357 }
358 return 0;
359 }
360
read_mem_unaligned(unsigned long * dest,unsigned long ea,int nb,struct pt_regs * regs)361 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
362 unsigned long ea, int nb,
363 struct pt_regs *regs)
364 {
365 union {
366 unsigned long ul;
367 u8 b[sizeof(unsigned long)];
368 } u;
369 int i;
370 int err;
371
372 u.ul = 0;
373 i = IS_BE ? sizeof(unsigned long) - nb : 0;
374 err = copy_mem_in(&u.b[i], ea, nb, regs);
375 if (!err)
376 *dest = u.ul;
377 return err;
378 }
379
380 /*
381 * Read memory at address ea for nb bytes, return 0 for success
382 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
383 * If nb < sizeof(long), the result is right-justified on BE systems.
384 */
read_mem(unsigned long * dest,unsigned long ea,int nb,struct pt_regs * regs)385 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
386 struct pt_regs *regs)
387 {
388 if (!address_ok(regs, ea, nb))
389 return -EFAULT;
390 if ((ea & (nb - 1)) == 0)
391 return read_mem_aligned(dest, ea, nb, regs);
392 return read_mem_unaligned(dest, ea, nb, regs);
393 }
394 NOKPROBE_SYMBOL(read_mem);
395
write_mem_aligned(unsigned long val,unsigned long ea,int nb,struct pt_regs * regs)396 static nokprobe_inline int write_mem_aligned(unsigned long val,
397 unsigned long ea, int nb,
398 struct pt_regs *regs)
399 {
400 int err = 0;
401
402 switch (nb) {
403 case 1:
404 err = __put_user(val, (unsigned char __user *) ea);
405 break;
406 case 2:
407 err = __put_user(val, (unsigned short __user *) ea);
408 break;
409 case 4:
410 err = __put_user(val, (unsigned int __user *) ea);
411 break;
412 #ifdef __powerpc64__
413 case 8:
414 err = __put_user(val, (unsigned long __user *) ea);
415 break;
416 #endif
417 }
418 if (err)
419 regs->dar = ea;
420 return err;
421 }
422
423 /*
424 * Copy from a buffer to userspace, using the largest possible
425 * aligned accesses, up to sizeof(long).
426 */
copy_mem_out(u8 * dest,unsigned long ea,int nb,struct pt_regs * regs)427 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
428 struct pt_regs *regs)
429 {
430 int err = 0;
431 int c;
432
433 for (; nb > 0; nb -= c) {
434 c = max_align(ea);
435 if (c > nb)
436 c = max_align(nb);
437 switch (c) {
438 case 1:
439 err = __put_user(*dest, (unsigned char __user *) ea);
440 break;
441 case 2:
442 err = __put_user(*(u16 *)dest,
443 (unsigned short __user *) ea);
444 break;
445 case 4:
446 err = __put_user(*(u32 *)dest,
447 (unsigned int __user *) ea);
448 break;
449 #ifdef __powerpc64__
450 case 8:
451 err = __put_user(*(unsigned long *)dest,
452 (unsigned long __user *) ea);
453 break;
454 #endif
455 }
456 if (err) {
457 regs->dar = ea;
458 return err;
459 }
460 dest += c;
461 ea += c;
462 }
463 return 0;
464 }
465
write_mem_unaligned(unsigned long val,unsigned long ea,int nb,struct pt_regs * regs)466 static nokprobe_inline int write_mem_unaligned(unsigned long val,
467 unsigned long ea, int nb,
468 struct pt_regs *regs)
469 {
470 union {
471 unsigned long ul;
472 u8 b[sizeof(unsigned long)];
473 } u;
474 int i;
475
476 u.ul = val;
477 i = IS_BE ? sizeof(unsigned long) - nb : 0;
478 return copy_mem_out(&u.b[i], ea, nb, regs);
479 }
480
481 /*
482 * Write memory at address ea for nb bytes, return 0 for success
483 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
484 */
write_mem(unsigned long val,unsigned long ea,int nb,struct pt_regs * regs)485 static int write_mem(unsigned long val, unsigned long ea, int nb,
486 struct pt_regs *regs)
487 {
488 if (!address_ok(regs, ea, nb))
489 return -EFAULT;
490 if ((ea & (nb - 1)) == 0)
491 return write_mem_aligned(val, ea, nb, regs);
492 return write_mem_unaligned(val, ea, nb, regs);
493 }
494 NOKPROBE_SYMBOL(write_mem);
495
496 #ifdef CONFIG_PPC_FPU
497 /*
498 * These access either the real FP register or the image in the
499 * thread_struct, depending on regs->msr & MSR_FP.
500 */
do_fp_load(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)501 static int do_fp_load(struct instruction_op *op, unsigned long ea,
502 struct pt_regs *regs, bool cross_endian)
503 {
504 int err, rn, nb;
505 union {
506 int i;
507 unsigned int u;
508 float f;
509 double d[2];
510 unsigned long l[2];
511 u8 b[2 * sizeof(double)];
512 } u;
513
514 nb = GETSIZE(op->type);
515 if (!address_ok(regs, ea, nb))
516 return -EFAULT;
517 rn = op->reg;
518 err = copy_mem_in(u.b, ea, nb, regs);
519 if (err)
520 return err;
521 if (unlikely(cross_endian)) {
522 do_byte_reverse(u.b, min(nb, 8));
523 if (nb == 16)
524 do_byte_reverse(&u.b[8], 8);
525 }
526 preempt_disable();
527 if (nb == 4) {
528 if (op->type & FPCONV)
529 conv_sp_to_dp(&u.f, &u.d[0]);
530 else if (op->type & SIGNEXT)
531 u.l[0] = u.i;
532 else
533 u.l[0] = u.u;
534 }
535 if (regs->msr & MSR_FP)
536 put_fpr(rn, &u.d[0]);
537 else
538 current->thread.TS_FPR(rn) = u.l[0];
539 if (nb == 16) {
540 /* lfdp */
541 rn |= 1;
542 if (regs->msr & MSR_FP)
543 put_fpr(rn, &u.d[1]);
544 else
545 current->thread.TS_FPR(rn) = u.l[1];
546 }
547 preempt_enable();
548 return 0;
549 }
550 NOKPROBE_SYMBOL(do_fp_load);
551
do_fp_store(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)552 static int do_fp_store(struct instruction_op *op, unsigned long ea,
553 struct pt_regs *regs, bool cross_endian)
554 {
555 int rn, nb;
556 union {
557 unsigned int u;
558 float f;
559 double d[2];
560 unsigned long l[2];
561 u8 b[2 * sizeof(double)];
562 } u;
563
564 nb = GETSIZE(op->type);
565 if (!address_ok(regs, ea, nb))
566 return -EFAULT;
567 rn = op->reg;
568 preempt_disable();
569 if (regs->msr & MSR_FP)
570 get_fpr(rn, &u.d[0]);
571 else
572 u.l[0] = current->thread.TS_FPR(rn);
573 if (nb == 4) {
574 if (op->type & FPCONV)
575 conv_dp_to_sp(&u.d[0], &u.f);
576 else
577 u.u = u.l[0];
578 }
579 if (nb == 16) {
580 rn |= 1;
581 if (regs->msr & MSR_FP)
582 get_fpr(rn, &u.d[1]);
583 else
584 u.l[1] = current->thread.TS_FPR(rn);
585 }
586 preempt_enable();
587 if (unlikely(cross_endian)) {
588 do_byte_reverse(u.b, min(nb, 8));
589 if (nb == 16)
590 do_byte_reverse(&u.b[8], 8);
591 }
592 return copy_mem_out(u.b, ea, nb, regs);
593 }
594 NOKPROBE_SYMBOL(do_fp_store);
595 #endif
596
597 #ifdef CONFIG_ALTIVEC
598 /* For Altivec/VMX, no need to worry about alignment */
do_vec_load(int rn,unsigned long ea,int size,struct pt_regs * regs,bool cross_endian)599 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
600 int size, struct pt_regs *regs,
601 bool cross_endian)
602 {
603 int err;
604 union {
605 __vector128 v;
606 u8 b[sizeof(__vector128)];
607 } u = {};
608
609 if (!address_ok(regs, ea & ~0xfUL, 16))
610 return -EFAULT;
611 /* align to multiple of size */
612 ea &= ~(size - 1);
613 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
614 if (err)
615 return err;
616 if (unlikely(cross_endian))
617 do_byte_reverse(&u.b[ea & 0xf], size);
618 preempt_disable();
619 if (regs->msr & MSR_VEC)
620 put_vr(rn, &u.v);
621 else
622 current->thread.vr_state.vr[rn] = u.v;
623 preempt_enable();
624 return 0;
625 }
626
do_vec_store(int rn,unsigned long ea,int size,struct pt_regs * regs,bool cross_endian)627 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
628 int size, struct pt_regs *regs,
629 bool cross_endian)
630 {
631 union {
632 __vector128 v;
633 u8 b[sizeof(__vector128)];
634 } u;
635
636 if (!address_ok(regs, ea & ~0xfUL, 16))
637 return -EFAULT;
638 /* align to multiple of size */
639 ea &= ~(size - 1);
640
641 preempt_disable();
642 if (regs->msr & MSR_VEC)
643 get_vr(rn, &u.v);
644 else
645 u.v = current->thread.vr_state.vr[rn];
646 preempt_enable();
647 if (unlikely(cross_endian))
648 do_byte_reverse(&u.b[ea & 0xf], size);
649 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
650 }
651 #endif /* CONFIG_ALTIVEC */
652
653 #ifdef __powerpc64__
emulate_lq(struct pt_regs * regs,unsigned long ea,int reg,bool cross_endian)654 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
655 int reg, bool cross_endian)
656 {
657 int err;
658
659 if (!address_ok(regs, ea, 16))
660 return -EFAULT;
661 /* if aligned, should be atomic */
662 if ((ea & 0xf) == 0) {
663 err = do_lq(ea, ®s->gpr[reg]);
664 } else {
665 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
666 if (!err)
667 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
668 }
669 if (!err && unlikely(cross_endian))
670 do_byte_reverse(®s->gpr[reg], 16);
671 return err;
672 }
673
emulate_stq(struct pt_regs * regs,unsigned long ea,int reg,bool cross_endian)674 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
675 int reg, bool cross_endian)
676 {
677 int err;
678 unsigned long vals[2];
679
680 if (!address_ok(regs, ea, 16))
681 return -EFAULT;
682 vals[0] = regs->gpr[reg];
683 vals[1] = regs->gpr[reg + 1];
684 if (unlikely(cross_endian))
685 do_byte_reverse(vals, 16);
686
687 /* if aligned, should be atomic */
688 if ((ea & 0xf) == 0)
689 return do_stq(ea, vals[0], vals[1]);
690
691 err = write_mem(vals[IS_LE], ea, 8, regs);
692 if (!err)
693 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
694 return err;
695 }
696 #endif /* __powerpc64 */
697
698 #ifdef CONFIG_VSX
emulate_vsx_load(struct instruction_op * op,union vsx_reg * reg,const void * mem,bool rev)699 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
700 const void *mem, bool rev)
701 {
702 int size, read_size;
703 int i, j;
704 const unsigned int *wp;
705 const unsigned short *hp;
706 const unsigned char *bp;
707
708 size = GETSIZE(op->type);
709 reg->d[0] = reg->d[1] = 0;
710
711 switch (op->element_size) {
712 case 16:
713 /* whole vector; lxv[x] or lxvl[l] */
714 if (size == 0)
715 break;
716 memcpy(reg, mem, size);
717 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
718 rev = !rev;
719 if (rev)
720 do_byte_reverse(reg, 16);
721 break;
722 case 8:
723 /* scalar loads, lxvd2x, lxvdsx */
724 read_size = (size >= 8) ? 8 : size;
725 i = IS_LE ? 8 : 8 - read_size;
726 memcpy(®->b[i], mem, read_size);
727 if (rev)
728 do_byte_reverse(®->b[i], 8);
729 if (size < 8) {
730 if (op->type & SIGNEXT) {
731 /* size == 4 is the only case here */
732 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
733 } else if (op->vsx_flags & VSX_FPCONV) {
734 preempt_disable();
735 conv_sp_to_dp(®->fp[1 + IS_LE],
736 ®->dp[IS_LE]);
737 preempt_enable();
738 }
739 } else {
740 if (size == 16) {
741 unsigned long v = *(unsigned long *)(mem + 8);
742 reg->d[IS_BE] = !rev ? v : byterev_8(v);
743 } else if (op->vsx_flags & VSX_SPLAT)
744 reg->d[IS_BE] = reg->d[IS_LE];
745 }
746 break;
747 case 4:
748 /* lxvw4x, lxvwsx */
749 wp = mem;
750 for (j = 0; j < size / 4; ++j) {
751 i = IS_LE ? 3 - j : j;
752 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
753 }
754 if (op->vsx_flags & VSX_SPLAT) {
755 u32 val = reg->w[IS_LE ? 3 : 0];
756 for (; j < 4; ++j) {
757 i = IS_LE ? 3 - j : j;
758 reg->w[i] = val;
759 }
760 }
761 break;
762 case 2:
763 /* lxvh8x */
764 hp = mem;
765 for (j = 0; j < size / 2; ++j) {
766 i = IS_LE ? 7 - j : j;
767 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
768 }
769 break;
770 case 1:
771 /* lxvb16x */
772 bp = mem;
773 for (j = 0; j < size; ++j) {
774 i = IS_LE ? 15 - j : j;
775 reg->b[i] = *bp++;
776 }
777 break;
778 }
779 }
780 EXPORT_SYMBOL_GPL(emulate_vsx_load);
781 NOKPROBE_SYMBOL(emulate_vsx_load);
782
emulate_vsx_store(struct instruction_op * op,const union vsx_reg * reg,void * mem,bool rev)783 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
784 void *mem, bool rev)
785 {
786 int size, write_size;
787 int i, j;
788 union vsx_reg buf;
789 unsigned int *wp;
790 unsigned short *hp;
791 unsigned char *bp;
792
793 size = GETSIZE(op->type);
794
795 switch (op->element_size) {
796 case 16:
797 /* stxv, stxvx, stxvl, stxvll */
798 if (size == 0)
799 break;
800 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
801 rev = !rev;
802 if (rev) {
803 /* reverse 16 bytes */
804 buf.d[0] = byterev_8(reg->d[1]);
805 buf.d[1] = byterev_8(reg->d[0]);
806 reg = &buf;
807 }
808 memcpy(mem, reg, size);
809 break;
810 case 8:
811 /* scalar stores, stxvd2x */
812 write_size = (size >= 8) ? 8 : size;
813 i = IS_LE ? 8 : 8 - write_size;
814 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
815 buf.d[0] = buf.d[1] = 0;
816 preempt_disable();
817 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
818 preempt_enable();
819 reg = &buf;
820 }
821 memcpy(mem, ®->b[i], write_size);
822 if (size == 16)
823 memcpy(mem + 8, ®->d[IS_BE], 8);
824 if (unlikely(rev)) {
825 do_byte_reverse(mem, write_size);
826 if (size == 16)
827 do_byte_reverse(mem + 8, 8);
828 }
829 break;
830 case 4:
831 /* stxvw4x */
832 wp = mem;
833 for (j = 0; j < size / 4; ++j) {
834 i = IS_LE ? 3 - j : j;
835 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
836 }
837 break;
838 case 2:
839 /* stxvh8x */
840 hp = mem;
841 for (j = 0; j < size / 2; ++j) {
842 i = IS_LE ? 7 - j : j;
843 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
844 }
845 break;
846 case 1:
847 /* stvxb16x */
848 bp = mem;
849 for (j = 0; j < size; ++j) {
850 i = IS_LE ? 15 - j : j;
851 *bp++ = reg->b[i];
852 }
853 break;
854 }
855 }
856 EXPORT_SYMBOL_GPL(emulate_vsx_store);
857 NOKPROBE_SYMBOL(emulate_vsx_store);
858
do_vsx_load(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)859 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
860 unsigned long ea, struct pt_regs *regs,
861 bool cross_endian)
862 {
863 int reg = op->reg;
864 u8 mem[16];
865 union vsx_reg buf;
866 int size = GETSIZE(op->type);
867
868 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
869 return -EFAULT;
870
871 emulate_vsx_load(op, &buf, mem, cross_endian);
872 preempt_disable();
873 if (reg < 32) {
874 /* FP regs + extensions */
875 if (regs->msr & MSR_FP) {
876 load_vsrn(reg, &buf);
877 } else {
878 current->thread.fp_state.fpr[reg][0] = buf.d[0];
879 current->thread.fp_state.fpr[reg][1] = buf.d[1];
880 }
881 } else {
882 if (regs->msr & MSR_VEC)
883 load_vsrn(reg, &buf);
884 else
885 current->thread.vr_state.vr[reg - 32] = buf.v;
886 }
887 preempt_enable();
888 return 0;
889 }
890
do_vsx_store(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)891 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
892 unsigned long ea, struct pt_regs *regs,
893 bool cross_endian)
894 {
895 int reg = op->reg;
896 u8 mem[16];
897 union vsx_reg buf;
898 int size = GETSIZE(op->type);
899
900 if (!address_ok(regs, ea, size))
901 return -EFAULT;
902
903 preempt_disable();
904 if (reg < 32) {
905 /* FP regs + extensions */
906 if (regs->msr & MSR_FP) {
907 store_vsrn(reg, &buf);
908 } else {
909 buf.d[0] = current->thread.fp_state.fpr[reg][0];
910 buf.d[1] = current->thread.fp_state.fpr[reg][1];
911 }
912 } else {
913 if (regs->msr & MSR_VEC)
914 store_vsrn(reg, &buf);
915 else
916 buf.v = current->thread.vr_state.vr[reg - 32];
917 }
918 preempt_enable();
919 emulate_vsx_store(op, &buf, mem, cross_endian);
920 return copy_mem_out(mem, ea, size, regs);
921 }
922 #endif /* CONFIG_VSX */
923
emulate_dcbz(unsigned long ea,struct pt_regs * regs)924 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
925 {
926 int err;
927 unsigned long i, size;
928
929 #ifdef __powerpc64__
930 size = ppc64_caches.l1d.block_size;
931 if (!(regs->msr & MSR_64BIT))
932 ea &= 0xffffffffUL;
933 #else
934 size = L1_CACHE_BYTES;
935 #endif
936 ea &= ~(size - 1);
937 if (!address_ok(regs, ea, size))
938 return -EFAULT;
939 for (i = 0; i < size; i += sizeof(long)) {
940 err = __put_user(0, (unsigned long __user *) (ea + i));
941 if (err) {
942 regs->dar = ea;
943 return err;
944 }
945 }
946 return 0;
947 }
948 NOKPROBE_SYMBOL(emulate_dcbz);
949
950 #define __put_user_asmx(x, addr, err, op, cr) \
951 __asm__ __volatile__( \
952 ".machine push\n" \
953 ".machine power8\n" \
954 "1: " op " %2,0,%3\n" \
955 ".machine pop\n" \
956 " mfcr %1\n" \
957 "2:\n" \
958 ".section .fixup,\"ax\"\n" \
959 "3: li %0,%4\n" \
960 " b 2b\n" \
961 ".previous\n" \
962 EX_TABLE(1b, 3b) \
963 : "=r" (err), "=r" (cr) \
964 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
965
966 #define __get_user_asmx(x, addr, err, op) \
967 __asm__ __volatile__( \
968 ".machine push\n" \
969 ".machine power8\n" \
970 "1: "op" %1,0,%2\n" \
971 ".machine pop\n" \
972 "2:\n" \
973 ".section .fixup,\"ax\"\n" \
974 "3: li %0,%3\n" \
975 " b 2b\n" \
976 ".previous\n" \
977 EX_TABLE(1b, 3b) \
978 : "=r" (err), "=r" (x) \
979 : "r" (addr), "i" (-EFAULT), "0" (err))
980
981 #define __cacheop_user_asmx(addr, err, op) \
982 __asm__ __volatile__( \
983 "1: "op" 0,%1\n" \
984 "2:\n" \
985 ".section .fixup,\"ax\"\n" \
986 "3: li %0,%3\n" \
987 " b 2b\n" \
988 ".previous\n" \
989 EX_TABLE(1b, 3b) \
990 : "=r" (err) \
991 : "r" (addr), "i" (-EFAULT), "0" (err))
992
set_cr0(const struct pt_regs * regs,struct instruction_op * op)993 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
994 struct instruction_op *op)
995 {
996 long val = op->val;
997
998 op->type |= SETCC;
999 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1000 #ifdef __powerpc64__
1001 if (!(regs->msr & MSR_64BIT))
1002 val = (int) val;
1003 #endif
1004 if (val < 0)
1005 op->ccval |= 0x80000000;
1006 else if (val > 0)
1007 op->ccval |= 0x40000000;
1008 else
1009 op->ccval |= 0x20000000;
1010 }
1011
set_ca32(struct instruction_op * op,bool val)1012 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1013 {
1014 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1015 if (val)
1016 op->xerval |= XER_CA32;
1017 else
1018 op->xerval &= ~XER_CA32;
1019 }
1020 }
1021
add_with_carry(const struct pt_regs * regs,struct instruction_op * op,int rd,unsigned long val1,unsigned long val2,unsigned long carry_in)1022 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1023 struct instruction_op *op, int rd,
1024 unsigned long val1, unsigned long val2,
1025 unsigned long carry_in)
1026 {
1027 unsigned long val = val1 + val2;
1028
1029 if (carry_in)
1030 ++val;
1031 op->type = COMPUTE + SETREG + SETXER;
1032 op->reg = rd;
1033 op->val = val;
1034 #ifdef __powerpc64__
1035 if (!(regs->msr & MSR_64BIT)) {
1036 val = (unsigned int) val;
1037 val1 = (unsigned int) val1;
1038 }
1039 #endif
1040 op->xerval = regs->xer;
1041 if (val < val1 || (carry_in && val == val1))
1042 op->xerval |= XER_CA;
1043 else
1044 op->xerval &= ~XER_CA;
1045
1046 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1047 (carry_in && (unsigned int)val == (unsigned int)val1));
1048 }
1049
do_cmp_signed(const struct pt_regs * regs,struct instruction_op * op,long v1,long v2,int crfld)1050 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1051 struct instruction_op *op,
1052 long v1, long v2, int crfld)
1053 {
1054 unsigned int crval, shift;
1055
1056 op->type = COMPUTE + SETCC;
1057 crval = (regs->xer >> 31) & 1; /* get SO bit */
1058 if (v1 < v2)
1059 crval |= 8;
1060 else if (v1 > v2)
1061 crval |= 4;
1062 else
1063 crval |= 2;
1064 shift = (7 - crfld) * 4;
1065 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1066 }
1067
do_cmp_unsigned(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,unsigned long v2,int crfld)1068 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1069 struct instruction_op *op,
1070 unsigned long v1,
1071 unsigned long v2, int crfld)
1072 {
1073 unsigned int crval, shift;
1074
1075 op->type = COMPUTE + SETCC;
1076 crval = (regs->xer >> 31) & 1; /* get SO bit */
1077 if (v1 < v2)
1078 crval |= 8;
1079 else if (v1 > v2)
1080 crval |= 4;
1081 else
1082 crval |= 2;
1083 shift = (7 - crfld) * 4;
1084 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1085 }
1086
do_cmpb(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,unsigned long v2)1087 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1088 struct instruction_op *op,
1089 unsigned long v1, unsigned long v2)
1090 {
1091 unsigned long long out_val, mask;
1092 int i;
1093
1094 out_val = 0;
1095 for (i = 0; i < 8; i++) {
1096 mask = 0xffUL << (i * 8);
1097 if ((v1 & mask) == (v2 & mask))
1098 out_val |= mask;
1099 }
1100 op->val = out_val;
1101 }
1102
1103 /*
1104 * The size parameter is used to adjust the equivalent popcnt instruction.
1105 * popcntb = 8, popcntw = 32, popcntd = 64
1106 */
do_popcnt(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,int size)1107 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1108 struct instruction_op *op,
1109 unsigned long v1, int size)
1110 {
1111 unsigned long long out = v1;
1112
1113 out -= (out >> 1) & 0x5555555555555555ULL;
1114 out = (0x3333333333333333ULL & out) +
1115 (0x3333333333333333ULL & (out >> 2));
1116 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1117
1118 if (size == 8) { /* popcntb */
1119 op->val = out;
1120 return;
1121 }
1122 out += out >> 8;
1123 out += out >> 16;
1124 if (size == 32) { /* popcntw */
1125 op->val = out & 0x0000003f0000003fULL;
1126 return;
1127 }
1128
1129 out = (out + (out >> 32)) & 0x7f;
1130 op->val = out; /* popcntd */
1131 }
1132
1133 #ifdef CONFIG_PPC64
do_bpermd(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,unsigned long v2)1134 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1135 struct instruction_op *op,
1136 unsigned long v1, unsigned long v2)
1137 {
1138 unsigned char perm, idx;
1139 unsigned int i;
1140
1141 perm = 0;
1142 for (i = 0; i < 8; i++) {
1143 idx = (v1 >> (i * 8)) & 0xff;
1144 if (idx < 64)
1145 if (v2 & PPC_BIT(idx))
1146 perm |= 1 << i;
1147 }
1148 op->val = perm;
1149 }
1150 #endif /* CONFIG_PPC64 */
1151 /*
1152 * The size parameter adjusts the equivalent prty instruction.
1153 * prtyw = 32, prtyd = 64
1154 */
do_prty(const struct pt_regs * regs,struct instruction_op * op,unsigned long v,int size)1155 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1156 struct instruction_op *op,
1157 unsigned long v, int size)
1158 {
1159 unsigned long long res = v ^ (v >> 8);
1160
1161 res ^= res >> 16;
1162 if (size == 32) { /* prtyw */
1163 op->val = res & 0x0000000100000001ULL;
1164 return;
1165 }
1166
1167 res ^= res >> 32;
1168 op->val = res & 1; /*prtyd */
1169 }
1170
trap_compare(long v1,long v2)1171 static nokprobe_inline int trap_compare(long v1, long v2)
1172 {
1173 int ret = 0;
1174
1175 if (v1 < v2)
1176 ret |= 0x10;
1177 else if (v1 > v2)
1178 ret |= 0x08;
1179 else
1180 ret |= 0x04;
1181 if ((unsigned long)v1 < (unsigned long)v2)
1182 ret |= 0x02;
1183 else if ((unsigned long)v1 > (unsigned long)v2)
1184 ret |= 0x01;
1185 return ret;
1186 }
1187
1188 /*
1189 * Elements of 32-bit rotate and mask instructions.
1190 */
1191 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1192 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1193 #ifdef __powerpc64__
1194 #define MASK64_L(mb) (~0UL >> (mb))
1195 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1196 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1197 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1198 #else
1199 #define DATA32(x) (x)
1200 #endif
1201 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1202
1203 /*
1204 * Decode an instruction, and return information about it in *op
1205 * without changing *regs.
1206 * Integer arithmetic and logical instructions, branches, and barrier
1207 * instructions can be emulated just using the information in *op.
1208 *
1209 * Return value is 1 if the instruction can be emulated just by
1210 * updating *regs with the information in *op, -1 if we need the
1211 * GPRs but *regs doesn't contain the full register set, or 0
1212 * otherwise.
1213 */
analyse_instr(struct instruction_op * op,const struct pt_regs * regs,struct ppc_inst instr)1214 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1215 struct ppc_inst instr)
1216 {
1217 #ifdef CONFIG_PPC64
1218 unsigned int suffixopcode, prefixtype, prefix_r;
1219 #endif
1220 unsigned int opcode, ra, rb, rc, rd, spr, u;
1221 unsigned long int imm;
1222 unsigned long int val, val2;
1223 unsigned int mb, me, sh;
1224 unsigned int word, suffix;
1225 long ival;
1226
1227 word = ppc_inst_val(instr);
1228 suffix = ppc_inst_suffix(instr);
1229
1230 op->type = COMPUTE;
1231
1232 opcode = ppc_inst_primary_opcode(instr);
1233 switch (opcode) {
1234 case 16: /* bc */
1235 op->type = BRANCH;
1236 imm = (signed short)(word & 0xfffc);
1237 if ((word & 2) == 0)
1238 imm += regs->nip;
1239 op->val = truncate_if_32bit(regs->msr, imm);
1240 if (word & 1)
1241 op->type |= SETLK;
1242 if (branch_taken(word, regs, op))
1243 op->type |= BRTAKEN;
1244 return 1;
1245 #ifdef CONFIG_PPC64
1246 case 17: /* sc */
1247 if ((word & 0xfe2) == 2)
1248 op->type = SYSCALL;
1249 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1250 (word & 0xfe3) == 1) { /* scv */
1251 op->type = SYSCALL_VECTORED_0;
1252 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1253 goto unknown_opcode;
1254 } else
1255 op->type = UNKNOWN;
1256 return 0;
1257 #endif
1258 case 18: /* b */
1259 op->type = BRANCH | BRTAKEN;
1260 imm = word & 0x03fffffc;
1261 if (imm & 0x02000000)
1262 imm -= 0x04000000;
1263 if ((word & 2) == 0)
1264 imm += regs->nip;
1265 op->val = truncate_if_32bit(regs->msr, imm);
1266 if (word & 1)
1267 op->type |= SETLK;
1268 return 1;
1269 case 19:
1270 switch ((word >> 1) & 0x3ff) {
1271 case 0: /* mcrf */
1272 op->type = COMPUTE + SETCC;
1273 rd = 7 - ((word >> 23) & 0x7);
1274 ra = 7 - ((word >> 18) & 0x7);
1275 rd *= 4;
1276 ra *= 4;
1277 val = (regs->ccr >> ra) & 0xf;
1278 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1279 return 1;
1280
1281 case 16: /* bclr */
1282 case 528: /* bcctr */
1283 op->type = BRANCH;
1284 imm = (word & 0x400)? regs->ctr: regs->link;
1285 op->val = truncate_if_32bit(regs->msr, imm);
1286 if (word & 1)
1287 op->type |= SETLK;
1288 if (branch_taken(word, regs, op))
1289 op->type |= BRTAKEN;
1290 return 1;
1291
1292 case 18: /* rfid, scary */
1293 if (regs->msr & MSR_PR)
1294 goto priv;
1295 op->type = RFI;
1296 return 0;
1297
1298 case 150: /* isync */
1299 op->type = BARRIER | BARRIER_ISYNC;
1300 return 1;
1301
1302 case 33: /* crnor */
1303 case 129: /* crandc */
1304 case 193: /* crxor */
1305 case 225: /* crnand */
1306 case 257: /* crand */
1307 case 289: /* creqv */
1308 case 417: /* crorc */
1309 case 449: /* cror */
1310 op->type = COMPUTE + SETCC;
1311 ra = (word >> 16) & 0x1f;
1312 rb = (word >> 11) & 0x1f;
1313 rd = (word >> 21) & 0x1f;
1314 ra = (regs->ccr >> (31 - ra)) & 1;
1315 rb = (regs->ccr >> (31 - rb)) & 1;
1316 val = (word >> (6 + ra * 2 + rb)) & 1;
1317 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1318 (val << (31 - rd));
1319 return 1;
1320 }
1321 break;
1322 case 31:
1323 switch ((word >> 1) & 0x3ff) {
1324 case 598: /* sync */
1325 op->type = BARRIER + BARRIER_SYNC;
1326 #ifdef __powerpc64__
1327 switch ((word >> 21) & 3) {
1328 case 1: /* lwsync */
1329 op->type = BARRIER + BARRIER_LWSYNC;
1330 break;
1331 case 2: /* ptesync */
1332 op->type = BARRIER + BARRIER_PTESYNC;
1333 break;
1334 }
1335 #endif
1336 return 1;
1337
1338 case 854: /* eieio */
1339 op->type = BARRIER + BARRIER_EIEIO;
1340 return 1;
1341 }
1342 break;
1343 }
1344
1345 /* Following cases refer to regs->gpr[], so we need all regs */
1346 if (!FULL_REGS(regs))
1347 return -1;
1348
1349 rd = (word >> 21) & 0x1f;
1350 ra = (word >> 16) & 0x1f;
1351 rb = (word >> 11) & 0x1f;
1352 rc = (word >> 6) & 0x1f;
1353
1354 switch (opcode) {
1355 #ifdef __powerpc64__
1356 case 1:
1357 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1358 goto unknown_opcode;
1359
1360 prefix_r = GET_PREFIX_R(word);
1361 ra = GET_PREFIX_RA(suffix);
1362 rd = (suffix >> 21) & 0x1f;
1363 op->reg = rd;
1364 op->val = regs->gpr[rd];
1365 suffixopcode = get_op(suffix);
1366 prefixtype = (word >> 24) & 0x3;
1367 switch (prefixtype) {
1368 case 2:
1369 if (prefix_r && ra)
1370 return 0;
1371 switch (suffixopcode) {
1372 case 14: /* paddi */
1373 op->type = COMPUTE | PREFIXED;
1374 op->val = mlsd_8lsd_ea(word, suffix, regs);
1375 goto compute_done;
1376 }
1377 }
1378 break;
1379 case 2: /* tdi */
1380 if (rd & trap_compare(regs->gpr[ra], (short) word))
1381 goto trap;
1382 return 1;
1383 #endif
1384 case 3: /* twi */
1385 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1386 goto trap;
1387 return 1;
1388
1389 #ifdef __powerpc64__
1390 case 4:
1391 /*
1392 * There are very many instructions with this primary opcode
1393 * introduced in the ISA as early as v2.03. However, the ones
1394 * we currently emulate were all introduced with ISA 3.0
1395 */
1396 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1397 goto unknown_opcode;
1398
1399 switch (word & 0x3f) {
1400 case 48: /* maddhd */
1401 asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1402 "=r" (op->val) : "r" (regs->gpr[ra]),
1403 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1404 goto compute_done;
1405
1406 case 49: /* maddhdu */
1407 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1408 "=r" (op->val) : "r" (regs->gpr[ra]),
1409 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1410 goto compute_done;
1411
1412 case 51: /* maddld */
1413 asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1414 "=r" (op->val) : "r" (regs->gpr[ra]),
1415 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1416 goto compute_done;
1417 }
1418
1419 /*
1420 * There are other instructions from ISA 3.0 with the same
1421 * primary opcode which do not have emulation support yet.
1422 */
1423 goto unknown_opcode;
1424 #endif
1425
1426 case 7: /* mulli */
1427 op->val = regs->gpr[ra] * (short) word;
1428 goto compute_done;
1429
1430 case 8: /* subfic */
1431 imm = (short) word;
1432 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1433 return 1;
1434
1435 case 10: /* cmpli */
1436 imm = (unsigned short) word;
1437 val = regs->gpr[ra];
1438 #ifdef __powerpc64__
1439 if ((rd & 1) == 0)
1440 val = (unsigned int) val;
1441 #endif
1442 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1443 return 1;
1444
1445 case 11: /* cmpi */
1446 imm = (short) word;
1447 val = regs->gpr[ra];
1448 #ifdef __powerpc64__
1449 if ((rd & 1) == 0)
1450 val = (int) val;
1451 #endif
1452 do_cmp_signed(regs, op, val, imm, rd >> 2);
1453 return 1;
1454
1455 case 12: /* addic */
1456 imm = (short) word;
1457 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1458 return 1;
1459
1460 case 13: /* addic. */
1461 imm = (short) word;
1462 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1463 set_cr0(regs, op);
1464 return 1;
1465
1466 case 14: /* addi */
1467 imm = (short) word;
1468 if (ra)
1469 imm += regs->gpr[ra];
1470 op->val = imm;
1471 goto compute_done;
1472
1473 case 15: /* addis */
1474 imm = ((short) word) << 16;
1475 if (ra)
1476 imm += regs->gpr[ra];
1477 op->val = imm;
1478 goto compute_done;
1479
1480 case 19:
1481 if (((word >> 1) & 0x1f) == 2) {
1482 /* addpcis */
1483 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1484 goto unknown_opcode;
1485 imm = (short) (word & 0xffc1); /* d0 + d2 fields */
1486 imm |= (word >> 15) & 0x3e; /* d1 field */
1487 op->val = regs->nip + (imm << 16) + 4;
1488 goto compute_done;
1489 }
1490 op->type = UNKNOWN;
1491 return 0;
1492
1493 case 20: /* rlwimi */
1494 mb = (word >> 6) & 0x1f;
1495 me = (word >> 1) & 0x1f;
1496 val = DATA32(regs->gpr[rd]);
1497 imm = MASK32(mb, me);
1498 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1499 goto logical_done;
1500
1501 case 21: /* rlwinm */
1502 mb = (word >> 6) & 0x1f;
1503 me = (word >> 1) & 0x1f;
1504 val = DATA32(regs->gpr[rd]);
1505 op->val = ROTATE(val, rb) & MASK32(mb, me);
1506 goto logical_done;
1507
1508 case 23: /* rlwnm */
1509 mb = (word >> 6) & 0x1f;
1510 me = (word >> 1) & 0x1f;
1511 rb = regs->gpr[rb] & 0x1f;
1512 val = DATA32(regs->gpr[rd]);
1513 op->val = ROTATE(val, rb) & MASK32(mb, me);
1514 goto logical_done;
1515
1516 case 24: /* ori */
1517 op->val = regs->gpr[rd] | (unsigned short) word;
1518 goto logical_done_nocc;
1519
1520 case 25: /* oris */
1521 imm = (unsigned short) word;
1522 op->val = regs->gpr[rd] | (imm << 16);
1523 goto logical_done_nocc;
1524
1525 case 26: /* xori */
1526 op->val = regs->gpr[rd] ^ (unsigned short) word;
1527 goto logical_done_nocc;
1528
1529 case 27: /* xoris */
1530 imm = (unsigned short) word;
1531 op->val = regs->gpr[rd] ^ (imm << 16);
1532 goto logical_done_nocc;
1533
1534 case 28: /* andi. */
1535 op->val = regs->gpr[rd] & (unsigned short) word;
1536 set_cr0(regs, op);
1537 goto logical_done_nocc;
1538
1539 case 29: /* andis. */
1540 imm = (unsigned short) word;
1541 op->val = regs->gpr[rd] & (imm << 16);
1542 set_cr0(regs, op);
1543 goto logical_done_nocc;
1544
1545 #ifdef __powerpc64__
1546 case 30: /* rld* */
1547 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1548 val = regs->gpr[rd];
1549 if ((word & 0x10) == 0) {
1550 sh = rb | ((word & 2) << 4);
1551 val = ROTATE(val, sh);
1552 switch ((word >> 2) & 3) {
1553 case 0: /* rldicl */
1554 val &= MASK64_L(mb);
1555 break;
1556 case 1: /* rldicr */
1557 val &= MASK64_R(mb);
1558 break;
1559 case 2: /* rldic */
1560 val &= MASK64(mb, 63 - sh);
1561 break;
1562 case 3: /* rldimi */
1563 imm = MASK64(mb, 63 - sh);
1564 val = (regs->gpr[ra] & ~imm) |
1565 (val & imm);
1566 }
1567 op->val = val;
1568 goto logical_done;
1569 } else {
1570 sh = regs->gpr[rb] & 0x3f;
1571 val = ROTATE(val, sh);
1572 switch ((word >> 1) & 7) {
1573 case 0: /* rldcl */
1574 op->val = val & MASK64_L(mb);
1575 goto logical_done;
1576 case 1: /* rldcr */
1577 op->val = val & MASK64_R(mb);
1578 goto logical_done;
1579 }
1580 }
1581 #endif
1582 op->type = UNKNOWN; /* illegal instruction */
1583 return 0;
1584
1585 case 31:
1586 /* isel occupies 32 minor opcodes */
1587 if (((word >> 1) & 0x1f) == 15) {
1588 mb = (word >> 6) & 0x1f; /* bc field */
1589 val = (regs->ccr >> (31 - mb)) & 1;
1590 val2 = (ra) ? regs->gpr[ra] : 0;
1591
1592 op->val = (val) ? val2 : regs->gpr[rb];
1593 goto compute_done;
1594 }
1595
1596 switch ((word >> 1) & 0x3ff) {
1597 case 4: /* tw */
1598 if (rd == 0x1f ||
1599 (rd & trap_compare((int)regs->gpr[ra],
1600 (int)regs->gpr[rb])))
1601 goto trap;
1602 return 1;
1603 #ifdef __powerpc64__
1604 case 68: /* td */
1605 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1606 goto trap;
1607 return 1;
1608 #endif
1609 case 83: /* mfmsr */
1610 if (regs->msr & MSR_PR)
1611 goto priv;
1612 op->type = MFMSR;
1613 op->reg = rd;
1614 return 0;
1615 case 146: /* mtmsr */
1616 if (regs->msr & MSR_PR)
1617 goto priv;
1618 op->type = MTMSR;
1619 op->reg = rd;
1620 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1621 return 0;
1622 #ifdef CONFIG_PPC64
1623 case 178: /* mtmsrd */
1624 if (regs->msr & MSR_PR)
1625 goto priv;
1626 op->type = MTMSR;
1627 op->reg = rd;
1628 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1629 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1630 imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1631 op->val = imm;
1632 return 0;
1633 #endif
1634
1635 case 19: /* mfcr */
1636 imm = 0xffffffffUL;
1637 if ((word >> 20) & 1) {
1638 imm = 0xf0000000UL;
1639 for (sh = 0; sh < 8; ++sh) {
1640 if (word & (0x80000 >> sh))
1641 break;
1642 imm >>= 4;
1643 }
1644 }
1645 op->val = regs->ccr & imm;
1646 goto compute_done;
1647
1648 case 144: /* mtcrf */
1649 op->type = COMPUTE + SETCC;
1650 imm = 0xf0000000UL;
1651 val = regs->gpr[rd];
1652 op->ccval = regs->ccr;
1653 for (sh = 0; sh < 8; ++sh) {
1654 if (word & (0x80000 >> sh))
1655 op->ccval = (op->ccval & ~imm) |
1656 (val & imm);
1657 imm >>= 4;
1658 }
1659 return 1;
1660
1661 case 339: /* mfspr */
1662 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1663 op->type = MFSPR;
1664 op->reg = rd;
1665 op->spr = spr;
1666 if (spr == SPRN_XER || spr == SPRN_LR ||
1667 spr == SPRN_CTR)
1668 return 1;
1669 return 0;
1670
1671 case 467: /* mtspr */
1672 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1673 op->type = MTSPR;
1674 op->val = regs->gpr[rd];
1675 op->spr = spr;
1676 if (spr == SPRN_XER || spr == SPRN_LR ||
1677 spr == SPRN_CTR)
1678 return 1;
1679 return 0;
1680
1681 /*
1682 * Compare instructions
1683 */
1684 case 0: /* cmp */
1685 val = regs->gpr[ra];
1686 val2 = regs->gpr[rb];
1687 #ifdef __powerpc64__
1688 if ((rd & 1) == 0) {
1689 /* word (32-bit) compare */
1690 val = (int) val;
1691 val2 = (int) val2;
1692 }
1693 #endif
1694 do_cmp_signed(regs, op, val, val2, rd >> 2);
1695 return 1;
1696
1697 case 32: /* cmpl */
1698 val = regs->gpr[ra];
1699 val2 = regs->gpr[rb];
1700 #ifdef __powerpc64__
1701 if ((rd & 1) == 0) {
1702 /* word (32-bit) compare */
1703 val = (unsigned int) val;
1704 val2 = (unsigned int) val2;
1705 }
1706 #endif
1707 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1708 return 1;
1709
1710 case 508: /* cmpb */
1711 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1712 goto logical_done_nocc;
1713
1714 /*
1715 * Arithmetic instructions
1716 */
1717 case 8: /* subfc */
1718 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1719 regs->gpr[rb], 1);
1720 goto arith_done;
1721 #ifdef __powerpc64__
1722 case 9: /* mulhdu */
1723 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1724 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1725 goto arith_done;
1726 #endif
1727 case 10: /* addc */
1728 add_with_carry(regs, op, rd, regs->gpr[ra],
1729 regs->gpr[rb], 0);
1730 goto arith_done;
1731
1732 case 11: /* mulhwu */
1733 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1734 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1735 goto arith_done;
1736
1737 case 40: /* subf */
1738 op->val = regs->gpr[rb] - regs->gpr[ra];
1739 goto arith_done;
1740 #ifdef __powerpc64__
1741 case 73: /* mulhd */
1742 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1743 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1744 goto arith_done;
1745 #endif
1746 case 75: /* mulhw */
1747 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1748 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1749 goto arith_done;
1750
1751 case 104: /* neg */
1752 op->val = -regs->gpr[ra];
1753 goto arith_done;
1754
1755 case 136: /* subfe */
1756 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1757 regs->gpr[rb], regs->xer & XER_CA);
1758 goto arith_done;
1759
1760 case 138: /* adde */
1761 add_with_carry(regs, op, rd, regs->gpr[ra],
1762 regs->gpr[rb], regs->xer & XER_CA);
1763 goto arith_done;
1764
1765 case 200: /* subfze */
1766 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1767 regs->xer & XER_CA);
1768 goto arith_done;
1769
1770 case 202: /* addze */
1771 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1772 regs->xer & XER_CA);
1773 goto arith_done;
1774
1775 case 232: /* subfme */
1776 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1777 regs->xer & XER_CA);
1778 goto arith_done;
1779 #ifdef __powerpc64__
1780 case 233: /* mulld */
1781 op->val = regs->gpr[ra] * regs->gpr[rb];
1782 goto arith_done;
1783 #endif
1784 case 234: /* addme */
1785 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1786 regs->xer & XER_CA);
1787 goto arith_done;
1788
1789 case 235: /* mullw */
1790 op->val = (long)(int) regs->gpr[ra] *
1791 (int) regs->gpr[rb];
1792
1793 goto arith_done;
1794 #ifdef __powerpc64__
1795 case 265: /* modud */
1796 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1797 goto unknown_opcode;
1798 op->val = regs->gpr[ra] % regs->gpr[rb];
1799 goto compute_done;
1800 #endif
1801 case 266: /* add */
1802 op->val = regs->gpr[ra] + regs->gpr[rb];
1803 goto arith_done;
1804
1805 case 267: /* moduw */
1806 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1807 goto unknown_opcode;
1808 op->val = (unsigned int) regs->gpr[ra] %
1809 (unsigned int) regs->gpr[rb];
1810 goto compute_done;
1811 #ifdef __powerpc64__
1812 case 457: /* divdu */
1813 op->val = regs->gpr[ra] / regs->gpr[rb];
1814 goto arith_done;
1815 #endif
1816 case 459: /* divwu */
1817 op->val = (unsigned int) regs->gpr[ra] /
1818 (unsigned int) regs->gpr[rb];
1819 goto arith_done;
1820 #ifdef __powerpc64__
1821 case 489: /* divd */
1822 op->val = (long int) regs->gpr[ra] /
1823 (long int) regs->gpr[rb];
1824 goto arith_done;
1825 #endif
1826 case 491: /* divw */
1827 op->val = (int) regs->gpr[ra] /
1828 (int) regs->gpr[rb];
1829 goto arith_done;
1830 #ifdef __powerpc64__
1831 case 425: /* divde[.] */
1832 asm volatile(PPC_DIVDE(%0, %1, %2) :
1833 "=r" (op->val) : "r" (regs->gpr[ra]),
1834 "r" (regs->gpr[rb]));
1835 goto arith_done;
1836 case 393: /* divdeu[.] */
1837 asm volatile(PPC_DIVDEU(%0, %1, %2) :
1838 "=r" (op->val) : "r" (regs->gpr[ra]),
1839 "r" (regs->gpr[rb]));
1840 goto arith_done;
1841 #endif
1842 case 755: /* darn */
1843 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1844 goto unknown_opcode;
1845 switch (ra & 0x3) {
1846 case 0:
1847 /* 32-bit conditioned */
1848 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1849 goto compute_done;
1850
1851 case 1:
1852 /* 64-bit conditioned */
1853 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1854 goto compute_done;
1855
1856 case 2:
1857 /* 64-bit raw */
1858 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1859 goto compute_done;
1860 }
1861
1862 goto unknown_opcode;
1863 #ifdef __powerpc64__
1864 case 777: /* modsd */
1865 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1866 goto unknown_opcode;
1867 op->val = (long int) regs->gpr[ra] %
1868 (long int) regs->gpr[rb];
1869 goto compute_done;
1870 #endif
1871 case 779: /* modsw */
1872 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1873 goto unknown_opcode;
1874 op->val = (int) regs->gpr[ra] %
1875 (int) regs->gpr[rb];
1876 goto compute_done;
1877
1878
1879 /*
1880 * Logical instructions
1881 */
1882 case 26: /* cntlzw */
1883 val = (unsigned int) regs->gpr[rd];
1884 op->val = ( val ? __builtin_clz(val) : 32 );
1885 goto logical_done;
1886 #ifdef __powerpc64__
1887 case 58: /* cntlzd */
1888 val = regs->gpr[rd];
1889 op->val = ( val ? __builtin_clzl(val) : 64 );
1890 goto logical_done;
1891 #endif
1892 case 28: /* and */
1893 op->val = regs->gpr[rd] & regs->gpr[rb];
1894 goto logical_done;
1895
1896 case 60: /* andc */
1897 op->val = regs->gpr[rd] & ~regs->gpr[rb];
1898 goto logical_done;
1899
1900 case 122: /* popcntb */
1901 do_popcnt(regs, op, regs->gpr[rd], 8);
1902 goto logical_done_nocc;
1903
1904 case 124: /* nor */
1905 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1906 goto logical_done;
1907
1908 case 154: /* prtyw */
1909 do_prty(regs, op, regs->gpr[rd], 32);
1910 goto logical_done_nocc;
1911
1912 case 186: /* prtyd */
1913 do_prty(regs, op, regs->gpr[rd], 64);
1914 goto logical_done_nocc;
1915 #ifdef CONFIG_PPC64
1916 case 252: /* bpermd */
1917 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1918 goto logical_done_nocc;
1919 #endif
1920 case 284: /* xor */
1921 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1922 goto logical_done;
1923
1924 case 316: /* xor */
1925 op->val = regs->gpr[rd] ^ regs->gpr[rb];
1926 goto logical_done;
1927
1928 case 378: /* popcntw */
1929 do_popcnt(regs, op, regs->gpr[rd], 32);
1930 goto logical_done_nocc;
1931
1932 case 412: /* orc */
1933 op->val = regs->gpr[rd] | ~regs->gpr[rb];
1934 goto logical_done;
1935
1936 case 444: /* or */
1937 op->val = regs->gpr[rd] | regs->gpr[rb];
1938 goto logical_done;
1939
1940 case 476: /* nand */
1941 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1942 goto logical_done;
1943 #ifdef CONFIG_PPC64
1944 case 506: /* popcntd */
1945 do_popcnt(regs, op, regs->gpr[rd], 64);
1946 goto logical_done_nocc;
1947 #endif
1948 case 538: /* cnttzw */
1949 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1950 goto unknown_opcode;
1951 val = (unsigned int) regs->gpr[rd];
1952 op->val = (val ? __builtin_ctz(val) : 32);
1953 goto logical_done;
1954 #ifdef __powerpc64__
1955 case 570: /* cnttzd */
1956 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1957 goto unknown_opcode;
1958 val = regs->gpr[rd];
1959 op->val = (val ? __builtin_ctzl(val) : 64);
1960 goto logical_done;
1961 #endif
1962 case 922: /* extsh */
1963 op->val = (signed short) regs->gpr[rd];
1964 goto logical_done;
1965
1966 case 954: /* extsb */
1967 op->val = (signed char) regs->gpr[rd];
1968 goto logical_done;
1969 #ifdef __powerpc64__
1970 case 986: /* extsw */
1971 op->val = (signed int) regs->gpr[rd];
1972 goto logical_done;
1973 #endif
1974
1975 /*
1976 * Shift instructions
1977 */
1978 case 24: /* slw */
1979 sh = regs->gpr[rb] & 0x3f;
1980 if (sh < 32)
1981 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1982 else
1983 op->val = 0;
1984 goto logical_done;
1985
1986 case 536: /* srw */
1987 sh = regs->gpr[rb] & 0x3f;
1988 if (sh < 32)
1989 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1990 else
1991 op->val = 0;
1992 goto logical_done;
1993
1994 case 792: /* sraw */
1995 op->type = COMPUTE + SETREG + SETXER;
1996 sh = regs->gpr[rb] & 0x3f;
1997 ival = (signed int) regs->gpr[rd];
1998 op->val = ival >> (sh < 32 ? sh : 31);
1999 op->xerval = regs->xer;
2000 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
2001 op->xerval |= XER_CA;
2002 else
2003 op->xerval &= ~XER_CA;
2004 set_ca32(op, op->xerval & XER_CA);
2005 goto logical_done;
2006
2007 case 824: /* srawi */
2008 op->type = COMPUTE + SETREG + SETXER;
2009 sh = rb;
2010 ival = (signed int) regs->gpr[rd];
2011 op->val = ival >> sh;
2012 op->xerval = regs->xer;
2013 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2014 op->xerval |= XER_CA;
2015 else
2016 op->xerval &= ~XER_CA;
2017 set_ca32(op, op->xerval & XER_CA);
2018 goto logical_done;
2019
2020 #ifdef __powerpc64__
2021 case 27: /* sld */
2022 sh = regs->gpr[rb] & 0x7f;
2023 if (sh < 64)
2024 op->val = regs->gpr[rd] << sh;
2025 else
2026 op->val = 0;
2027 goto logical_done;
2028
2029 case 539: /* srd */
2030 sh = regs->gpr[rb] & 0x7f;
2031 if (sh < 64)
2032 op->val = regs->gpr[rd] >> sh;
2033 else
2034 op->val = 0;
2035 goto logical_done;
2036
2037 case 794: /* srad */
2038 op->type = COMPUTE + SETREG + SETXER;
2039 sh = regs->gpr[rb] & 0x7f;
2040 ival = (signed long int) regs->gpr[rd];
2041 op->val = ival >> (sh < 64 ? sh : 63);
2042 op->xerval = regs->xer;
2043 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2044 op->xerval |= XER_CA;
2045 else
2046 op->xerval &= ~XER_CA;
2047 set_ca32(op, op->xerval & XER_CA);
2048 goto logical_done;
2049
2050 case 826: /* sradi with sh_5 = 0 */
2051 case 827: /* sradi with sh_5 = 1 */
2052 op->type = COMPUTE + SETREG + SETXER;
2053 sh = rb | ((word & 2) << 4);
2054 ival = (signed long int) regs->gpr[rd];
2055 op->val = ival >> sh;
2056 op->xerval = regs->xer;
2057 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2058 op->xerval |= XER_CA;
2059 else
2060 op->xerval &= ~XER_CA;
2061 set_ca32(op, op->xerval & XER_CA);
2062 goto logical_done;
2063
2064 case 890: /* extswsli with sh_5 = 0 */
2065 case 891: /* extswsli with sh_5 = 1 */
2066 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2067 goto unknown_opcode;
2068 op->type = COMPUTE + SETREG;
2069 sh = rb | ((word & 2) << 4);
2070 val = (signed int) regs->gpr[rd];
2071 if (sh)
2072 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2073 else
2074 op->val = val;
2075 goto logical_done;
2076
2077 #endif /* __powerpc64__ */
2078
2079 /*
2080 * Cache instructions
2081 */
2082 case 54: /* dcbst */
2083 op->type = MKOP(CACHEOP, DCBST, 0);
2084 op->ea = xform_ea(word, regs);
2085 return 0;
2086
2087 case 86: /* dcbf */
2088 op->type = MKOP(CACHEOP, DCBF, 0);
2089 op->ea = xform_ea(word, regs);
2090 return 0;
2091
2092 case 246: /* dcbtst */
2093 op->type = MKOP(CACHEOP, DCBTST, 0);
2094 op->ea = xform_ea(word, regs);
2095 op->reg = rd;
2096 return 0;
2097
2098 case 278: /* dcbt */
2099 op->type = MKOP(CACHEOP, DCBTST, 0);
2100 op->ea = xform_ea(word, regs);
2101 op->reg = rd;
2102 return 0;
2103
2104 case 982: /* icbi */
2105 op->type = MKOP(CACHEOP, ICBI, 0);
2106 op->ea = xform_ea(word, regs);
2107 return 0;
2108
2109 case 1014: /* dcbz */
2110 op->type = MKOP(CACHEOP, DCBZ, 0);
2111 op->ea = xform_ea(word, regs);
2112 return 0;
2113 }
2114 break;
2115 }
2116
2117 /*
2118 * Loads and stores.
2119 */
2120 op->type = UNKNOWN;
2121 op->update_reg = ra;
2122 op->reg = rd;
2123 op->val = regs->gpr[rd];
2124 u = (word >> 20) & UPDATE;
2125 op->vsx_flags = 0;
2126
2127 switch (opcode) {
2128 case 31:
2129 u = word & UPDATE;
2130 op->ea = xform_ea(word, regs);
2131 switch ((word >> 1) & 0x3ff) {
2132 case 20: /* lwarx */
2133 op->type = MKOP(LARX, 0, 4);
2134 break;
2135
2136 case 150: /* stwcx. */
2137 op->type = MKOP(STCX, 0, 4);
2138 break;
2139
2140 #ifdef __powerpc64__
2141 case 84: /* ldarx */
2142 op->type = MKOP(LARX, 0, 8);
2143 break;
2144
2145 case 214: /* stdcx. */
2146 op->type = MKOP(STCX, 0, 8);
2147 break;
2148
2149 case 52: /* lbarx */
2150 op->type = MKOP(LARX, 0, 1);
2151 break;
2152
2153 case 694: /* stbcx. */
2154 op->type = MKOP(STCX, 0, 1);
2155 break;
2156
2157 case 116: /* lharx */
2158 op->type = MKOP(LARX, 0, 2);
2159 break;
2160
2161 case 726: /* sthcx. */
2162 op->type = MKOP(STCX, 0, 2);
2163 break;
2164
2165 case 276: /* lqarx */
2166 if (!((rd & 1) || rd == ra || rd == rb))
2167 op->type = MKOP(LARX, 0, 16);
2168 break;
2169
2170 case 182: /* stqcx. */
2171 if (!(rd & 1))
2172 op->type = MKOP(STCX, 0, 16);
2173 break;
2174 #endif
2175
2176 case 23: /* lwzx */
2177 case 55: /* lwzux */
2178 op->type = MKOP(LOAD, u, 4);
2179 break;
2180
2181 case 87: /* lbzx */
2182 case 119: /* lbzux */
2183 op->type = MKOP(LOAD, u, 1);
2184 break;
2185
2186 #ifdef CONFIG_ALTIVEC
2187 /*
2188 * Note: for the load/store vector element instructions,
2189 * bits of the EA say which field of the VMX register to use.
2190 */
2191 case 7: /* lvebx */
2192 op->type = MKOP(LOAD_VMX, 0, 1);
2193 op->element_size = 1;
2194 break;
2195
2196 case 39: /* lvehx */
2197 op->type = MKOP(LOAD_VMX, 0, 2);
2198 op->element_size = 2;
2199 break;
2200
2201 case 71: /* lvewx */
2202 op->type = MKOP(LOAD_VMX, 0, 4);
2203 op->element_size = 4;
2204 break;
2205
2206 case 103: /* lvx */
2207 case 359: /* lvxl */
2208 op->type = MKOP(LOAD_VMX, 0, 16);
2209 op->element_size = 16;
2210 break;
2211
2212 case 135: /* stvebx */
2213 op->type = MKOP(STORE_VMX, 0, 1);
2214 op->element_size = 1;
2215 break;
2216
2217 case 167: /* stvehx */
2218 op->type = MKOP(STORE_VMX, 0, 2);
2219 op->element_size = 2;
2220 break;
2221
2222 case 199: /* stvewx */
2223 op->type = MKOP(STORE_VMX, 0, 4);
2224 op->element_size = 4;
2225 break;
2226
2227 case 231: /* stvx */
2228 case 487: /* stvxl */
2229 op->type = MKOP(STORE_VMX, 0, 16);
2230 break;
2231 #endif /* CONFIG_ALTIVEC */
2232
2233 #ifdef __powerpc64__
2234 case 21: /* ldx */
2235 case 53: /* ldux */
2236 op->type = MKOP(LOAD, u, 8);
2237 break;
2238
2239 case 149: /* stdx */
2240 case 181: /* stdux */
2241 op->type = MKOP(STORE, u, 8);
2242 break;
2243 #endif
2244
2245 case 151: /* stwx */
2246 case 183: /* stwux */
2247 op->type = MKOP(STORE, u, 4);
2248 break;
2249
2250 case 215: /* stbx */
2251 case 247: /* stbux */
2252 op->type = MKOP(STORE, u, 1);
2253 break;
2254
2255 case 279: /* lhzx */
2256 case 311: /* lhzux */
2257 op->type = MKOP(LOAD, u, 2);
2258 break;
2259
2260 #ifdef __powerpc64__
2261 case 341: /* lwax */
2262 case 373: /* lwaux */
2263 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2264 break;
2265 #endif
2266
2267 case 343: /* lhax */
2268 case 375: /* lhaux */
2269 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2270 break;
2271
2272 case 407: /* sthx */
2273 case 439: /* sthux */
2274 op->type = MKOP(STORE, u, 2);
2275 break;
2276
2277 #ifdef __powerpc64__
2278 case 532: /* ldbrx */
2279 op->type = MKOP(LOAD, BYTEREV, 8);
2280 break;
2281
2282 #endif
2283 case 533: /* lswx */
2284 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2285 break;
2286
2287 case 534: /* lwbrx */
2288 op->type = MKOP(LOAD, BYTEREV, 4);
2289 break;
2290
2291 case 597: /* lswi */
2292 if (rb == 0)
2293 rb = 32; /* # bytes to load */
2294 op->type = MKOP(LOAD_MULTI, 0, rb);
2295 op->ea = ra ? regs->gpr[ra] : 0;
2296 break;
2297
2298 #ifdef CONFIG_PPC_FPU
2299 case 535: /* lfsx */
2300 case 567: /* lfsux */
2301 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2302 break;
2303
2304 case 599: /* lfdx */
2305 case 631: /* lfdux */
2306 op->type = MKOP(LOAD_FP, u, 8);
2307 break;
2308
2309 case 663: /* stfsx */
2310 case 695: /* stfsux */
2311 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2312 break;
2313
2314 case 727: /* stfdx */
2315 case 759: /* stfdux */
2316 op->type = MKOP(STORE_FP, u, 8);
2317 break;
2318
2319 #ifdef __powerpc64__
2320 case 791: /* lfdpx */
2321 op->type = MKOP(LOAD_FP, 0, 16);
2322 break;
2323
2324 case 855: /* lfiwax */
2325 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2326 break;
2327
2328 case 887: /* lfiwzx */
2329 op->type = MKOP(LOAD_FP, 0, 4);
2330 break;
2331
2332 case 919: /* stfdpx */
2333 op->type = MKOP(STORE_FP, 0, 16);
2334 break;
2335
2336 case 983: /* stfiwx */
2337 op->type = MKOP(STORE_FP, 0, 4);
2338 break;
2339 #endif /* __powerpc64 */
2340 #endif /* CONFIG_PPC_FPU */
2341
2342 #ifdef __powerpc64__
2343 case 660: /* stdbrx */
2344 op->type = MKOP(STORE, BYTEREV, 8);
2345 op->val = byterev_8(regs->gpr[rd]);
2346 break;
2347
2348 #endif
2349 case 661: /* stswx */
2350 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2351 break;
2352
2353 case 662: /* stwbrx */
2354 op->type = MKOP(STORE, BYTEREV, 4);
2355 op->val = byterev_4(regs->gpr[rd]);
2356 break;
2357
2358 case 725: /* stswi */
2359 if (rb == 0)
2360 rb = 32; /* # bytes to store */
2361 op->type = MKOP(STORE_MULTI, 0, rb);
2362 op->ea = ra ? regs->gpr[ra] : 0;
2363 break;
2364
2365 case 790: /* lhbrx */
2366 op->type = MKOP(LOAD, BYTEREV, 2);
2367 break;
2368
2369 case 918: /* sthbrx */
2370 op->type = MKOP(STORE, BYTEREV, 2);
2371 op->val = byterev_2(regs->gpr[rd]);
2372 break;
2373
2374 #ifdef CONFIG_VSX
2375 case 12: /* lxsiwzx */
2376 op->reg = rd | ((word & 1) << 5);
2377 op->type = MKOP(LOAD_VSX, 0, 4);
2378 op->element_size = 8;
2379 break;
2380
2381 case 76: /* lxsiwax */
2382 op->reg = rd | ((word & 1) << 5);
2383 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2384 op->element_size = 8;
2385 break;
2386
2387 case 140: /* stxsiwx */
2388 op->reg = rd | ((word & 1) << 5);
2389 op->type = MKOP(STORE_VSX, 0, 4);
2390 op->element_size = 8;
2391 break;
2392
2393 case 268: /* lxvx */
2394 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2395 goto unknown_opcode;
2396 op->reg = rd | ((word & 1) << 5);
2397 op->type = MKOP(LOAD_VSX, 0, 16);
2398 op->element_size = 16;
2399 op->vsx_flags = VSX_CHECK_VEC;
2400 break;
2401
2402 case 269: /* lxvl */
2403 case 301: { /* lxvll */
2404 int nb;
2405 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2406 goto unknown_opcode;
2407 op->reg = rd | ((word & 1) << 5);
2408 op->ea = ra ? regs->gpr[ra] : 0;
2409 nb = regs->gpr[rb] & 0xff;
2410 if (nb > 16)
2411 nb = 16;
2412 op->type = MKOP(LOAD_VSX, 0, nb);
2413 op->element_size = 16;
2414 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2415 VSX_CHECK_VEC;
2416 break;
2417 }
2418 case 332: /* lxvdsx */
2419 op->reg = rd | ((word & 1) << 5);
2420 op->type = MKOP(LOAD_VSX, 0, 8);
2421 op->element_size = 8;
2422 op->vsx_flags = VSX_SPLAT;
2423 break;
2424
2425 case 364: /* lxvwsx */
2426 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2427 goto unknown_opcode;
2428 op->reg = rd | ((word & 1) << 5);
2429 op->type = MKOP(LOAD_VSX, 0, 4);
2430 op->element_size = 4;
2431 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2432 break;
2433
2434 case 396: /* stxvx */
2435 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2436 goto unknown_opcode;
2437 op->reg = rd | ((word & 1) << 5);
2438 op->type = MKOP(STORE_VSX, 0, 16);
2439 op->element_size = 16;
2440 op->vsx_flags = VSX_CHECK_VEC;
2441 break;
2442
2443 case 397: /* stxvl */
2444 case 429: { /* stxvll */
2445 int nb;
2446 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2447 goto unknown_opcode;
2448 op->reg = rd | ((word & 1) << 5);
2449 op->ea = ra ? regs->gpr[ra] : 0;
2450 nb = regs->gpr[rb] & 0xff;
2451 if (nb > 16)
2452 nb = 16;
2453 op->type = MKOP(STORE_VSX, 0, nb);
2454 op->element_size = 16;
2455 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2456 VSX_CHECK_VEC;
2457 break;
2458 }
2459 case 524: /* lxsspx */
2460 op->reg = rd | ((word & 1) << 5);
2461 op->type = MKOP(LOAD_VSX, 0, 4);
2462 op->element_size = 8;
2463 op->vsx_flags = VSX_FPCONV;
2464 break;
2465
2466 case 588: /* lxsdx */
2467 op->reg = rd | ((word & 1) << 5);
2468 op->type = MKOP(LOAD_VSX, 0, 8);
2469 op->element_size = 8;
2470 break;
2471
2472 case 652: /* stxsspx */
2473 op->reg = rd | ((word & 1) << 5);
2474 op->type = MKOP(STORE_VSX, 0, 4);
2475 op->element_size = 8;
2476 op->vsx_flags = VSX_FPCONV;
2477 break;
2478
2479 case 716: /* stxsdx */
2480 op->reg = rd | ((word & 1) << 5);
2481 op->type = MKOP(STORE_VSX, 0, 8);
2482 op->element_size = 8;
2483 break;
2484
2485 case 780: /* lxvw4x */
2486 op->reg = rd | ((word & 1) << 5);
2487 op->type = MKOP(LOAD_VSX, 0, 16);
2488 op->element_size = 4;
2489 break;
2490
2491 case 781: /* lxsibzx */
2492 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2493 goto unknown_opcode;
2494 op->reg = rd | ((word & 1) << 5);
2495 op->type = MKOP(LOAD_VSX, 0, 1);
2496 op->element_size = 8;
2497 op->vsx_flags = VSX_CHECK_VEC;
2498 break;
2499
2500 case 812: /* lxvh8x */
2501 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2502 goto unknown_opcode;
2503 op->reg = rd | ((word & 1) << 5);
2504 op->type = MKOP(LOAD_VSX, 0, 16);
2505 op->element_size = 2;
2506 op->vsx_flags = VSX_CHECK_VEC;
2507 break;
2508
2509 case 813: /* lxsihzx */
2510 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2511 goto unknown_opcode;
2512 op->reg = rd | ((word & 1) << 5);
2513 op->type = MKOP(LOAD_VSX, 0, 2);
2514 op->element_size = 8;
2515 op->vsx_flags = VSX_CHECK_VEC;
2516 break;
2517
2518 case 844: /* lxvd2x */
2519 op->reg = rd | ((word & 1) << 5);
2520 op->type = MKOP(LOAD_VSX, 0, 16);
2521 op->element_size = 8;
2522 break;
2523
2524 case 876: /* lxvb16x */
2525 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2526 goto unknown_opcode;
2527 op->reg = rd | ((word & 1) << 5);
2528 op->type = MKOP(LOAD_VSX, 0, 16);
2529 op->element_size = 1;
2530 op->vsx_flags = VSX_CHECK_VEC;
2531 break;
2532
2533 case 908: /* stxvw4x */
2534 op->reg = rd | ((word & 1) << 5);
2535 op->type = MKOP(STORE_VSX, 0, 16);
2536 op->element_size = 4;
2537 break;
2538
2539 case 909: /* stxsibx */
2540 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2541 goto unknown_opcode;
2542 op->reg = rd | ((word & 1) << 5);
2543 op->type = MKOP(STORE_VSX, 0, 1);
2544 op->element_size = 8;
2545 op->vsx_flags = VSX_CHECK_VEC;
2546 break;
2547
2548 case 940: /* stxvh8x */
2549 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2550 goto unknown_opcode;
2551 op->reg = rd | ((word & 1) << 5);
2552 op->type = MKOP(STORE_VSX, 0, 16);
2553 op->element_size = 2;
2554 op->vsx_flags = VSX_CHECK_VEC;
2555 break;
2556
2557 case 941: /* stxsihx */
2558 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2559 goto unknown_opcode;
2560 op->reg = rd | ((word & 1) << 5);
2561 op->type = MKOP(STORE_VSX, 0, 2);
2562 op->element_size = 8;
2563 op->vsx_flags = VSX_CHECK_VEC;
2564 break;
2565
2566 case 972: /* stxvd2x */
2567 op->reg = rd | ((word & 1) << 5);
2568 op->type = MKOP(STORE_VSX, 0, 16);
2569 op->element_size = 8;
2570 break;
2571
2572 case 1004: /* stxvb16x */
2573 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2574 goto unknown_opcode;
2575 op->reg = rd | ((word & 1) << 5);
2576 op->type = MKOP(STORE_VSX, 0, 16);
2577 op->element_size = 1;
2578 op->vsx_flags = VSX_CHECK_VEC;
2579 break;
2580
2581 #endif /* CONFIG_VSX */
2582 }
2583 break;
2584
2585 case 32: /* lwz */
2586 case 33: /* lwzu */
2587 op->type = MKOP(LOAD, u, 4);
2588 op->ea = dform_ea(word, regs);
2589 break;
2590
2591 case 34: /* lbz */
2592 case 35: /* lbzu */
2593 op->type = MKOP(LOAD, u, 1);
2594 op->ea = dform_ea(word, regs);
2595 break;
2596
2597 case 36: /* stw */
2598 case 37: /* stwu */
2599 op->type = MKOP(STORE, u, 4);
2600 op->ea = dform_ea(word, regs);
2601 break;
2602
2603 case 38: /* stb */
2604 case 39: /* stbu */
2605 op->type = MKOP(STORE, u, 1);
2606 op->ea = dform_ea(word, regs);
2607 break;
2608
2609 case 40: /* lhz */
2610 case 41: /* lhzu */
2611 op->type = MKOP(LOAD, u, 2);
2612 op->ea = dform_ea(word, regs);
2613 break;
2614
2615 case 42: /* lha */
2616 case 43: /* lhau */
2617 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2618 op->ea = dform_ea(word, regs);
2619 break;
2620
2621 case 44: /* sth */
2622 case 45: /* sthu */
2623 op->type = MKOP(STORE, u, 2);
2624 op->ea = dform_ea(word, regs);
2625 break;
2626
2627 case 46: /* lmw */
2628 if (ra >= rd)
2629 break; /* invalid form, ra in range to load */
2630 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2631 op->ea = dform_ea(word, regs);
2632 break;
2633
2634 case 47: /* stmw */
2635 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2636 op->ea = dform_ea(word, regs);
2637 break;
2638
2639 #ifdef CONFIG_PPC_FPU
2640 case 48: /* lfs */
2641 case 49: /* lfsu */
2642 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2643 op->ea = dform_ea(word, regs);
2644 break;
2645
2646 case 50: /* lfd */
2647 case 51: /* lfdu */
2648 op->type = MKOP(LOAD_FP, u, 8);
2649 op->ea = dform_ea(word, regs);
2650 break;
2651
2652 case 52: /* stfs */
2653 case 53: /* stfsu */
2654 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2655 op->ea = dform_ea(word, regs);
2656 break;
2657
2658 case 54: /* stfd */
2659 case 55: /* stfdu */
2660 op->type = MKOP(STORE_FP, u, 8);
2661 op->ea = dform_ea(word, regs);
2662 break;
2663 #endif
2664
2665 #ifdef __powerpc64__
2666 case 56: /* lq */
2667 if (!((rd & 1) || (rd == ra)))
2668 op->type = MKOP(LOAD, 0, 16);
2669 op->ea = dqform_ea(word, regs);
2670 break;
2671 #endif
2672
2673 #ifdef CONFIG_VSX
2674 case 57: /* lfdp, lxsd, lxssp */
2675 op->ea = dsform_ea(word, regs);
2676 switch (word & 3) {
2677 case 0: /* lfdp */
2678 if (rd & 1)
2679 break; /* reg must be even */
2680 op->type = MKOP(LOAD_FP, 0, 16);
2681 break;
2682 case 2: /* lxsd */
2683 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2684 goto unknown_opcode;
2685 op->reg = rd + 32;
2686 op->type = MKOP(LOAD_VSX, 0, 8);
2687 op->element_size = 8;
2688 op->vsx_flags = VSX_CHECK_VEC;
2689 break;
2690 case 3: /* lxssp */
2691 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2692 goto unknown_opcode;
2693 op->reg = rd + 32;
2694 op->type = MKOP(LOAD_VSX, 0, 4);
2695 op->element_size = 8;
2696 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2697 break;
2698 }
2699 break;
2700 #endif /* CONFIG_VSX */
2701
2702 #ifdef __powerpc64__
2703 case 58: /* ld[u], lwa */
2704 op->ea = dsform_ea(word, regs);
2705 switch (word & 3) {
2706 case 0: /* ld */
2707 op->type = MKOP(LOAD, 0, 8);
2708 break;
2709 case 1: /* ldu */
2710 op->type = MKOP(LOAD, UPDATE, 8);
2711 break;
2712 case 2: /* lwa */
2713 op->type = MKOP(LOAD, SIGNEXT, 4);
2714 break;
2715 }
2716 break;
2717 #endif
2718
2719 #ifdef CONFIG_VSX
2720 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2721 switch (word & 7) {
2722 case 0: /* stfdp with LSB of DS field = 0 */
2723 case 4: /* stfdp with LSB of DS field = 1 */
2724 op->ea = dsform_ea(word, regs);
2725 op->type = MKOP(STORE_FP, 0, 16);
2726 break;
2727
2728 case 1: /* lxv */
2729 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2730 goto unknown_opcode;
2731 op->ea = dqform_ea(word, regs);
2732 if (word & 8)
2733 op->reg = rd + 32;
2734 op->type = MKOP(LOAD_VSX, 0, 16);
2735 op->element_size = 16;
2736 op->vsx_flags = VSX_CHECK_VEC;
2737 break;
2738
2739 case 2: /* stxsd with LSB of DS field = 0 */
2740 case 6: /* stxsd with LSB of DS field = 1 */
2741 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2742 goto unknown_opcode;
2743 op->ea = dsform_ea(word, regs);
2744 op->reg = rd + 32;
2745 op->type = MKOP(STORE_VSX, 0, 8);
2746 op->element_size = 8;
2747 op->vsx_flags = VSX_CHECK_VEC;
2748 break;
2749
2750 case 3: /* stxssp with LSB of DS field = 0 */
2751 case 7: /* stxssp with LSB of DS field = 1 */
2752 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2753 goto unknown_opcode;
2754 op->ea = dsform_ea(word, regs);
2755 op->reg = rd + 32;
2756 op->type = MKOP(STORE_VSX, 0, 4);
2757 op->element_size = 8;
2758 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2759 break;
2760
2761 case 5: /* stxv */
2762 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2763 goto unknown_opcode;
2764 op->ea = dqform_ea(word, regs);
2765 if (word & 8)
2766 op->reg = rd + 32;
2767 op->type = MKOP(STORE_VSX, 0, 16);
2768 op->element_size = 16;
2769 op->vsx_flags = VSX_CHECK_VEC;
2770 break;
2771 }
2772 break;
2773 #endif /* CONFIG_VSX */
2774
2775 #ifdef __powerpc64__
2776 case 62: /* std[u] */
2777 op->ea = dsform_ea(word, regs);
2778 switch (word & 3) {
2779 case 0: /* std */
2780 op->type = MKOP(STORE, 0, 8);
2781 break;
2782 case 1: /* stdu */
2783 op->type = MKOP(STORE, UPDATE, 8);
2784 break;
2785 case 2: /* stq */
2786 if (!(rd & 1))
2787 op->type = MKOP(STORE, 0, 16);
2788 break;
2789 }
2790 break;
2791 case 1: /* Prefixed instructions */
2792 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2793 goto unknown_opcode;
2794
2795 prefix_r = GET_PREFIX_R(word);
2796 ra = GET_PREFIX_RA(suffix);
2797 op->update_reg = ra;
2798 rd = (suffix >> 21) & 0x1f;
2799 op->reg = rd;
2800 op->val = regs->gpr[rd];
2801
2802 suffixopcode = get_op(suffix);
2803 prefixtype = (word >> 24) & 0x3;
2804 switch (prefixtype) {
2805 case 0: /* Type 00 Eight-Byte Load/Store */
2806 if (prefix_r && ra)
2807 break;
2808 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2809 switch (suffixopcode) {
2810 case 41: /* plwa */
2811 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2812 break;
2813 #ifdef CONFIG_VSX
2814 case 42: /* plxsd */
2815 op->reg = rd + 32;
2816 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2817 op->element_size = 8;
2818 op->vsx_flags = VSX_CHECK_VEC;
2819 break;
2820 case 43: /* plxssp */
2821 op->reg = rd + 32;
2822 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2823 op->element_size = 8;
2824 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2825 break;
2826 case 46: /* pstxsd */
2827 op->reg = rd + 32;
2828 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2829 op->element_size = 8;
2830 op->vsx_flags = VSX_CHECK_VEC;
2831 break;
2832 case 47: /* pstxssp */
2833 op->reg = rd + 32;
2834 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2835 op->element_size = 8;
2836 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2837 break;
2838 case 51: /* plxv1 */
2839 op->reg += 32;
2840 fallthrough;
2841 case 50: /* plxv0 */
2842 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2843 op->element_size = 16;
2844 op->vsx_flags = VSX_CHECK_VEC;
2845 break;
2846 case 55: /* pstxv1 */
2847 op->reg = rd + 32;
2848 fallthrough;
2849 case 54: /* pstxv0 */
2850 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2851 op->element_size = 16;
2852 op->vsx_flags = VSX_CHECK_VEC;
2853 break;
2854 #endif /* CONFIG_VSX */
2855 case 56: /* plq */
2856 op->type = MKOP(LOAD, PREFIXED, 16);
2857 break;
2858 case 57: /* pld */
2859 op->type = MKOP(LOAD, PREFIXED, 8);
2860 break;
2861 case 60: /* pstq */
2862 op->type = MKOP(STORE, PREFIXED, 16);
2863 break;
2864 case 61: /* pstd */
2865 op->type = MKOP(STORE, PREFIXED, 8);
2866 break;
2867 }
2868 break;
2869 case 1: /* Type 01 Eight-Byte Register-to-Register */
2870 break;
2871 case 2: /* Type 10 Modified Load/Store */
2872 if (prefix_r && ra)
2873 break;
2874 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2875 switch (suffixopcode) {
2876 case 32: /* plwz */
2877 op->type = MKOP(LOAD, PREFIXED, 4);
2878 break;
2879 case 34: /* plbz */
2880 op->type = MKOP(LOAD, PREFIXED, 1);
2881 break;
2882 case 36: /* pstw */
2883 op->type = MKOP(STORE, PREFIXED, 4);
2884 break;
2885 case 38: /* pstb */
2886 op->type = MKOP(STORE, PREFIXED, 1);
2887 break;
2888 case 40: /* plhz */
2889 op->type = MKOP(LOAD, PREFIXED, 2);
2890 break;
2891 case 42: /* plha */
2892 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2893 break;
2894 case 44: /* psth */
2895 op->type = MKOP(STORE, PREFIXED, 2);
2896 break;
2897 case 48: /* plfs */
2898 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
2899 break;
2900 case 50: /* plfd */
2901 op->type = MKOP(LOAD_FP, PREFIXED, 8);
2902 break;
2903 case 52: /* pstfs */
2904 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
2905 break;
2906 case 54: /* pstfd */
2907 op->type = MKOP(STORE_FP, PREFIXED, 8);
2908 break;
2909 }
2910 break;
2911 case 3: /* Type 11 Modified Register-to-Register */
2912 break;
2913 }
2914 #endif /* __powerpc64__ */
2915
2916 }
2917
2918 if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {
2919 switch (GETTYPE(op->type)) {
2920 case LOAD:
2921 if (ra == rd)
2922 goto unknown_opcode;
2923 fallthrough;
2924 case STORE:
2925 case LOAD_FP:
2926 case STORE_FP:
2927 if (ra == 0)
2928 goto unknown_opcode;
2929 }
2930 }
2931
2932 #ifdef CONFIG_VSX
2933 if ((GETTYPE(op->type) == LOAD_VSX ||
2934 GETTYPE(op->type) == STORE_VSX) &&
2935 !cpu_has_feature(CPU_FTR_VSX)) {
2936 return -1;
2937 }
2938 #endif /* CONFIG_VSX */
2939
2940 return 0;
2941
2942 unknown_opcode:
2943 op->type = UNKNOWN;
2944 return 0;
2945
2946 logical_done:
2947 if (word & 1)
2948 set_cr0(regs, op);
2949 logical_done_nocc:
2950 op->reg = ra;
2951 op->type |= SETREG;
2952 return 1;
2953
2954 arith_done:
2955 if (word & 1)
2956 set_cr0(regs, op);
2957 compute_done:
2958 op->reg = rd;
2959 op->type |= SETREG;
2960 return 1;
2961
2962 priv:
2963 op->type = INTERRUPT | 0x700;
2964 op->val = SRR1_PROGPRIV;
2965 return 0;
2966
2967 trap:
2968 op->type = INTERRUPT | 0x700;
2969 op->val = SRR1_PROGTRAP;
2970 return 0;
2971 }
2972 EXPORT_SYMBOL_GPL(analyse_instr);
2973 NOKPROBE_SYMBOL(analyse_instr);
2974
2975 /*
2976 * For PPC32 we always use stwu with r1 to change the stack pointer.
2977 * So this emulated store may corrupt the exception frame, now we
2978 * have to provide the exception frame trampoline, which is pushed
2979 * below the kprobed function stack. So we only update gpr[1] but
2980 * don't emulate the real store operation. We will do real store
2981 * operation safely in exception return code by checking this flag.
2982 */
handle_stack_update(unsigned long ea,struct pt_regs * regs)2983 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2984 {
2985 #ifdef CONFIG_PPC32
2986 /*
2987 * Check if we will touch kernel stack overflow
2988 */
2989 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2990 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2991 return -EINVAL;
2992 }
2993 #endif /* CONFIG_PPC32 */
2994 /*
2995 * Check if we already set since that means we'll
2996 * lose the previous value.
2997 */
2998 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2999 set_thread_flag(TIF_EMULATE_STACK_STORE);
3000 return 0;
3001 }
3002
do_signext(unsigned long * valp,int size)3003 static nokprobe_inline void do_signext(unsigned long *valp, int size)
3004 {
3005 switch (size) {
3006 case 2:
3007 *valp = (signed short) *valp;
3008 break;
3009 case 4:
3010 *valp = (signed int) *valp;
3011 break;
3012 }
3013 }
3014
do_byterev(unsigned long * valp,int size)3015 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3016 {
3017 switch (size) {
3018 case 2:
3019 *valp = byterev_2(*valp);
3020 break;
3021 case 4:
3022 *valp = byterev_4(*valp);
3023 break;
3024 #ifdef __powerpc64__
3025 case 8:
3026 *valp = byterev_8(*valp);
3027 break;
3028 #endif
3029 }
3030 }
3031
3032 /*
3033 * Emulate an instruction that can be executed just by updating
3034 * fields in *regs.
3035 */
emulate_update_regs(struct pt_regs * regs,struct instruction_op * op)3036 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3037 {
3038 unsigned long next_pc;
3039
3040 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3041 switch (GETTYPE(op->type)) {
3042 case COMPUTE:
3043 if (op->type & SETREG)
3044 regs->gpr[op->reg] = op->val;
3045 if (op->type & SETCC)
3046 regs->ccr = op->ccval;
3047 if (op->type & SETXER)
3048 regs->xer = op->xerval;
3049 break;
3050
3051 case BRANCH:
3052 if (op->type & SETLK)
3053 regs->link = next_pc;
3054 if (op->type & BRTAKEN)
3055 next_pc = op->val;
3056 if (op->type & DECCTR)
3057 --regs->ctr;
3058 break;
3059
3060 case BARRIER:
3061 switch (op->type & BARRIER_MASK) {
3062 case BARRIER_SYNC:
3063 mb();
3064 break;
3065 case BARRIER_ISYNC:
3066 isync();
3067 break;
3068 case BARRIER_EIEIO:
3069 eieio();
3070 break;
3071 #ifdef CONFIG_PPC64
3072 case BARRIER_LWSYNC:
3073 asm volatile("lwsync" : : : "memory");
3074 break;
3075 case BARRIER_PTESYNC:
3076 asm volatile("ptesync" : : : "memory");
3077 break;
3078 #endif
3079 }
3080 break;
3081
3082 case MFSPR:
3083 switch (op->spr) {
3084 case SPRN_XER:
3085 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3086 break;
3087 case SPRN_LR:
3088 regs->gpr[op->reg] = regs->link;
3089 break;
3090 case SPRN_CTR:
3091 regs->gpr[op->reg] = regs->ctr;
3092 break;
3093 default:
3094 WARN_ON_ONCE(1);
3095 }
3096 break;
3097
3098 case MTSPR:
3099 switch (op->spr) {
3100 case SPRN_XER:
3101 regs->xer = op->val & 0xffffffffUL;
3102 break;
3103 case SPRN_LR:
3104 regs->link = op->val;
3105 break;
3106 case SPRN_CTR:
3107 regs->ctr = op->val;
3108 break;
3109 default:
3110 WARN_ON_ONCE(1);
3111 }
3112 break;
3113
3114 default:
3115 WARN_ON_ONCE(1);
3116 }
3117 regs->nip = next_pc;
3118 }
3119 NOKPROBE_SYMBOL(emulate_update_regs);
3120
3121 /*
3122 * Emulate a previously-analysed load or store instruction.
3123 * Return values are:
3124 * 0 = instruction emulated successfully
3125 * -EFAULT = address out of range or access faulted (regs->dar
3126 * contains the faulting address)
3127 * -EACCES = misaligned access, instruction requires alignment
3128 * -EINVAL = unknown operation in *op
3129 */
emulate_loadstore(struct pt_regs * regs,struct instruction_op * op)3130 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3131 {
3132 int err, size, type;
3133 int i, rd, nb;
3134 unsigned int cr;
3135 unsigned long val;
3136 unsigned long ea;
3137 bool cross_endian;
3138
3139 err = 0;
3140 size = GETSIZE(op->type);
3141 type = GETTYPE(op->type);
3142 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3143 ea = truncate_if_32bit(regs->msr, op->ea);
3144
3145 switch (type) {
3146 case LARX:
3147 if (ea & (size - 1))
3148 return -EACCES; /* can't handle misaligned */
3149 if (!address_ok(regs, ea, size))
3150 return -EFAULT;
3151 err = 0;
3152 val = 0;
3153 switch (size) {
3154 #ifdef __powerpc64__
3155 case 1:
3156 __get_user_asmx(val, ea, err, "lbarx");
3157 break;
3158 case 2:
3159 __get_user_asmx(val, ea, err, "lharx");
3160 break;
3161 #endif
3162 case 4:
3163 __get_user_asmx(val, ea, err, "lwarx");
3164 break;
3165 #ifdef __powerpc64__
3166 case 8:
3167 __get_user_asmx(val, ea, err, "ldarx");
3168 break;
3169 case 16:
3170 err = do_lqarx(ea, ®s->gpr[op->reg]);
3171 break;
3172 #endif
3173 default:
3174 return -EINVAL;
3175 }
3176 if (err) {
3177 regs->dar = ea;
3178 break;
3179 }
3180 if (size < 16)
3181 regs->gpr[op->reg] = val;
3182 break;
3183
3184 case STCX:
3185 if (ea & (size - 1))
3186 return -EACCES; /* can't handle misaligned */
3187 if (!address_ok(regs, ea, size))
3188 return -EFAULT;
3189 err = 0;
3190 switch (size) {
3191 #ifdef __powerpc64__
3192 case 1:
3193 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3194 break;
3195 case 2:
3196 __put_user_asmx(op->val, ea, err, "sthcx.", cr);
3197 break;
3198 #endif
3199 case 4:
3200 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3201 break;
3202 #ifdef __powerpc64__
3203 case 8:
3204 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3205 break;
3206 case 16:
3207 err = do_stqcx(ea, regs->gpr[op->reg],
3208 regs->gpr[op->reg + 1], &cr);
3209 break;
3210 #endif
3211 default:
3212 return -EINVAL;
3213 }
3214 if (!err)
3215 regs->ccr = (regs->ccr & 0x0fffffff) |
3216 (cr & 0xe0000000) |
3217 ((regs->xer >> 3) & 0x10000000);
3218 else
3219 regs->dar = ea;
3220 break;
3221
3222 case LOAD:
3223 #ifdef __powerpc64__
3224 if (size == 16) {
3225 err = emulate_lq(regs, ea, op->reg, cross_endian);
3226 break;
3227 }
3228 #endif
3229 err = read_mem(®s->gpr[op->reg], ea, size, regs);
3230 if (!err) {
3231 if (op->type & SIGNEXT)
3232 do_signext(®s->gpr[op->reg], size);
3233 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3234 do_byterev(®s->gpr[op->reg], size);
3235 }
3236 break;
3237
3238 #ifdef CONFIG_PPC_FPU
3239 case LOAD_FP:
3240 /*
3241 * If the instruction is in userspace, we can emulate it even
3242 * if the VMX state is not live, because we have the state
3243 * stored in the thread_struct. If the instruction is in
3244 * the kernel, we must not touch the state in the thread_struct.
3245 */
3246 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3247 return 0;
3248 err = do_fp_load(op, ea, regs, cross_endian);
3249 break;
3250 #endif
3251 #ifdef CONFIG_ALTIVEC
3252 case LOAD_VMX:
3253 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3254 return 0;
3255 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3256 break;
3257 #endif
3258 #ifdef CONFIG_VSX
3259 case LOAD_VSX: {
3260 unsigned long msrbit = MSR_VSX;
3261
3262 /*
3263 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3264 * when the target of the instruction is a vector register.
3265 */
3266 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3267 msrbit = MSR_VEC;
3268 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3269 return 0;
3270 err = do_vsx_load(op, ea, regs, cross_endian);
3271 break;
3272 }
3273 #endif
3274 case LOAD_MULTI:
3275 if (!address_ok(regs, ea, size))
3276 return -EFAULT;
3277 rd = op->reg;
3278 for (i = 0; i < size; i += 4) {
3279 unsigned int v32 = 0;
3280
3281 nb = size - i;
3282 if (nb > 4)
3283 nb = 4;
3284 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3285 if (err)
3286 break;
3287 if (unlikely(cross_endian))
3288 v32 = byterev_4(v32);
3289 regs->gpr[rd] = v32;
3290 ea += 4;
3291 /* reg number wraps from 31 to 0 for lsw[ix] */
3292 rd = (rd + 1) & 0x1f;
3293 }
3294 break;
3295
3296 case STORE:
3297 #ifdef __powerpc64__
3298 if (size == 16) {
3299 err = emulate_stq(regs, ea, op->reg, cross_endian);
3300 break;
3301 }
3302 #endif
3303 if ((op->type & UPDATE) && size == sizeof(long) &&
3304 op->reg == 1 && op->update_reg == 1 &&
3305 !(regs->msr & MSR_PR) &&
3306 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3307 err = handle_stack_update(ea, regs);
3308 break;
3309 }
3310 if (unlikely(cross_endian))
3311 do_byterev(&op->val, size);
3312 err = write_mem(op->val, ea, size, regs);
3313 break;
3314
3315 #ifdef CONFIG_PPC_FPU
3316 case STORE_FP:
3317 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3318 return 0;
3319 err = do_fp_store(op, ea, regs, cross_endian);
3320 break;
3321 #endif
3322 #ifdef CONFIG_ALTIVEC
3323 case STORE_VMX:
3324 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3325 return 0;
3326 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3327 break;
3328 #endif
3329 #ifdef CONFIG_VSX
3330 case STORE_VSX: {
3331 unsigned long msrbit = MSR_VSX;
3332
3333 /*
3334 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3335 * when the target of the instruction is a vector register.
3336 */
3337 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3338 msrbit = MSR_VEC;
3339 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3340 return 0;
3341 err = do_vsx_store(op, ea, regs, cross_endian);
3342 break;
3343 }
3344 #endif
3345 case STORE_MULTI:
3346 if (!address_ok(regs, ea, size))
3347 return -EFAULT;
3348 rd = op->reg;
3349 for (i = 0; i < size; i += 4) {
3350 unsigned int v32 = regs->gpr[rd];
3351
3352 nb = size - i;
3353 if (nb > 4)
3354 nb = 4;
3355 if (unlikely(cross_endian))
3356 v32 = byterev_4(v32);
3357 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3358 if (err)
3359 break;
3360 ea += 4;
3361 /* reg number wraps from 31 to 0 for stsw[ix] */
3362 rd = (rd + 1) & 0x1f;
3363 }
3364 break;
3365
3366 default:
3367 return -EINVAL;
3368 }
3369
3370 if (err)
3371 return err;
3372
3373 if (op->type & UPDATE)
3374 regs->gpr[op->update_reg] = op->ea;
3375
3376 return 0;
3377 }
3378 NOKPROBE_SYMBOL(emulate_loadstore);
3379
3380 /*
3381 * Emulate instructions that cause a transfer of control,
3382 * loads and stores, and a few other instructions.
3383 * Returns 1 if the step was emulated, 0 if not,
3384 * or -1 if the instruction is one that should not be stepped,
3385 * such as an rfid, or a mtmsrd that would clear MSR_RI.
3386 */
emulate_step(struct pt_regs * regs,struct ppc_inst instr)3387 int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
3388 {
3389 struct instruction_op op;
3390 int r, err, type;
3391 unsigned long val;
3392 unsigned long ea;
3393
3394 r = analyse_instr(&op, regs, instr);
3395 if (r < 0)
3396 return r;
3397 if (r > 0) {
3398 emulate_update_regs(regs, &op);
3399 return 1;
3400 }
3401
3402 err = 0;
3403 type = GETTYPE(op.type);
3404
3405 if (OP_IS_LOAD_STORE(type)) {
3406 err = emulate_loadstore(regs, &op);
3407 if (err)
3408 return 0;
3409 goto instr_done;
3410 }
3411
3412 switch (type) {
3413 case CACHEOP:
3414 ea = truncate_if_32bit(regs->msr, op.ea);
3415 if (!address_ok(regs, ea, 8))
3416 return 0;
3417 switch (op.type & CACHEOP_MASK) {
3418 case DCBST:
3419 __cacheop_user_asmx(ea, err, "dcbst");
3420 break;
3421 case DCBF:
3422 __cacheop_user_asmx(ea, err, "dcbf");
3423 break;
3424 case DCBTST:
3425 if (op.reg == 0)
3426 prefetchw((void *) ea);
3427 break;
3428 case DCBT:
3429 if (op.reg == 0)
3430 prefetch((void *) ea);
3431 break;
3432 case ICBI:
3433 __cacheop_user_asmx(ea, err, "icbi");
3434 break;
3435 case DCBZ:
3436 err = emulate_dcbz(ea, regs);
3437 break;
3438 }
3439 if (err) {
3440 regs->dar = ea;
3441 return 0;
3442 }
3443 goto instr_done;
3444
3445 case MFMSR:
3446 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3447 goto instr_done;
3448
3449 case MTMSR:
3450 val = regs->gpr[op.reg];
3451 if ((val & MSR_RI) == 0)
3452 /* can't step mtmsr[d] that would clear MSR_RI */
3453 return -1;
3454 /* here op.val is the mask of bits to change */
3455 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3456 goto instr_done;
3457
3458 #ifdef CONFIG_PPC64
3459 case SYSCALL: /* sc */
3460 /*
3461 * N.B. this uses knowledge about how the syscall
3462 * entry code works. If that is changed, this will
3463 * need to be changed also.
3464 */
3465 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3466 cpu_has_feature(CPU_FTR_REAL_LE) &&
3467 regs->gpr[0] == 0x1ebe) {
3468 regs->msr ^= MSR_LE;
3469 goto instr_done;
3470 }
3471 regs->gpr[9] = regs->gpr[13];
3472 regs->gpr[10] = MSR_KERNEL;
3473 regs->gpr[11] = regs->nip + 4;
3474 regs->gpr[12] = regs->msr & MSR_MASK;
3475 regs->gpr[13] = (unsigned long) get_paca();
3476 regs->nip = (unsigned long) &system_call_common;
3477 regs->msr = MSR_KERNEL;
3478 return 1;
3479
3480 #ifdef CONFIG_PPC_BOOK3S_64
3481 case SYSCALL_VECTORED_0: /* scv 0 */
3482 regs->gpr[9] = regs->gpr[13];
3483 regs->gpr[10] = MSR_KERNEL;
3484 regs->gpr[11] = regs->nip + 4;
3485 regs->gpr[12] = regs->msr & MSR_MASK;
3486 regs->gpr[13] = (unsigned long) get_paca();
3487 regs->nip = (unsigned long) &system_call_vectored_emulate;
3488 regs->msr = MSR_KERNEL;
3489 return 1;
3490 #endif
3491
3492 case RFI:
3493 return -1;
3494 #endif
3495 }
3496 return 0;
3497
3498 instr_done:
3499 regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
3500 return 1;
3501 }
3502 NOKPROBE_SYMBOL(emulate_step);
3503