1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * arch/powerpc/platforms/83xx/mpc832x_rdb.c
4 *
5 * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
6 *
7 * Description:
8 * MPC832x RDB board specific routines.
9 * This file is based on mpc832x_mds.c and mpc8313_rdb.c
10 * Author: Michael Barkowski <michael.barkowski@freescale.com>
11 */
12
13 #include <linux/pci.h>
14 #include <linux/interrupt.h>
15 #include <linux/spi/spi.h>
16 #include <linux/spi/mmc_spi.h>
17 #include <linux/mmc/host.h>
18 #include <linux/of_platform.h>
19 #include <linux/fsl_devices.h>
20
21 #include <asm/time.h>
22 #include <asm/ipic.h>
23 #include <asm/udbg.h>
24 #include <soc/fsl/qe/qe.h>
25 #include <sysdev/fsl_soc.h>
26 #include <sysdev/fsl_pci.h>
27
28 #include "mpc83xx.h"
29
30 #undef DEBUG
31 #ifdef DEBUG
32 #define DBG(fmt...) udbg_printf(fmt)
33 #else
34 #define DBG(fmt...)
35 #endif
36
37 #ifdef CONFIG_QUICC_ENGINE
of_fsl_spi_probe(char * type,char * compatible,u32 sysclk,struct spi_board_info * board_infos,unsigned int num_board_infos,void (* cs_control)(struct spi_device * dev,bool on))38 static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
39 struct spi_board_info *board_infos,
40 unsigned int num_board_infos,
41 void (*cs_control)(struct spi_device *dev,
42 bool on))
43 {
44 struct device_node *np;
45 unsigned int i = 0;
46
47 for_each_compatible_node(np, type, compatible) {
48 int ret;
49 unsigned int j;
50 const void *prop;
51 struct resource res[2];
52 struct platform_device *pdev;
53 struct fsl_spi_platform_data pdata = {
54 .cs_control = cs_control,
55 };
56
57 memset(res, 0, sizeof(res));
58
59 pdata.sysclk = sysclk;
60
61 prop = of_get_property(np, "reg", NULL);
62 if (!prop)
63 goto err;
64 pdata.bus_num = *(u32 *)prop;
65
66 prop = of_get_property(np, "cell-index", NULL);
67 if (prop)
68 i = *(u32 *)prop;
69
70 prop = of_get_property(np, "mode", NULL);
71 if (prop && !strcmp(prop, "cpu-qe"))
72 pdata.flags = SPI_QE_CPU_MODE;
73
74 for (j = 0; j < num_board_infos; j++) {
75 if (board_infos[j].bus_num == pdata.bus_num)
76 pdata.max_chipselect++;
77 }
78
79 if (!pdata.max_chipselect)
80 continue;
81
82 ret = of_address_to_resource(np, 0, &res[0]);
83 if (ret)
84 goto err;
85
86 ret = of_irq_to_resource(np, 0, &res[1]);
87 if (ret <= 0)
88 goto err;
89
90 pdev = platform_device_alloc("mpc83xx_spi", i);
91 if (!pdev)
92 goto err;
93
94 ret = platform_device_add_data(pdev, &pdata, sizeof(pdata));
95 if (ret)
96 goto unreg;
97
98 ret = platform_device_add_resources(pdev, res,
99 ARRAY_SIZE(res));
100 if (ret)
101 goto unreg;
102
103 ret = platform_device_add(pdev);
104 if (ret)
105 goto unreg;
106
107 goto next;
108 unreg:
109 platform_device_put(pdev);
110 err:
111 pr_err("%pOF: registration failed\n", np);
112 next:
113 i++;
114 }
115
116 return i;
117 }
118
fsl_spi_init(struct spi_board_info * board_infos,unsigned int num_board_infos,void (* cs_control)(struct spi_device * spi,bool on))119 static int __init fsl_spi_init(struct spi_board_info *board_infos,
120 unsigned int num_board_infos,
121 void (*cs_control)(struct spi_device *spi,
122 bool on))
123 {
124 u32 sysclk = -1;
125 int ret;
126
127 /* SPI controller is either clocked from QE or SoC clock */
128 sysclk = get_brgfreq();
129 if (sysclk == -1) {
130 sysclk = fsl_get_sys_freq();
131 if (sysclk == -1)
132 return -ENODEV;
133 }
134
135 ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
136 num_board_infos, cs_control);
137 if (!ret)
138 of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
139 num_board_infos, cs_control);
140
141 return spi_register_board_info(board_infos, num_board_infos);
142 }
143
mpc83xx_spi_cs_control(struct spi_device * spi,bool on)144 static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on)
145 {
146 pr_debug("%s %d %d\n", __func__, spi->chip_select, on);
147 par_io_data_set(3, 13, on);
148 }
149
150 static struct mmc_spi_platform_data mpc832x_mmc_pdata = {
151 .ocr_mask = MMC_VDD_33_34,
152 };
153
154 static struct spi_board_info mpc832x_spi_boardinfo = {
155 .bus_num = 0x4c0,
156 .chip_select = 0,
157 .max_speed_hz = 50000000,
158 .modalias = "mmc_spi",
159 .platform_data = &mpc832x_mmc_pdata,
160 };
161
mpc832x_spi_init(void)162 static int __init mpc832x_spi_init(void)
163 {
164 par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
165 par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
166 par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */
167 par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */
168
169 par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */
170 par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
171 par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
172
173 /*
174 * Don't bother with legacy stuff when device tree contains
175 * mmc-spi-slot node.
176 */
177 if (of_find_compatible_node(NULL, NULL, "mmc-spi-slot"))
178 return 0;
179 return fsl_spi_init(&mpc832x_spi_boardinfo, 1, mpc83xx_spi_cs_control);
180 }
181 machine_device_initcall(mpc832x_rdb, mpc832x_spi_init);
182 #endif /* CONFIG_QUICC_ENGINE */
183
184 /* ************************************************************************
185 *
186 * Setup the architecture
187 *
188 */
mpc832x_rdb_setup_arch(void)189 static void __init mpc832x_rdb_setup_arch(void)
190 {
191 #if defined(CONFIG_QUICC_ENGINE)
192 struct device_node *np;
193 #endif
194
195 mpc83xx_setup_arch();
196
197 #ifdef CONFIG_QUICC_ENGINE
198 if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
199 par_io_init(np);
200 of_node_put(np);
201
202 for_each_node_by_name(np, "ucc")
203 par_io_of_config(np);
204 }
205 #endif /* CONFIG_QUICC_ENGINE */
206 }
207
208 machine_device_initcall(mpc832x_rdb, mpc83xx_declare_of_platform_devices);
209
210 /*
211 * Called very early, MMU is off, device-tree isn't unflattened
212 */
mpc832x_rdb_probe(void)213 static int __init mpc832x_rdb_probe(void)
214 {
215 return of_machine_is_compatible("MPC832xRDB");
216 }
217
define_machine(mpc832x_rdb)218 define_machine(mpc832x_rdb) {
219 .name = "MPC832x RDB",
220 .probe = mpc832x_rdb_probe,
221 .setup_arch = mpc832x_rdb_setup_arch,
222 .init_IRQ = mpc83xx_ipic_init_IRQ,
223 .get_irq = ipic_get_irq,
224 .restart = mpc83xx_restart,
225 .time_init = mpc83xx_time_init,
226 .calibrate_decr = generic_calibrate_decr,
227 .progress = udbg_progress,
228 };
229