1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
35 #include "ahci.h"
36
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
39
40 enum {
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
47 };
48
49 enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
53 board_ahci_mobile,
54 board_ahci_nomsi,
55 board_ahci_noncq,
56 board_ahci_nosntf,
57 board_ahci_yes_fbs,
58
59 /* board IDs for specific chipsets in alphabetical order */
60 board_ahci_al,
61 board_ahci_avn,
62 board_ahci_mcp65,
63 board_ahci_mcp77,
64 board_ahci_mcp89,
65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81 };
82
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void ahci_remove_one(struct pci_dev *dev);
85 static void ahci_shutdown_one(struct pci_dev *dev);
86 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
92 static bool is_mcp89_apple(struct pci_dev *pdev);
93 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
95 #ifdef CONFIG_PM
96 static int ahci_pci_device_runtime_suspend(struct device *dev);
97 static int ahci_pci_device_runtime_resume(struct device *dev);
98 #ifdef CONFIG_PM_SLEEP
99 static int ahci_pci_device_suspend(struct device *dev);
100 static int ahci_pci_device_resume(struct device *dev);
101 #endif
102 #endif /* CONFIG_PM */
103
104 static struct scsi_host_template ahci_sht = {
105 AHCI_SHT("ahci"),
106 };
107
108 static struct ata_port_operations ahci_vt8251_ops = {
109 .inherits = &ahci_ops,
110 .hardreset = ahci_vt8251_hardreset,
111 };
112
113 static struct ata_port_operations ahci_p5wdh_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_p5wdh_hardreset,
116 };
117
118 static struct ata_port_operations ahci_avn_ops = {
119 .inherits = &ahci_ops,
120 .hardreset = ahci_avn_hardreset,
121 };
122
123 static const struct ata_port_info ahci_port_info[] = {
124 /* by features */
125 [board_ahci] = {
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_ign_iferr] = {
132 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
137 },
138 [board_ahci_mobile] = {
139 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 [board_ahci_nomsi] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
152 [board_ahci_noncq] = {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
159 [board_ahci_nosntf] = {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_yes_fbs] = {
167 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_ops,
172 },
173 /* by chipsets */
174 [board_ahci_al] = {
175 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
176 .flags = AHCI_FLAG_COMMON,
177 .pio_mask = ATA_PIO4,
178 .udma_mask = ATA_UDMA6,
179 .port_ops = &ahci_ops,
180 },
181 [board_ahci_avn] = {
182 .flags = AHCI_FLAG_COMMON,
183 .pio_mask = ATA_PIO4,
184 .udma_mask = ATA_UDMA6,
185 .port_ops = &ahci_avn_ops,
186 },
187 [board_ahci_mcp65] = {
188 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
189 AHCI_HFLAG_YES_NCQ),
190 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_ops,
194 },
195 [board_ahci_mcp77] = {
196 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_ops,
201 },
202 [board_ahci_mcp89] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_ops,
208 },
209 [board_ahci_mv] = {
210 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
211 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
212 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_ops,
216 },
217 [board_ahci_sb600] = {
218 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
219 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
220 AHCI_HFLAG_32BIT_ONLY),
221 .flags = AHCI_FLAG_COMMON,
222 .pio_mask = ATA_PIO4,
223 .udma_mask = ATA_UDMA6,
224 .port_ops = &ahci_pmp_retry_srst_ops,
225 },
226 [board_ahci_sb700] = { /* for SB700 and SB800 */
227 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_pmp_retry_srst_ops,
232 },
233 [board_ahci_vt8251] = {
234 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
235 .flags = AHCI_FLAG_COMMON,
236 .pio_mask = ATA_PIO4,
237 .udma_mask = ATA_UDMA6,
238 .port_ops = &ahci_vt8251_ops,
239 },
240 [board_ahci_pcs7] = {
241 .flags = AHCI_FLAG_COMMON,
242 .pio_mask = ATA_PIO4,
243 .udma_mask = ATA_UDMA6,
244 .port_ops = &ahci_ops,
245 },
246 };
247
248 static const struct pci_device_id ahci_pci_tbl[] = {
249 /* Intel */
250 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
251 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
252 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
253 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
254 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
255 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
256 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
257 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
259 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
260 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
261 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
262 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
263 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
264 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
265 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
266 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
270 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
271 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
274 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
275 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
276 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
277 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
278 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
279 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
280 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
281 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
282 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
283 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
284 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
285 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
286 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
287 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
288 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
289 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
290 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
312 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
313 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
314 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
315 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
316 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
317 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
318 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
319 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
320 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
321 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
322 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
323 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
324 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
325 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
326 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
327 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
328 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
329 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
330 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
331 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
332 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
333 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
334 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
335 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
336 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
337 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
339 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
343 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
344 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
345 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
348 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
353 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
354 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
356 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
362 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
363 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
364 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
365 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
366 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
367 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
368 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
369 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
372 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
373 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
375 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
376 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
377 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
378 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
379 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
380 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
381 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
382 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
383 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
384 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
385 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
386 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
387 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
388 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
389 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
390 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
391 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
392 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
393 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
394 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
395 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
396 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
397 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
398 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
399 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
400 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
401 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
402 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
403 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
405 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
406 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
407 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
410 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
411 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
413 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
415 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
416 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
417 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
418 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
419 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
420
421 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
422 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
423 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
424 /* JMicron 362B and 362C have an AHCI function with IDE class code */
425 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
426 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
427 /* May need to update quirk_jmicron_async_suspend() for additions */
428
429 /* ATI */
430 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
431 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
436 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
437
438 /* Amazon's Annapurna Labs support */
439 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
440 .class = PCI_CLASS_STORAGE_SATA_AHCI,
441 .class_mask = 0xffffff,
442 board_ahci_al },
443 /* AMD */
444 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
445 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
446 { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
447 /* AMD is using RAID class only for ahci controllers */
448 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
449 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
450
451 /* VIA */
452 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
453 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
454
455 /* NVIDIA */
456 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
458 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
459 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
460 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
462 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
463 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
464 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
475 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
487 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
491 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
492 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
499 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
500 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
503 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
504 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
511 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
512 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
515 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
516 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
523 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
524 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
527 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
528 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
530 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
532 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
533 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
534 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
535 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
536 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
537 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
538 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
539 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
540
541 /* SiS */
542 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
543 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
544 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
545
546 /* ST Microelectronics */
547 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
548
549 /* Marvell */
550 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
551 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
552 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
553 .class = PCI_CLASS_STORAGE_SATA_AHCI,
554 .class_mask = 0xffffff,
555 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
556 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
557 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
558 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
559 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
560 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
562 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
564 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
566 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
568 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
570 .driver_data = board_ahci_yes_fbs },
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
572 .driver_data = board_ahci_yes_fbs },
573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
574 .driver_data = board_ahci_yes_fbs },
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
576 .driver_data = board_ahci_yes_fbs },
577 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
578 .driver_data = board_ahci_yes_fbs },
579 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
580 .driver_data = board_ahci_yes_fbs },
581
582 /* Promise */
583 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
584 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
585
586 /* Asmedia */
587 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
588 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
589 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
590 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
591 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
592 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
593
594 /*
595 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
596 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
597 */
598 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
599 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
600
601 /* Enmotus */
602 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
603
604 /* Loongson */
605 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
606
607 /* Generic, PCI class code for AHCI */
608 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
609 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
610
611 { } /* terminate list */
612 };
613
614 static const struct dev_pm_ops ahci_pci_pm_ops = {
615 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
616 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
617 ahci_pci_device_runtime_resume, NULL)
618 };
619
620 static struct pci_driver ahci_pci_driver = {
621 .name = DRV_NAME,
622 .id_table = ahci_pci_tbl,
623 .probe = ahci_init_one,
624 .remove = ahci_remove_one,
625 .shutdown = ahci_shutdown_one,
626 .driver = {
627 .pm = &ahci_pci_pm_ops,
628 },
629 };
630
631 #if IS_ENABLED(CONFIG_PATA_MARVELL)
632 static int marvell_enable;
633 #else
634 static int marvell_enable = 1;
635 #endif
636 module_param(marvell_enable, int, 0644);
637 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
638
639 static int mobile_lpm_policy = -1;
640 module_param(mobile_lpm_policy, int, 0644);
641 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
642
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)643 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
644 struct ahci_host_priv *hpriv)
645 {
646 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
647 dev_info(&pdev->dev, "JMB361 has only one port\n");
648 hpriv->force_port_map = 1;
649 }
650
651 /*
652 * Temporary Marvell 6145 hack: PATA port presence
653 * is asserted through the standard AHCI port
654 * presence register, as bit 4 (counting from 0)
655 */
656 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
657 if (pdev->device == 0x6121)
658 hpriv->mask_port_map = 0x3;
659 else
660 hpriv->mask_port_map = 0xf;
661 dev_info(&pdev->dev,
662 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
663 }
664
665 ahci_save_initial_config(&pdev->dev, hpriv);
666 }
667
ahci_pci_reset_controller(struct ata_host * host)668 static int ahci_pci_reset_controller(struct ata_host *host)
669 {
670 struct pci_dev *pdev = to_pci_dev(host->dev);
671 struct ahci_host_priv *hpriv = host->private_data;
672 int rc;
673
674 rc = ahci_reset_controller(host);
675 if (rc)
676 return rc;
677
678 /*
679 * If platform firmware failed to enable ports, try to enable
680 * them here.
681 */
682 ahci_intel_pcs_quirk(pdev, hpriv);
683
684 return 0;
685 }
686
ahci_pci_init_controller(struct ata_host * host)687 static void ahci_pci_init_controller(struct ata_host *host)
688 {
689 struct ahci_host_priv *hpriv = host->private_data;
690 struct pci_dev *pdev = to_pci_dev(host->dev);
691 void __iomem *port_mmio;
692 u32 tmp;
693 int mv;
694
695 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
696 if (pdev->device == 0x6121)
697 mv = 2;
698 else
699 mv = 4;
700 port_mmio = __ahci_port_base(host, mv);
701
702 writel(0, port_mmio + PORT_IRQ_MASK);
703
704 /* clear port IRQ */
705 tmp = readl(port_mmio + PORT_IRQ_STAT);
706 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
707 if (tmp)
708 writel(tmp, port_mmio + PORT_IRQ_STAT);
709 }
710
711 ahci_init_controller(host);
712 }
713
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)714 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
715 unsigned long deadline)
716 {
717 struct ata_port *ap = link->ap;
718 struct ahci_host_priv *hpriv = ap->host->private_data;
719 bool online;
720 int rc;
721
722 DPRINTK("ENTER\n");
723
724 hpriv->stop_engine(ap);
725
726 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
727 deadline, &online, NULL);
728
729 hpriv->start_engine(ap);
730
731 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
732
733 /* vt8251 doesn't clear BSY on signature FIS reception,
734 * request follow-up softreset.
735 */
736 return online ? -EAGAIN : rc;
737 }
738
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)739 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
740 unsigned long deadline)
741 {
742 struct ata_port *ap = link->ap;
743 struct ahci_port_priv *pp = ap->private_data;
744 struct ahci_host_priv *hpriv = ap->host->private_data;
745 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
746 struct ata_taskfile tf;
747 bool online;
748 int rc;
749
750 hpriv->stop_engine(ap);
751
752 /* clear D2H reception area to properly wait for D2H FIS */
753 ata_tf_init(link->device, &tf);
754 tf.command = ATA_BUSY;
755 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
756
757 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
758 deadline, &online, NULL);
759
760 hpriv->start_engine(ap);
761
762 /* The pseudo configuration device on SIMG4726 attached to
763 * ASUS P5W-DH Deluxe doesn't send signature FIS after
764 * hardreset if no device is attached to the first downstream
765 * port && the pseudo device locks up on SRST w/ PMP==0. To
766 * work around this, wait for !BSY only briefly. If BSY isn't
767 * cleared, perform CLO and proceed to IDENTIFY (achieved by
768 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
769 *
770 * Wait for two seconds. Devices attached to downstream port
771 * which can't process the following IDENTIFY after this will
772 * have to be reset again. For most cases, this should
773 * suffice while making probing snappish enough.
774 */
775 if (online) {
776 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
777 ahci_check_ready);
778 if (rc)
779 ahci_kick_engine(ap);
780 }
781 return rc;
782 }
783
784 /*
785 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
786 *
787 * It has been observed with some SSDs that the timing of events in the
788 * link synchronization phase can leave the port in a state that can not
789 * be recovered by a SATA-hard-reset alone. The failing signature is
790 * SStatus.DET stuck at 1 ("Device presence detected but Phy
791 * communication not established"). It was found that unloading and
792 * reloading the driver when this problem occurs allows the drive
793 * connection to be recovered (DET advanced to 0x3). The critical
794 * component of reloading the driver is that the port state machines are
795 * reset by bouncing "port enable" in the AHCI PCS configuration
796 * register. So, reproduce that effect by bouncing a port whenever we
797 * see DET==1 after a reset.
798 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)799 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
800 unsigned long deadline)
801 {
802 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
803 struct ata_port *ap = link->ap;
804 struct ahci_port_priv *pp = ap->private_data;
805 struct ahci_host_priv *hpriv = ap->host->private_data;
806 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
807 unsigned long tmo = deadline - jiffies;
808 struct ata_taskfile tf;
809 bool online;
810 int rc, i;
811
812 DPRINTK("ENTER\n");
813
814 hpriv->stop_engine(ap);
815
816 for (i = 0; i < 2; i++) {
817 u16 val;
818 u32 sstatus;
819 int port = ap->port_no;
820 struct ata_host *host = ap->host;
821 struct pci_dev *pdev = to_pci_dev(host->dev);
822
823 /* clear D2H reception area to properly wait for D2H FIS */
824 ata_tf_init(link->device, &tf);
825 tf.command = ATA_BUSY;
826 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
827
828 rc = sata_link_hardreset(link, timing, deadline, &online,
829 ahci_check_ready);
830
831 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
832 (sstatus & 0xf) != 1)
833 break;
834
835 ata_link_info(link, "avn bounce port%d\n", port);
836
837 pci_read_config_word(pdev, 0x92, &val);
838 val &= ~(1 << port);
839 pci_write_config_word(pdev, 0x92, val);
840 ata_msleep(ap, 1000);
841 val |= 1 << port;
842 pci_write_config_word(pdev, 0x92, val);
843 deadline += tmo;
844 }
845
846 hpriv->start_engine(ap);
847
848 if (online)
849 *class = ahci_dev_classify(ap);
850
851 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
852 return rc;
853 }
854
855
856 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)857 static void ahci_pci_disable_interrupts(struct ata_host *host)
858 {
859 struct ahci_host_priv *hpriv = host->private_data;
860 void __iomem *mmio = hpriv->mmio;
861 u32 ctl;
862
863 /* AHCI spec rev1.1 section 8.3.3:
864 * Software must disable interrupts prior to requesting a
865 * transition of the HBA to D3 state.
866 */
867 ctl = readl(mmio + HOST_CTL);
868 ctl &= ~HOST_IRQ_EN;
869 writel(ctl, mmio + HOST_CTL);
870 readl(mmio + HOST_CTL); /* flush */
871 }
872
ahci_pci_device_runtime_suspend(struct device * dev)873 static int ahci_pci_device_runtime_suspend(struct device *dev)
874 {
875 struct pci_dev *pdev = to_pci_dev(dev);
876 struct ata_host *host = pci_get_drvdata(pdev);
877
878 ahci_pci_disable_interrupts(host);
879 return 0;
880 }
881
ahci_pci_device_runtime_resume(struct device * dev)882 static int ahci_pci_device_runtime_resume(struct device *dev)
883 {
884 struct pci_dev *pdev = to_pci_dev(dev);
885 struct ata_host *host = pci_get_drvdata(pdev);
886 int rc;
887
888 rc = ahci_pci_reset_controller(host);
889 if (rc)
890 return rc;
891 ahci_pci_init_controller(host);
892 return 0;
893 }
894
895 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)896 static int ahci_pci_device_suspend(struct device *dev)
897 {
898 struct pci_dev *pdev = to_pci_dev(dev);
899 struct ata_host *host = pci_get_drvdata(pdev);
900 struct ahci_host_priv *hpriv = host->private_data;
901
902 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
903 dev_err(&pdev->dev,
904 "BIOS update required for suspend/resume\n");
905 return -EIO;
906 }
907
908 ahci_pci_disable_interrupts(host);
909 return ata_host_suspend(host, PMSG_SUSPEND);
910 }
911
ahci_pci_device_resume(struct device * dev)912 static int ahci_pci_device_resume(struct device *dev)
913 {
914 struct pci_dev *pdev = to_pci_dev(dev);
915 struct ata_host *host = pci_get_drvdata(pdev);
916 int rc;
917
918 /* Apple BIOS helpfully mangles the registers on resume */
919 if (is_mcp89_apple(pdev))
920 ahci_mcp89_apple_enable(pdev);
921
922 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
923 rc = ahci_pci_reset_controller(host);
924 if (rc)
925 return rc;
926
927 ahci_pci_init_controller(host);
928 }
929
930 ata_host_resume(host);
931
932 return 0;
933 }
934 #endif
935
936 #endif /* CONFIG_PM */
937
ahci_configure_dma_masks(struct pci_dev * pdev,int using_dac)938 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
939 {
940 const int dma_bits = using_dac ? 64 : 32;
941 int rc;
942
943 /*
944 * If the device fixup already set the dma_mask to some non-standard
945 * value, don't extend it here. This happens on STA2X11, for example.
946 *
947 * XXX: manipulating the DMA mask from platform code is completely
948 * bogus, platform code should use dev->bus_dma_limit instead..
949 */
950 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
951 return 0;
952
953 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
954 if (rc)
955 dev_err(&pdev->dev, "DMA enable failed\n");
956 return rc;
957 }
958
ahci_pci_print_info(struct ata_host * host)959 static void ahci_pci_print_info(struct ata_host *host)
960 {
961 struct pci_dev *pdev = to_pci_dev(host->dev);
962 u16 cc;
963 const char *scc_s;
964
965 pci_read_config_word(pdev, 0x0a, &cc);
966 if (cc == PCI_CLASS_STORAGE_IDE)
967 scc_s = "IDE";
968 else if (cc == PCI_CLASS_STORAGE_SATA)
969 scc_s = "SATA";
970 else if (cc == PCI_CLASS_STORAGE_RAID)
971 scc_s = "RAID";
972 else
973 scc_s = "unknown";
974
975 ahci_print_info(host, scc_s);
976 }
977
978 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
979 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
980 * support PMP and the 4726 either directly exports the device
981 * attached to the first downstream port or acts as a hardware storage
982 * controller and emulate a single ATA device (can be RAID 0/1 or some
983 * other configuration).
984 *
985 * When there's no device attached to the first downstream port of the
986 * 4726, "Config Disk" appears, which is a pseudo ATA device to
987 * configure the 4726. However, ATA emulation of the device is very
988 * lame. It doesn't send signature D2H Reg FIS after the initial
989 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
990 *
991 * The following function works around the problem by always using
992 * hardreset on the port and not depending on receiving signature FIS
993 * afterward. If signature FIS isn't received soon, ATA class is
994 * assumed without follow-up softreset.
995 */
ahci_p5wdh_workaround(struct ata_host * host)996 static void ahci_p5wdh_workaround(struct ata_host *host)
997 {
998 static const struct dmi_system_id sysids[] = {
999 {
1000 .ident = "P5W DH Deluxe",
1001 .matches = {
1002 DMI_MATCH(DMI_SYS_VENDOR,
1003 "ASUSTEK COMPUTER INC"),
1004 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1005 },
1006 },
1007 { }
1008 };
1009 struct pci_dev *pdev = to_pci_dev(host->dev);
1010
1011 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1012 dmi_check_system(sysids)) {
1013 struct ata_port *ap = host->ports[1];
1014
1015 dev_info(&pdev->dev,
1016 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1017
1018 ap->ops = &ahci_p5wdh_ops;
1019 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1020 }
1021 }
1022
1023 /*
1024 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1025 * booting in BIOS compatibility mode. We restore the registers but not ID.
1026 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1027 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1028 {
1029 u32 val;
1030
1031 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1032
1033 pci_read_config_dword(pdev, 0xf8, &val);
1034 val |= 1 << 0x1b;
1035 /* the following changes the device ID, but appears not to affect function */
1036 /* val = (val & ~0xf0000000) | 0x80000000; */
1037 pci_write_config_dword(pdev, 0xf8, val);
1038
1039 pci_read_config_dword(pdev, 0x54c, &val);
1040 val |= 1 << 0xc;
1041 pci_write_config_dword(pdev, 0x54c, val);
1042
1043 pci_read_config_dword(pdev, 0x4a4, &val);
1044 val &= 0xff;
1045 val |= 0x01060100;
1046 pci_write_config_dword(pdev, 0x4a4, val);
1047
1048 pci_read_config_dword(pdev, 0x54c, &val);
1049 val &= ~(1 << 0xc);
1050 pci_write_config_dword(pdev, 0x54c, val);
1051
1052 pci_read_config_dword(pdev, 0xf8, &val);
1053 val &= ~(1 << 0x1b);
1054 pci_write_config_dword(pdev, 0xf8, val);
1055 }
1056
is_mcp89_apple(struct pci_dev * pdev)1057 static bool is_mcp89_apple(struct pci_dev *pdev)
1058 {
1059 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1060 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1061 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1062 pdev->subsystem_device == 0xcb89;
1063 }
1064
1065 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1066 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1067 {
1068 static const struct dmi_system_id sysids[] = {
1069 /*
1070 * The oldest version known to be broken is 0901 and
1071 * working is 1501 which was released on 2007-10-26.
1072 * Enable 64bit DMA on 1501 and anything newer.
1073 *
1074 * Please read bko#9412 for more info.
1075 */
1076 {
1077 .ident = "ASUS M2A-VM",
1078 .matches = {
1079 DMI_MATCH(DMI_BOARD_VENDOR,
1080 "ASUSTeK Computer INC."),
1081 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1082 },
1083 .driver_data = "20071026", /* yyyymmdd */
1084 },
1085 /*
1086 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1087 * support 64bit DMA.
1088 *
1089 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1090 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1091 * This spelling mistake was fixed in BIOS version 1.5, so
1092 * 1.5 and later have the Manufacturer as
1093 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1094 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1095 *
1096 * BIOS versions earlier than 1.9 had a Board Product Name
1097 * DMI field of "MS-7376". This was changed to be
1098 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1099 * match on DMI_BOARD_NAME of "MS-7376".
1100 */
1101 {
1102 .ident = "MSI K9A2 Platinum",
1103 .matches = {
1104 DMI_MATCH(DMI_BOARD_VENDOR,
1105 "MICRO-STAR INTER"),
1106 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1107 },
1108 },
1109 /*
1110 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1111 * 64bit DMA.
1112 *
1113 * This board also had the typo mentioned above in the
1114 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1115 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1116 */
1117 {
1118 .ident = "MSI K9AGM2",
1119 .matches = {
1120 DMI_MATCH(DMI_BOARD_VENDOR,
1121 "MICRO-STAR INTER"),
1122 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1123 },
1124 },
1125 /*
1126 * All BIOS versions for the Asus M3A support 64bit DMA.
1127 * (all release versions from 0301 to 1206 were tested)
1128 */
1129 {
1130 .ident = "ASUS M3A",
1131 .matches = {
1132 DMI_MATCH(DMI_BOARD_VENDOR,
1133 "ASUSTeK Computer INC."),
1134 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1135 },
1136 },
1137 { }
1138 };
1139 const struct dmi_system_id *match;
1140 int year, month, date;
1141 char buf[9];
1142
1143 match = dmi_first_match(sysids);
1144 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1145 !match)
1146 return false;
1147
1148 if (!match->driver_data)
1149 goto enable_64bit;
1150
1151 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1152 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1153
1154 if (strcmp(buf, match->driver_data) >= 0)
1155 goto enable_64bit;
1156 else {
1157 dev_warn(&pdev->dev,
1158 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1159 match->ident);
1160 return false;
1161 }
1162
1163 enable_64bit:
1164 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1165 return true;
1166 }
1167
ahci_broken_system_poweroff(struct pci_dev * pdev)1168 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1169 {
1170 static const struct dmi_system_id broken_systems[] = {
1171 {
1172 .ident = "HP Compaq nx6310",
1173 .matches = {
1174 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1175 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1176 },
1177 /* PCI slot number of the controller */
1178 .driver_data = (void *)0x1FUL,
1179 },
1180 {
1181 .ident = "HP Compaq 6720s",
1182 .matches = {
1183 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1184 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1185 },
1186 /* PCI slot number of the controller */
1187 .driver_data = (void *)0x1FUL,
1188 },
1189
1190 { } /* terminate list */
1191 };
1192 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1193
1194 if (dmi) {
1195 unsigned long slot = (unsigned long)dmi->driver_data;
1196 /* apply the quirk only to on-board controllers */
1197 return slot == PCI_SLOT(pdev->devfn);
1198 }
1199
1200 return false;
1201 }
1202
ahci_broken_suspend(struct pci_dev * pdev)1203 static bool ahci_broken_suspend(struct pci_dev *pdev)
1204 {
1205 static const struct dmi_system_id sysids[] = {
1206 /*
1207 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1208 * to the harddisk doesn't become online after
1209 * resuming from STR. Warn and fail suspend.
1210 *
1211 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1212 *
1213 * Use dates instead of versions to match as HP is
1214 * apparently recycling both product and version
1215 * strings.
1216 *
1217 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1218 */
1219 {
1220 .ident = "dv4",
1221 .matches = {
1222 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1223 DMI_MATCH(DMI_PRODUCT_NAME,
1224 "HP Pavilion dv4 Notebook PC"),
1225 },
1226 .driver_data = "20090105", /* F.30 */
1227 },
1228 {
1229 .ident = "dv5",
1230 .matches = {
1231 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1232 DMI_MATCH(DMI_PRODUCT_NAME,
1233 "HP Pavilion dv5 Notebook PC"),
1234 },
1235 .driver_data = "20090506", /* F.16 */
1236 },
1237 {
1238 .ident = "dv6",
1239 .matches = {
1240 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1241 DMI_MATCH(DMI_PRODUCT_NAME,
1242 "HP Pavilion dv6 Notebook PC"),
1243 },
1244 .driver_data = "20090423", /* F.21 */
1245 },
1246 {
1247 .ident = "HDX18",
1248 .matches = {
1249 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1250 DMI_MATCH(DMI_PRODUCT_NAME,
1251 "HP HDX18 Notebook PC"),
1252 },
1253 .driver_data = "20090430", /* F.23 */
1254 },
1255 /*
1256 * Acer eMachines G725 has the same problem. BIOS
1257 * V1.03 is known to be broken. V3.04 is known to
1258 * work. Between, there are V1.06, V2.06 and V3.03
1259 * that we don't have much idea about. For now,
1260 * blacklist anything older than V3.04.
1261 *
1262 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1263 */
1264 {
1265 .ident = "G725",
1266 .matches = {
1267 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1268 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1269 },
1270 .driver_data = "20091216", /* V3.04 */
1271 },
1272 { } /* terminate list */
1273 };
1274 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1275 int year, month, date;
1276 char buf[9];
1277
1278 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1279 return false;
1280
1281 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1282 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1283
1284 return strcmp(buf, dmi->driver_data) < 0;
1285 }
1286
ahci_broken_lpm(struct pci_dev * pdev)1287 static bool ahci_broken_lpm(struct pci_dev *pdev)
1288 {
1289 static const struct dmi_system_id sysids[] = {
1290 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1291 {
1292 .matches = {
1293 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1294 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1295 },
1296 .driver_data = "20180406", /* 1.31 */
1297 },
1298 {
1299 .matches = {
1300 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1301 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1302 },
1303 .driver_data = "20180420", /* 1.28 */
1304 },
1305 {
1306 .matches = {
1307 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1308 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1309 },
1310 .driver_data = "20180315", /* 1.33 */
1311 },
1312 {
1313 .matches = {
1314 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1315 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1316 },
1317 /*
1318 * Note date based on release notes, 2.35 has been
1319 * reported to be good, but I've been unable to get
1320 * a hold of the reporter to get the DMI BIOS date.
1321 * TODO: fix this.
1322 */
1323 .driver_data = "20180310", /* 2.35 */
1324 },
1325 { } /* terminate list */
1326 };
1327 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1328 int year, month, date;
1329 char buf[9];
1330
1331 if (!dmi)
1332 return false;
1333
1334 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1335 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1336
1337 return strcmp(buf, dmi->driver_data) < 0;
1338 }
1339
ahci_broken_online(struct pci_dev * pdev)1340 static bool ahci_broken_online(struct pci_dev *pdev)
1341 {
1342 #define ENCODE_BUSDEVFN(bus, slot, func) \
1343 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1344 static const struct dmi_system_id sysids[] = {
1345 /*
1346 * There are several gigabyte boards which use
1347 * SIMG5723s configured as hardware RAID. Certain
1348 * 5723 firmware revisions shipped there keep the link
1349 * online but fail to answer properly to SRST or
1350 * IDENTIFY when no device is attached downstream
1351 * causing libata to retry quite a few times leading
1352 * to excessive detection delay.
1353 *
1354 * As these firmwares respond to the second reset try
1355 * with invalid device signature, considering unknown
1356 * sig as offline works around the problem acceptably.
1357 */
1358 {
1359 .ident = "EP45-DQ6",
1360 .matches = {
1361 DMI_MATCH(DMI_BOARD_VENDOR,
1362 "Gigabyte Technology Co., Ltd."),
1363 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1364 },
1365 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1366 },
1367 {
1368 .ident = "EP45-DS5",
1369 .matches = {
1370 DMI_MATCH(DMI_BOARD_VENDOR,
1371 "Gigabyte Technology Co., Ltd."),
1372 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1373 },
1374 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1375 },
1376 { } /* terminate list */
1377 };
1378 #undef ENCODE_BUSDEVFN
1379 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1380 unsigned int val;
1381
1382 if (!dmi)
1383 return false;
1384
1385 val = (unsigned long)dmi->driver_data;
1386
1387 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1388 }
1389
ahci_broken_devslp(struct pci_dev * pdev)1390 static bool ahci_broken_devslp(struct pci_dev *pdev)
1391 {
1392 /* device with broken DEVSLP but still showing SDS capability */
1393 static const struct pci_device_id ids[] = {
1394 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1395 {}
1396 };
1397
1398 return pci_match_id(ids, pdev);
1399 }
1400
1401 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1402 static void ahci_gtf_filter_workaround(struct ata_host *host)
1403 {
1404 static const struct dmi_system_id sysids[] = {
1405 /*
1406 * Aspire 3810T issues a bunch of SATA enable commands
1407 * via _GTF including an invalid one and one which is
1408 * rejected by the device. Among the successful ones
1409 * is FPDMA non-zero offset enable which when enabled
1410 * only on the drive side leads to NCQ command
1411 * failures. Filter it out.
1412 */
1413 {
1414 .ident = "Aspire 3810T",
1415 .matches = {
1416 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1417 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1418 },
1419 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1420 },
1421 { }
1422 };
1423 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1424 unsigned int filter;
1425 int i;
1426
1427 if (!dmi)
1428 return;
1429
1430 filter = (unsigned long)dmi->driver_data;
1431 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1432 filter, dmi->ident);
1433
1434 for (i = 0; i < host->n_ports; i++) {
1435 struct ata_port *ap = host->ports[i];
1436 struct ata_link *link;
1437 struct ata_device *dev;
1438
1439 ata_for_each_link(link, ap, EDGE)
1440 ata_for_each_dev(dev, link, ALL)
1441 dev->gtf_filter |= filter;
1442 }
1443 }
1444 #else
ahci_gtf_filter_workaround(struct ata_host * host)1445 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1446 {}
1447 #endif
1448
1449 /*
1450 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1451 * as DUMMY, or detected but eventually get a "link down" and never get up
1452 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1453 * port_map may hold a value of 0x00.
1454 *
1455 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1456 * and can significantly reduce the occurrence of the problem.
1457 *
1458 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1459 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1460 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1461 struct pci_dev *pdev)
1462 {
1463 static const struct dmi_system_id sysids[] = {
1464 {
1465 .ident = "Acer Switch Alpha 12",
1466 .matches = {
1467 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1468 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1469 },
1470 },
1471 { }
1472 };
1473
1474 if (dmi_check_system(sysids)) {
1475 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1476 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1477 hpriv->port_map = 0x7;
1478 hpriv->cap = 0xC734FF02;
1479 }
1480 }
1481 }
1482
1483 #ifdef CONFIG_ARM64
1484 /*
1485 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1486 * Workaround is to make sure all pending IRQs are served before leaving
1487 * handler.
1488 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1489 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1490 {
1491 struct ata_host *host = dev_instance;
1492 struct ahci_host_priv *hpriv;
1493 unsigned int rc = 0;
1494 void __iomem *mmio;
1495 u32 irq_stat, irq_masked;
1496 unsigned int handled = 1;
1497
1498 VPRINTK("ENTER\n");
1499 hpriv = host->private_data;
1500 mmio = hpriv->mmio;
1501 irq_stat = readl(mmio + HOST_IRQ_STAT);
1502 if (!irq_stat)
1503 return IRQ_NONE;
1504
1505 do {
1506 irq_masked = irq_stat & hpriv->port_map;
1507 spin_lock(&host->lock);
1508 rc = ahci_handle_port_intr(host, irq_masked);
1509 if (!rc)
1510 handled = 0;
1511 writel(irq_stat, mmio + HOST_IRQ_STAT);
1512 irq_stat = readl(mmio + HOST_IRQ_STAT);
1513 spin_unlock(&host->lock);
1514 } while (irq_stat);
1515 VPRINTK("EXIT\n");
1516
1517 return IRQ_RETVAL(handled);
1518 }
1519 #endif
1520
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1521 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1522 struct ahci_host_priv *hpriv)
1523 {
1524 int i;
1525 u32 cap;
1526
1527 /*
1528 * Check if this device might have remapped nvme devices.
1529 */
1530 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1531 pci_resource_len(pdev, bar) < SZ_512K ||
1532 bar != AHCI_PCI_BAR_STANDARD ||
1533 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1534 return;
1535
1536 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1537 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1538 if ((cap & (1 << i)) == 0)
1539 continue;
1540 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1541 != PCI_CLASS_STORAGE_EXPRESS)
1542 continue;
1543
1544 /* We've found a remapped device */
1545 hpriv->remapped_nvme++;
1546 }
1547
1548 if (!hpriv->remapped_nvme)
1549 return;
1550
1551 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1552 hpriv->remapped_nvme);
1553 dev_warn(&pdev->dev,
1554 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1555
1556 /*
1557 * Don't rely on the msi-x capability in the remap case,
1558 * share the legacy interrupt across ahci and remapped devices.
1559 */
1560 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1561 }
1562
ahci_get_irq_vector(struct ata_host * host,int port)1563 static int ahci_get_irq_vector(struct ata_host *host, int port)
1564 {
1565 return pci_irq_vector(to_pci_dev(host->dev), port);
1566 }
1567
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1568 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1569 struct ahci_host_priv *hpriv)
1570 {
1571 int nvec;
1572
1573 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1574 return -ENODEV;
1575
1576 /*
1577 * If number of MSIs is less than number of ports then Sharing Last
1578 * Message mode could be enforced. In this case assume that advantage
1579 * of multipe MSIs is negated and use single MSI mode instead.
1580 */
1581 if (n_ports > 1) {
1582 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1583 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1584 if (nvec > 0) {
1585 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1586 hpriv->get_irq_vector = ahci_get_irq_vector;
1587 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1588 return nvec;
1589 }
1590
1591 /*
1592 * Fallback to single MSI mode if the controller
1593 * enforced MRSM mode.
1594 */
1595 printk(KERN_INFO
1596 "ahci: MRSM is on, fallback to single MSI\n");
1597 pci_free_irq_vectors(pdev);
1598 }
1599 }
1600
1601 /*
1602 * If the host is not capable of supporting per-port vectors, fall
1603 * back to single MSI before finally attempting single MSI-X.
1604 */
1605 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1606 if (nvec == 1)
1607 return nvec;
1608 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1609 }
1610
ahci_update_initial_lpm_policy(struct ata_port * ap,struct ahci_host_priv * hpriv)1611 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1612 struct ahci_host_priv *hpriv)
1613 {
1614 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1615
1616
1617 /* Ignore processing for non mobile platforms */
1618 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1619 return;
1620
1621 /* user modified policy via module param */
1622 if (mobile_lpm_policy != -1) {
1623 policy = mobile_lpm_policy;
1624 goto update_policy;
1625 }
1626
1627 #ifdef CONFIG_ACPI
1628 if (policy > ATA_LPM_MED_POWER &&
1629 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1630 if (hpriv->cap & HOST_CAP_PART)
1631 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1632 else if (hpriv->cap & HOST_CAP_SSC)
1633 policy = ATA_LPM_MIN_POWER;
1634 }
1635 #endif
1636
1637 update_policy:
1638 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1639 ap->target_lpm_policy = policy;
1640 }
1641
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1642 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1643 {
1644 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1645 u16 tmp16;
1646
1647 /*
1648 * Only apply the 6-port PCS quirk for known legacy platforms.
1649 */
1650 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1651 return;
1652
1653 /* Skip applying the quirk on Denverton and beyond */
1654 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1655 return;
1656
1657 /*
1658 * port_map is determined from PORTS_IMPL PCI register which is
1659 * implemented as write or write-once register. If the register
1660 * isn't programmed, ahci automatically generates it from number
1661 * of ports, which is good enough for PCS programming. It is
1662 * otherwise expected that platform firmware enables the ports
1663 * before the OS boots.
1664 */
1665 pci_read_config_word(pdev, PCS_6, &tmp16);
1666 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1667 tmp16 |= hpriv->port_map;
1668 pci_write_config_word(pdev, PCS_6, tmp16);
1669 }
1670 }
1671
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)1672 static ssize_t remapped_nvme_show(struct device *dev,
1673 struct device_attribute *attr,
1674 char *buf)
1675 {
1676 struct ata_host *host = dev_get_drvdata(dev);
1677 struct ahci_host_priv *hpriv = host->private_data;
1678
1679 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1680 }
1681
1682 static DEVICE_ATTR_RO(remapped_nvme);
1683
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1684 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1685 {
1686 unsigned int board_id = ent->driver_data;
1687 struct ata_port_info pi = ahci_port_info[board_id];
1688 const struct ata_port_info *ppi[] = { &pi, NULL };
1689 struct device *dev = &pdev->dev;
1690 struct ahci_host_priv *hpriv;
1691 struct ata_host *host;
1692 int n_ports, i, rc;
1693 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1694
1695 VPRINTK("ENTER\n");
1696
1697 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1698
1699 ata_print_version_once(&pdev->dev, DRV_VERSION);
1700
1701 /* The AHCI driver can only drive the SATA ports, the PATA driver
1702 can drive them all so if both drivers are selected make sure
1703 AHCI stays out of the way */
1704 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1705 return -ENODEV;
1706
1707 /* Apple BIOS on MCP89 prevents us using AHCI */
1708 if (is_mcp89_apple(pdev))
1709 ahci_mcp89_apple_enable(pdev);
1710
1711 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1712 * At the moment, we can only use the AHCI mode. Let the users know
1713 * that for SAS drives they're out of luck.
1714 */
1715 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1716 dev_info(&pdev->dev,
1717 "PDC42819 can only drive SATA devices with this driver\n");
1718
1719 /* Some devices use non-standard BARs */
1720 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1721 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1722 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1723 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1724 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1725 if (pdev->device == 0xa01c)
1726 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1727 if (pdev->device == 0xa084)
1728 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1729 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1730 if (pdev->device == 0x7a08)
1731 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1732 }
1733
1734 /* acquire resources */
1735 rc = pcim_enable_device(pdev);
1736 if (rc)
1737 return rc;
1738
1739 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1740 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1741 u8 map;
1742
1743 /* ICH6s share the same PCI ID for both piix and ahci
1744 * modes. Enabling ahci mode while MAP indicates
1745 * combined mode is a bad idea. Yield to ata_piix.
1746 */
1747 pci_read_config_byte(pdev, ICH_MAP, &map);
1748 if (map & 0x3) {
1749 dev_info(&pdev->dev,
1750 "controller is in combined mode, can't enable AHCI mode\n");
1751 return -ENODEV;
1752 }
1753 }
1754
1755 /* AHCI controllers often implement SFF compatible interface.
1756 * Grab all PCI BARs just in case.
1757 */
1758 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1759 if (rc == -EBUSY)
1760 pcim_pin_device(pdev);
1761 if (rc)
1762 return rc;
1763
1764 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1765 if (!hpriv)
1766 return -ENOMEM;
1767 hpriv->flags |= (unsigned long)pi.private_data;
1768
1769 /* MCP65 revision A1 and A2 can't do MSI */
1770 if (board_id == board_ahci_mcp65 &&
1771 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1772 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1773
1774 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1775 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1776 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1777
1778 /* only some SB600s can do 64bit DMA */
1779 if (ahci_sb600_enable_64bit(pdev))
1780 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1781
1782 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1783
1784 /* detect remapped nvme devices */
1785 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1786
1787 sysfs_add_file_to_group(&pdev->dev.kobj,
1788 &dev_attr_remapped_nvme.attr,
1789 NULL);
1790
1791 /* must set flag prior to save config in order to take effect */
1792 if (ahci_broken_devslp(pdev))
1793 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1794
1795 #ifdef CONFIG_ARM64
1796 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1797 pdev->device == 0xa235 &&
1798 pdev->revision < 0x30)
1799 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1800
1801 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1802 hpriv->irq_handler = ahci_thunderx_irq_handler;
1803 #endif
1804
1805 /* save initial config */
1806 ahci_pci_save_initial_config(pdev, hpriv);
1807
1808 /* prepare host */
1809 if (hpriv->cap & HOST_CAP_NCQ) {
1810 pi.flags |= ATA_FLAG_NCQ;
1811 /*
1812 * Auto-activate optimization is supposed to be
1813 * supported on all AHCI controllers indicating NCQ
1814 * capability, but it seems to be broken on some
1815 * chipsets including NVIDIAs.
1816 */
1817 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1818 pi.flags |= ATA_FLAG_FPDMA_AA;
1819
1820 /*
1821 * All AHCI controllers should be forward-compatible
1822 * with the new auxiliary field. This code should be
1823 * conditionalized if any buggy AHCI controllers are
1824 * encountered.
1825 */
1826 pi.flags |= ATA_FLAG_FPDMA_AUX;
1827 }
1828
1829 if (hpriv->cap & HOST_CAP_PMP)
1830 pi.flags |= ATA_FLAG_PMP;
1831
1832 ahci_set_em_messages(hpriv, &pi);
1833
1834 if (ahci_broken_system_poweroff(pdev)) {
1835 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1836 dev_info(&pdev->dev,
1837 "quirky BIOS, skipping spindown on poweroff\n");
1838 }
1839
1840 if (ahci_broken_lpm(pdev)) {
1841 pi.flags |= ATA_FLAG_NO_LPM;
1842 dev_warn(&pdev->dev,
1843 "BIOS update required for Link Power Management support\n");
1844 }
1845
1846 if (ahci_broken_suspend(pdev)) {
1847 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1848 dev_warn(&pdev->dev,
1849 "BIOS update required for suspend/resume\n");
1850 }
1851
1852 if (ahci_broken_online(pdev)) {
1853 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1854 dev_info(&pdev->dev,
1855 "online status unreliable, applying workaround\n");
1856 }
1857
1858
1859 /* Acer SA5-271 workaround modifies private_data */
1860 acer_sa5_271_workaround(hpriv, pdev);
1861
1862 /* CAP.NP sometimes indicate the index of the last enabled
1863 * port, at other times, that of the last possible port, so
1864 * determining the maximum port number requires looking at
1865 * both CAP.NP and port_map.
1866 */
1867 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1868
1869 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1870 if (!host)
1871 return -ENOMEM;
1872 host->private_data = hpriv;
1873
1874 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1875 /* legacy intx interrupts */
1876 pci_intx(pdev, 1);
1877 }
1878 hpriv->irq = pci_irq_vector(pdev, 0);
1879
1880 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1881 host->flags |= ATA_HOST_PARALLEL_SCAN;
1882 else
1883 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1884
1885 if (pi.flags & ATA_FLAG_EM)
1886 ahci_reset_em(host);
1887
1888 for (i = 0; i < host->n_ports; i++) {
1889 struct ata_port *ap = host->ports[i];
1890
1891 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1892 ata_port_pbar_desc(ap, ahci_pci_bar,
1893 0x100 + ap->port_no * 0x80, "port");
1894
1895 /* set enclosure management message type */
1896 if (ap->flags & ATA_FLAG_EM)
1897 ap->em_message_type = hpriv->em_msg_type;
1898
1899 ahci_update_initial_lpm_policy(ap, hpriv);
1900
1901 /* disabled/not-implemented port */
1902 if (!(hpriv->port_map & (1 << i)))
1903 ap->ops = &ata_dummy_port_ops;
1904 }
1905
1906 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1907 ahci_p5wdh_workaround(host);
1908
1909 /* apply gtf filter quirk */
1910 ahci_gtf_filter_workaround(host);
1911
1912 /* initialize adapter */
1913 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1914 if (rc)
1915 return rc;
1916
1917 rc = ahci_pci_reset_controller(host);
1918 if (rc)
1919 return rc;
1920
1921 ahci_pci_init_controller(host);
1922 ahci_pci_print_info(host);
1923
1924 pci_set_master(pdev);
1925
1926 rc = ahci_host_activate(host, &ahci_sht);
1927 if (rc)
1928 return rc;
1929
1930 pm_runtime_put_noidle(&pdev->dev);
1931 return 0;
1932 }
1933
ahci_shutdown_one(struct pci_dev * pdev)1934 static void ahci_shutdown_one(struct pci_dev *pdev)
1935 {
1936 ata_pci_shutdown_one(pdev);
1937 }
1938
ahci_remove_one(struct pci_dev * pdev)1939 static void ahci_remove_one(struct pci_dev *pdev)
1940 {
1941 sysfs_remove_file_from_group(&pdev->dev.kobj,
1942 &dev_attr_remapped_nvme.attr,
1943 NULL);
1944 pm_runtime_get_noresume(&pdev->dev);
1945 ata_pci_remove_one(pdev);
1946 }
1947
1948 module_pci_driver(ahci_pci_driver);
1949
1950 MODULE_AUTHOR("Jeff Garzik");
1951 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1952 MODULE_LICENSE("GPL");
1953 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1954 MODULE_VERSION(DRV_VERSION);
1955