1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
4 *
5 * Copyright (C) 2014 Atmel Corporation
6 *
7 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
8 */
9
10 #include <asm/barrier.h>
11 #include <dt-bindings/dma/at91.h>
12 #include <linux/clk.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dmapool.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/module.h>
20 #include <linux/of_dma.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm.h>
24
25 #include "dmaengine.h"
26
27 /* Global registers */
28 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
29 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
30 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
31 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
32 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
33 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
34 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
35 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
36 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
37 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
38 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
39 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
40 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
41 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
42 #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
43 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
44 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
45 #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
46 #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
47 #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
48 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
49
50 /* Channel relative registers offsets */
51 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
52 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
53 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
54 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
55 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
56 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
57 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
58 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
59 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
60 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
61 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
62 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
63 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
64 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
65 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
66 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
67 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
68 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
69 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
70 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
71 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
72 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
73 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
74 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
75 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
76 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
77 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
78 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
79 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
80 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
81 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
82 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
83 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
84 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
85 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
86 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
87 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
88 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
89 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
90 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
91 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
92 #define AT_XDMAC_CNDC_NDVIEW_MASK GENMASK(28, 27)
93 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
94 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
95 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
96 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
97 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
98 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
99 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
100 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
101 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
102 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
103 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
104 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
105 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
106 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
107 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
108 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
109 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
110 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
111 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
112 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
113 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
114 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
115 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
116 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
117 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
118 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
119 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
120 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
121 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
122 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
123 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
124 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
125 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
126 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
127 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
128 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
129 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
130 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
131 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
132 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
133 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
134 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
135 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
136 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
137 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
138 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
139 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
140 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
141 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
142 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
143 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
144 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
145 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
146 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
147 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
148 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
149 #define AT_XDMAC_CC_PERID(i) ((0x7f & (i)) << 24) /* Channel Peripheral Identifier */
150 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
151 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
152 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
153
154 #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
155
156 /* Microblock control members */
157 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
158 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
159 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
160 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
161 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
162 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
163 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
164 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
165
166 #define AT_XDMAC_MAX_CHAN 0x20
167 #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
168 #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
169 #define AT_XDMAC_RESIDUE_MAX_RETRIES 5
170
171 #define AT_XDMAC_DMA_BUSWIDTHS\
172 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
173 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
174 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
175 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
176 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
177
178 enum atc_status {
179 AT_XDMAC_CHAN_IS_CYCLIC = 0,
180 AT_XDMAC_CHAN_IS_PAUSED,
181 };
182
183 /* ----- Channels ----- */
184 struct at_xdmac_chan {
185 struct dma_chan chan;
186 void __iomem *ch_regs;
187 u32 mask; /* Channel Mask */
188 u32 cfg; /* Channel Configuration Register */
189 u8 perid; /* Peripheral ID */
190 u8 perif; /* Peripheral Interface */
191 u8 memif; /* Memory Interface */
192 u32 save_cc;
193 u32 save_cim;
194 u32 save_cnda;
195 u32 save_cndc;
196 u32 irq_status;
197 unsigned long status;
198 struct tasklet_struct tasklet;
199 struct dma_slave_config sconfig;
200
201 spinlock_t lock;
202
203 struct list_head xfers_list;
204 struct list_head free_descs_list;
205 };
206
207
208 /* ----- Controller ----- */
209 struct at_xdmac {
210 struct dma_device dma;
211 void __iomem *regs;
212 int irq;
213 struct clk *clk;
214 u32 save_gim;
215 struct dma_pool *at_xdmac_desc_pool;
216 struct at_xdmac_chan chan[];
217 };
218
219
220 /* ----- Descriptors ----- */
221
222 /* Linked List Descriptor */
223 struct at_xdmac_lld {
224 u32 mbr_nda; /* Next Descriptor Member */
225 u32 mbr_ubc; /* Microblock Control Member */
226 u32 mbr_sa; /* Source Address Member */
227 u32 mbr_da; /* Destination Address Member */
228 u32 mbr_cfg; /* Configuration Register */
229 u32 mbr_bc; /* Block Control Register */
230 u32 mbr_ds; /* Data Stride Register */
231 u32 mbr_sus; /* Source Microblock Stride Register */
232 u32 mbr_dus; /* Destination Microblock Stride Register */
233 };
234
235 /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */
236 struct at_xdmac_desc {
237 struct at_xdmac_lld lld;
238 enum dma_transfer_direction direction;
239 struct dma_async_tx_descriptor tx_dma_desc;
240 struct list_head desc_node;
241 /* Following members are only used by the first descriptor */
242 bool active_xfer;
243 unsigned int xfer_size;
244 struct list_head descs_list;
245 struct list_head xfer_node;
246 } __aligned(sizeof(u64));
247
at_xdmac_chan_reg_base(struct at_xdmac * atxdmac,unsigned int chan_nb)248 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
249 {
250 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
251 }
252
253 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
254 #define at_xdmac_write(atxdmac, reg, value) \
255 writel_relaxed((value), (atxdmac)->regs + (reg))
256
257 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
258 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
259
to_at_xdmac_chan(struct dma_chan * dchan)260 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
261 {
262 return container_of(dchan, struct at_xdmac_chan, chan);
263 }
264
chan2dev(struct dma_chan * chan)265 static struct device *chan2dev(struct dma_chan *chan)
266 {
267 return &chan->dev->device;
268 }
269
to_at_xdmac(struct dma_device * ddev)270 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
271 {
272 return container_of(ddev, struct at_xdmac, dma);
273 }
274
txd_to_at_desc(struct dma_async_tx_descriptor * txd)275 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
276 {
277 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
278 }
279
at_xdmac_chan_is_cyclic(struct at_xdmac_chan * atchan)280 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
281 {
282 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
283 }
284
at_xdmac_chan_is_paused(struct at_xdmac_chan * atchan)285 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
286 {
287 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
288 }
289
at_xdmac_csize(u32 maxburst)290 static inline int at_xdmac_csize(u32 maxburst)
291 {
292 int csize;
293
294 csize = ffs(maxburst) - 1;
295 if (csize > 4)
296 csize = -EINVAL;
297
298 return csize;
299 };
300
at_xdmac_chan_is_peripheral_xfer(u32 cfg)301 static inline bool at_xdmac_chan_is_peripheral_xfer(u32 cfg)
302 {
303 return cfg & AT_XDMAC_CC_TYPE_PER_TRAN;
304 }
305
at_xdmac_get_dwidth(u32 cfg)306 static inline u8 at_xdmac_get_dwidth(u32 cfg)
307 {
308 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
309 };
310
311 static unsigned int init_nr_desc_per_channel = 64;
312 module_param(init_nr_desc_per_channel, uint, 0644);
313 MODULE_PARM_DESC(init_nr_desc_per_channel,
314 "initial descriptors per channel (default: 64)");
315
316
at_xdmac_chan_is_enabled(struct at_xdmac_chan * atchan)317 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
318 {
319 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
320 }
321
at_xdmac_off(struct at_xdmac * atxdmac)322 static void at_xdmac_off(struct at_xdmac *atxdmac)
323 {
324 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
325
326 /* Wait that all chans are disabled. */
327 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
328 cpu_relax();
329
330 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
331 }
332
333 /* Call with lock hold. */
at_xdmac_start_xfer(struct at_xdmac_chan * atchan,struct at_xdmac_desc * first)334 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
335 struct at_xdmac_desc *first)
336 {
337 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
338 u32 reg;
339
340 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
341
342 /* Set transfer as active to not try to start it again. */
343 first->active_xfer = true;
344
345 /* Tell xdmac where to get the first descriptor. */
346 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
347 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
348 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
349
350 /*
351 * When doing non cyclic transfer we need to use the next
352 * descriptor view 2 since some fields of the configuration register
353 * depend on transfer size and src/dest addresses.
354 */
355 if (at_xdmac_chan_is_cyclic(atchan))
356 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
357 else if ((first->lld.mbr_ubc &
358 AT_XDMAC_CNDC_NDVIEW_MASK) == AT_XDMAC_MBR_UBC_NDV3)
359 reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
360 else
361 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
362 /*
363 * Even if the register will be updated from the configuration in the
364 * descriptor when using view 2 or higher, the PROT bit won't be set
365 * properly. This bit can be modified only by using the channel
366 * configuration register.
367 */
368 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
369
370 reg |= AT_XDMAC_CNDC_NDDUP
371 | AT_XDMAC_CNDC_NDSUP
372 | AT_XDMAC_CNDC_NDE;
373 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
374
375 dev_vdbg(chan2dev(&atchan->chan),
376 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
377 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
378 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
379 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
380 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
381 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
382 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
383
384 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
385 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE;
386 /*
387 * Request Overflow Error is only for peripheral synchronized transfers
388 */
389 if (at_xdmac_chan_is_peripheral_xfer(first->lld.mbr_cfg))
390 reg |= AT_XDMAC_CIE_ROIE;
391
392 /*
393 * There is no end of list when doing cyclic dma, we need to get
394 * an interrupt after each periods.
395 */
396 if (at_xdmac_chan_is_cyclic(atchan))
397 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
398 reg | AT_XDMAC_CIE_BIE);
399 else
400 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
401 reg | AT_XDMAC_CIE_LIE);
402 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
403 dev_vdbg(chan2dev(&atchan->chan),
404 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
405 wmb();
406 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
407
408 dev_vdbg(chan2dev(&atchan->chan),
409 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
410 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
411 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
412 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
413 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
414 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
415 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
416
417 }
418
at_xdmac_tx_submit(struct dma_async_tx_descriptor * tx)419 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
420 {
421 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
422 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
423 dma_cookie_t cookie;
424 unsigned long irqflags;
425
426 spin_lock_irqsave(&atchan->lock, irqflags);
427 cookie = dma_cookie_assign(tx);
428
429 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
430 spin_unlock_irqrestore(&atchan->lock, irqflags);
431
432 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
433 __func__, atchan, desc);
434
435 return cookie;
436 }
437
at_xdmac_alloc_desc(struct dma_chan * chan,gfp_t gfp_flags)438 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
439 gfp_t gfp_flags)
440 {
441 struct at_xdmac_desc *desc;
442 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
443 dma_addr_t phys;
444
445 desc = dma_pool_zalloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
446 if (desc) {
447 INIT_LIST_HEAD(&desc->descs_list);
448 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
449 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
450 desc->tx_dma_desc.phys = phys;
451 }
452
453 return desc;
454 }
455
at_xdmac_init_used_desc(struct at_xdmac_desc * desc)456 static void at_xdmac_init_used_desc(struct at_xdmac_desc *desc)
457 {
458 memset(&desc->lld, 0, sizeof(desc->lld));
459 INIT_LIST_HEAD(&desc->descs_list);
460 desc->direction = DMA_TRANS_NONE;
461 desc->xfer_size = 0;
462 desc->active_xfer = false;
463 }
464
465 /* Call must be protected by lock. */
at_xdmac_get_desc(struct at_xdmac_chan * atchan)466 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
467 {
468 struct at_xdmac_desc *desc;
469
470 if (list_empty(&atchan->free_descs_list)) {
471 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
472 } else {
473 desc = list_first_entry(&atchan->free_descs_list,
474 struct at_xdmac_desc, desc_node);
475 list_del(&desc->desc_node);
476 at_xdmac_init_used_desc(desc);
477 }
478
479 return desc;
480 }
481
at_xdmac_queue_desc(struct dma_chan * chan,struct at_xdmac_desc * prev,struct at_xdmac_desc * desc)482 static void at_xdmac_queue_desc(struct dma_chan *chan,
483 struct at_xdmac_desc *prev,
484 struct at_xdmac_desc *desc)
485 {
486 if (!prev || !desc)
487 return;
488
489 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
490 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE;
491
492 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
493 __func__, prev, &prev->lld.mbr_nda);
494 }
495
at_xdmac_increment_block_count(struct dma_chan * chan,struct at_xdmac_desc * desc)496 static inline void at_xdmac_increment_block_count(struct dma_chan *chan,
497 struct at_xdmac_desc *desc)
498 {
499 if (!desc)
500 return;
501
502 desc->lld.mbr_bc++;
503
504 dev_dbg(chan2dev(chan),
505 "%s: incrementing the block count of the desc 0x%p\n",
506 __func__, desc);
507 }
508
at_xdmac_xlate(struct of_phandle_args * dma_spec,struct of_dma * of_dma)509 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
510 struct of_dma *of_dma)
511 {
512 struct at_xdmac *atxdmac = of_dma->of_dma_data;
513 struct at_xdmac_chan *atchan;
514 struct dma_chan *chan;
515 struct device *dev = atxdmac->dma.dev;
516
517 if (dma_spec->args_count != 1) {
518 dev_err(dev, "dma phandler args: bad number of args\n");
519 return NULL;
520 }
521
522 chan = dma_get_any_slave_channel(&atxdmac->dma);
523 if (!chan) {
524 dev_err(dev, "can't get a dma channel\n");
525 return NULL;
526 }
527
528 atchan = to_at_xdmac_chan(chan);
529 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
530 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
531 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
532 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
533 atchan->memif, atchan->perif, atchan->perid);
534
535 return chan;
536 }
537
at_xdmac_compute_chan_conf(struct dma_chan * chan,enum dma_transfer_direction direction)538 static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
539 enum dma_transfer_direction direction)
540 {
541 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
542 int csize, dwidth;
543
544 if (direction == DMA_DEV_TO_MEM) {
545 atchan->cfg =
546 AT91_XDMAC_DT_PERID(atchan->perid)
547 | AT_XDMAC_CC_DAM_INCREMENTED_AM
548 | AT_XDMAC_CC_SAM_FIXED_AM
549 | AT_XDMAC_CC_DIF(atchan->memif)
550 | AT_XDMAC_CC_SIF(atchan->perif)
551 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
552 | AT_XDMAC_CC_DSYNC_PER2MEM
553 | AT_XDMAC_CC_MBSIZE_SIXTEEN
554 | AT_XDMAC_CC_TYPE_PER_TRAN;
555 csize = ffs(atchan->sconfig.src_maxburst) - 1;
556 if (csize < 0) {
557 dev_err(chan2dev(chan), "invalid src maxburst value\n");
558 return -EINVAL;
559 }
560 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
561 dwidth = ffs(atchan->sconfig.src_addr_width) - 1;
562 if (dwidth < 0) {
563 dev_err(chan2dev(chan), "invalid src addr width value\n");
564 return -EINVAL;
565 }
566 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
567 } else if (direction == DMA_MEM_TO_DEV) {
568 atchan->cfg =
569 AT91_XDMAC_DT_PERID(atchan->perid)
570 | AT_XDMAC_CC_DAM_FIXED_AM
571 | AT_XDMAC_CC_SAM_INCREMENTED_AM
572 | AT_XDMAC_CC_DIF(atchan->perif)
573 | AT_XDMAC_CC_SIF(atchan->memif)
574 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
575 | AT_XDMAC_CC_DSYNC_MEM2PER
576 | AT_XDMAC_CC_MBSIZE_SIXTEEN
577 | AT_XDMAC_CC_TYPE_PER_TRAN;
578 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
579 if (csize < 0) {
580 dev_err(chan2dev(chan), "invalid src maxburst value\n");
581 return -EINVAL;
582 }
583 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
584 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1;
585 if (dwidth < 0) {
586 dev_err(chan2dev(chan), "invalid dst addr width value\n");
587 return -EINVAL;
588 }
589 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
590 }
591
592 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg);
593
594 return 0;
595 }
596
597 /*
598 * Only check that maxburst and addr width values are supported by the
599 * the controller but not that the configuration is good to perform the
600 * transfer since we don't know the direction at this stage.
601 */
at_xdmac_check_slave_config(struct dma_slave_config * sconfig)602 static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig)
603 {
604 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE)
605 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE))
606 return -EINVAL;
607
608 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH)
609 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH))
610 return -EINVAL;
611
612 return 0;
613 }
614
at_xdmac_set_slave_config(struct dma_chan * chan,struct dma_slave_config * sconfig)615 static int at_xdmac_set_slave_config(struct dma_chan *chan,
616 struct dma_slave_config *sconfig)
617 {
618 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
619
620 if (at_xdmac_check_slave_config(sconfig)) {
621 dev_err(chan2dev(chan), "invalid slave configuration\n");
622 return -EINVAL;
623 }
624
625 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig));
626
627 return 0;
628 }
629
630 static struct dma_async_tx_descriptor *
at_xdmac_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)631 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
632 unsigned int sg_len, enum dma_transfer_direction direction,
633 unsigned long flags, void *context)
634 {
635 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
636 struct at_xdmac_desc *first = NULL, *prev = NULL;
637 struct scatterlist *sg;
638 int i;
639 unsigned int xfer_size = 0;
640 unsigned long irqflags;
641 struct dma_async_tx_descriptor *ret = NULL;
642
643 if (!sgl)
644 return NULL;
645
646 if (!is_slave_direction(direction)) {
647 dev_err(chan2dev(chan), "invalid DMA direction\n");
648 return NULL;
649 }
650
651 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
652 __func__, sg_len,
653 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
654 flags);
655
656 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
657 spin_lock_irqsave(&atchan->lock, irqflags);
658
659 if (at_xdmac_compute_chan_conf(chan, direction))
660 goto spin_unlock;
661
662 /* Prepare descriptors. */
663 for_each_sg(sgl, sg, sg_len, i) {
664 struct at_xdmac_desc *desc = NULL;
665 u32 len, mem, dwidth, fixed_dwidth;
666
667 len = sg_dma_len(sg);
668 mem = sg_dma_address(sg);
669 if (unlikely(!len)) {
670 dev_err(chan2dev(chan), "sg data length is zero\n");
671 goto spin_unlock;
672 }
673 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
674 __func__, i, len, mem);
675
676 desc = at_xdmac_get_desc(atchan);
677 if (!desc) {
678 dev_err(chan2dev(chan), "can't get descriptor\n");
679 if (first)
680 list_splice_init(&first->descs_list, &atchan->free_descs_list);
681 goto spin_unlock;
682 }
683
684 /* Linked list descriptor setup. */
685 if (direction == DMA_DEV_TO_MEM) {
686 desc->lld.mbr_sa = atchan->sconfig.src_addr;
687 desc->lld.mbr_da = mem;
688 } else {
689 desc->lld.mbr_sa = mem;
690 desc->lld.mbr_da = atchan->sconfig.dst_addr;
691 }
692 dwidth = at_xdmac_get_dwidth(atchan->cfg);
693 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
694 ? dwidth
695 : AT_XDMAC_CC_DWIDTH_BYTE;
696 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
697 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
698 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
699 | (len >> fixed_dwidth); /* microblock length */
700 desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
701 AT_XDMAC_CC_DWIDTH(fixed_dwidth);
702 dev_dbg(chan2dev(chan),
703 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
704 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
705
706 /* Chain lld. */
707 if (prev)
708 at_xdmac_queue_desc(chan, prev, desc);
709
710 prev = desc;
711 if (!first)
712 first = desc;
713
714 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
715 __func__, desc, first);
716 list_add_tail(&desc->desc_node, &first->descs_list);
717 xfer_size += len;
718 }
719
720
721 first->tx_dma_desc.flags = flags;
722 first->xfer_size = xfer_size;
723 first->direction = direction;
724 ret = &first->tx_dma_desc;
725
726 spin_unlock:
727 spin_unlock_irqrestore(&atchan->lock, irqflags);
728 return ret;
729 }
730
731 static struct dma_async_tx_descriptor *
at_xdmac_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)732 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
733 size_t buf_len, size_t period_len,
734 enum dma_transfer_direction direction,
735 unsigned long flags)
736 {
737 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
738 struct at_xdmac_desc *first = NULL, *prev = NULL;
739 unsigned int periods = buf_len / period_len;
740 int i;
741 unsigned long irqflags;
742
743 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
744 __func__, &buf_addr, buf_len, period_len,
745 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
746
747 if (!is_slave_direction(direction)) {
748 dev_err(chan2dev(chan), "invalid DMA direction\n");
749 return NULL;
750 }
751
752 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
753 dev_err(chan2dev(chan), "channel currently used\n");
754 return NULL;
755 }
756
757 if (at_xdmac_compute_chan_conf(chan, direction))
758 return NULL;
759
760 for (i = 0; i < periods; i++) {
761 struct at_xdmac_desc *desc = NULL;
762
763 spin_lock_irqsave(&atchan->lock, irqflags);
764 desc = at_xdmac_get_desc(atchan);
765 if (!desc) {
766 dev_err(chan2dev(chan), "can't get descriptor\n");
767 if (first)
768 list_splice_init(&first->descs_list, &atchan->free_descs_list);
769 spin_unlock_irqrestore(&atchan->lock, irqflags);
770 return NULL;
771 }
772 spin_unlock_irqrestore(&atchan->lock, irqflags);
773 dev_dbg(chan2dev(chan),
774 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
775 __func__, desc, &desc->tx_dma_desc.phys);
776
777 if (direction == DMA_DEV_TO_MEM) {
778 desc->lld.mbr_sa = atchan->sconfig.src_addr;
779 desc->lld.mbr_da = buf_addr + i * period_len;
780 } else {
781 desc->lld.mbr_sa = buf_addr + i * period_len;
782 desc->lld.mbr_da = atchan->sconfig.dst_addr;
783 }
784 desc->lld.mbr_cfg = atchan->cfg;
785 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
786 | AT_XDMAC_MBR_UBC_NDEN
787 | AT_XDMAC_MBR_UBC_NSEN
788 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
789
790 dev_dbg(chan2dev(chan),
791 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
792 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
793
794 /* Chain lld. */
795 if (prev)
796 at_xdmac_queue_desc(chan, prev, desc);
797
798 prev = desc;
799 if (!first)
800 first = desc;
801
802 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
803 __func__, desc, first);
804 list_add_tail(&desc->desc_node, &first->descs_list);
805 }
806
807 at_xdmac_queue_desc(chan, prev, first);
808 first->tx_dma_desc.flags = flags;
809 first->xfer_size = buf_len;
810 first->direction = direction;
811
812 return &first->tx_dma_desc;
813 }
814
at_xdmac_align_width(struct dma_chan * chan,dma_addr_t addr)815 static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr)
816 {
817 u32 width;
818
819 /*
820 * Check address alignment to select the greater data width we
821 * can use.
822 *
823 * Some XDMAC implementations don't provide dword transfer, in
824 * this case selecting dword has the same behavior as
825 * selecting word transfers.
826 */
827 if (!(addr & 7)) {
828 width = AT_XDMAC_CC_DWIDTH_DWORD;
829 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
830 } else if (!(addr & 3)) {
831 width = AT_XDMAC_CC_DWIDTH_WORD;
832 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
833 } else if (!(addr & 1)) {
834 width = AT_XDMAC_CC_DWIDTH_HALFWORD;
835 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
836 } else {
837 width = AT_XDMAC_CC_DWIDTH_BYTE;
838 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
839 }
840
841 return width;
842 }
843
844 static struct at_xdmac_desc *
at_xdmac_interleaved_queue_desc(struct dma_chan * chan,struct at_xdmac_chan * atchan,struct at_xdmac_desc * prev,dma_addr_t src,dma_addr_t dst,struct dma_interleaved_template * xt,struct data_chunk * chunk)845 at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
846 struct at_xdmac_chan *atchan,
847 struct at_xdmac_desc *prev,
848 dma_addr_t src, dma_addr_t dst,
849 struct dma_interleaved_template *xt,
850 struct data_chunk *chunk)
851 {
852 struct at_xdmac_desc *desc;
853 u32 dwidth;
854 unsigned long flags;
855 size_t ublen;
856 /*
857 * WARNING: The channel configuration is set here since there is no
858 * dmaengine_slave_config call in this case. Moreover we don't know the
859 * direction, it involves we can't dynamically set the source and dest
860 * interface so we have to use the same one. Only interface 0 allows EBI
861 * access. Hopefully we can access DDR through both ports (at least on
862 * SAMA5D4x), so we can use the same interface for source and dest,
863 * that solves the fact we don't know the direction.
864 * ERRATA: Even if useless for memory transfers, the PERID has to not
865 * match the one of another channel. If not, it could lead to spurious
866 * flag status.
867 */
868 u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
869 | AT_XDMAC_CC_DIF(0)
870 | AT_XDMAC_CC_SIF(0)
871 | AT_XDMAC_CC_MBSIZE_SIXTEEN
872 | AT_XDMAC_CC_TYPE_MEM_TRAN;
873
874 dwidth = at_xdmac_align_width(chan, src | dst | chunk->size);
875 if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
876 dev_dbg(chan2dev(chan),
877 "%s: chunk too big (%zu, max size %lu)...\n",
878 __func__, chunk->size,
879 AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth);
880 return NULL;
881 }
882
883 if (prev)
884 dev_dbg(chan2dev(chan),
885 "Adding items at the end of desc 0x%p\n", prev);
886
887 if (xt->src_inc) {
888 if (xt->src_sgl)
889 chan_cc |= AT_XDMAC_CC_SAM_UBS_AM;
890 else
891 chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM;
892 }
893
894 if (xt->dst_inc) {
895 if (xt->dst_sgl)
896 chan_cc |= AT_XDMAC_CC_DAM_UBS_AM;
897 else
898 chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM;
899 }
900
901 spin_lock_irqsave(&atchan->lock, flags);
902 desc = at_xdmac_get_desc(atchan);
903 spin_unlock_irqrestore(&atchan->lock, flags);
904 if (!desc) {
905 dev_err(chan2dev(chan), "can't get descriptor\n");
906 return NULL;
907 }
908
909 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
910
911 ublen = chunk->size >> dwidth;
912
913 desc->lld.mbr_sa = src;
914 desc->lld.mbr_da = dst;
915 desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk);
916 desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk);
917
918 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
919 | AT_XDMAC_MBR_UBC_NDEN
920 | AT_XDMAC_MBR_UBC_NSEN
921 | ublen;
922 desc->lld.mbr_cfg = chan_cc;
923
924 dev_dbg(chan2dev(chan),
925 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
926 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da,
927 desc->lld.mbr_ubc, desc->lld.mbr_cfg);
928
929 /* Chain lld. */
930 if (prev)
931 at_xdmac_queue_desc(chan, prev, desc);
932
933 return desc;
934 }
935
936 static struct dma_async_tx_descriptor *
at_xdmac_prep_interleaved(struct dma_chan * chan,struct dma_interleaved_template * xt,unsigned long flags)937 at_xdmac_prep_interleaved(struct dma_chan *chan,
938 struct dma_interleaved_template *xt,
939 unsigned long flags)
940 {
941 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
942 struct at_xdmac_desc *prev = NULL, *first = NULL;
943 dma_addr_t dst_addr, src_addr;
944 size_t src_skip = 0, dst_skip = 0, len = 0;
945 struct data_chunk *chunk;
946 int i;
947
948 if (!xt || !xt->numf || (xt->dir != DMA_MEM_TO_MEM))
949 return NULL;
950
951 /*
952 * TODO: Handle the case where we have to repeat a chain of
953 * descriptors...
954 */
955 if ((xt->numf > 1) && (xt->frame_size > 1))
956 return NULL;
957
958 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, numf=%zu, frame_size=%zu, flags=0x%lx\n",
959 __func__, &xt->src_start, &xt->dst_start, xt->numf,
960 xt->frame_size, flags);
961
962 src_addr = xt->src_start;
963 dst_addr = xt->dst_start;
964
965 if (xt->numf > 1) {
966 first = at_xdmac_interleaved_queue_desc(chan, atchan,
967 NULL,
968 src_addr, dst_addr,
969 xt, xt->sgl);
970
971 /* Length of the block is (BLEN+1) microblocks. */
972 for (i = 0; i < xt->numf - 1; i++)
973 at_xdmac_increment_block_count(chan, first);
974
975 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
976 __func__, first, first);
977 list_add_tail(&first->desc_node, &first->descs_list);
978 } else {
979 for (i = 0; i < xt->frame_size; i++) {
980 size_t src_icg = 0, dst_icg = 0;
981 struct at_xdmac_desc *desc;
982
983 chunk = xt->sgl + i;
984
985 dst_icg = dmaengine_get_dst_icg(xt, chunk);
986 src_icg = dmaengine_get_src_icg(xt, chunk);
987
988 src_skip = chunk->size + src_icg;
989 dst_skip = chunk->size + dst_icg;
990
991 dev_dbg(chan2dev(chan),
992 "%s: chunk size=%zu, src icg=%zu, dst icg=%zu\n",
993 __func__, chunk->size, src_icg, dst_icg);
994
995 desc = at_xdmac_interleaved_queue_desc(chan, atchan,
996 prev,
997 src_addr, dst_addr,
998 xt, chunk);
999 if (!desc) {
1000 list_splice_init(&first->descs_list,
1001 &atchan->free_descs_list);
1002 return NULL;
1003 }
1004
1005 if (!first)
1006 first = desc;
1007
1008 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1009 __func__, desc, first);
1010 list_add_tail(&desc->desc_node, &first->descs_list);
1011
1012 if (xt->src_sgl)
1013 src_addr += src_skip;
1014
1015 if (xt->dst_sgl)
1016 dst_addr += dst_skip;
1017
1018 len += chunk->size;
1019 prev = desc;
1020 }
1021 }
1022
1023 first->tx_dma_desc.cookie = -EBUSY;
1024 first->tx_dma_desc.flags = flags;
1025 first->xfer_size = len;
1026
1027 return &first->tx_dma_desc;
1028 }
1029
1030 static struct dma_async_tx_descriptor *
at_xdmac_prep_dma_memcpy(struct dma_chan * chan,dma_addr_t dest,dma_addr_t src,size_t len,unsigned long flags)1031 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1032 size_t len, unsigned long flags)
1033 {
1034 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1035 struct at_xdmac_desc *first = NULL, *prev = NULL;
1036 size_t remaining_size = len, xfer_size = 0, ublen;
1037 dma_addr_t src_addr = src, dst_addr = dest;
1038 u32 dwidth;
1039 /*
1040 * WARNING: We don't know the direction, it involves we can't
1041 * dynamically set the source and dest interface so we have to use the
1042 * same one. Only interface 0 allows EBI access. Hopefully we can
1043 * access DDR through both ports (at least on SAMA5D4x), so we can use
1044 * the same interface for source and dest, that solves the fact we
1045 * don't know the direction.
1046 * ERRATA: Even if useless for memory transfers, the PERID has to not
1047 * match the one of another channel. If not, it could lead to spurious
1048 * flag status.
1049 */
1050 u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
1051 | AT_XDMAC_CC_DAM_INCREMENTED_AM
1052 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1053 | AT_XDMAC_CC_DIF(0)
1054 | AT_XDMAC_CC_SIF(0)
1055 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1056 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1057 unsigned long irqflags;
1058
1059 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
1060 __func__, &src, &dest, len, flags);
1061
1062 if (unlikely(!len))
1063 return NULL;
1064
1065 dwidth = at_xdmac_align_width(chan, src_addr | dst_addr);
1066
1067 /* Prepare descriptors. */
1068 while (remaining_size) {
1069 struct at_xdmac_desc *desc = NULL;
1070
1071 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
1072
1073 spin_lock_irqsave(&atchan->lock, irqflags);
1074 desc = at_xdmac_get_desc(atchan);
1075 spin_unlock_irqrestore(&atchan->lock, irqflags);
1076 if (!desc) {
1077 dev_err(chan2dev(chan), "can't get descriptor\n");
1078 if (first)
1079 list_splice_init(&first->descs_list, &atchan->free_descs_list);
1080 return NULL;
1081 }
1082
1083 /* Update src and dest addresses. */
1084 src_addr += xfer_size;
1085 dst_addr += xfer_size;
1086
1087 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
1088 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
1089 else
1090 xfer_size = remaining_size;
1091
1092 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
1093
1094 /* Check remaining length and change data width if needed. */
1095 dwidth = at_xdmac_align_width(chan,
1096 src_addr | dst_addr | xfer_size);
1097 chan_cc &= ~AT_XDMAC_CC_DWIDTH_MASK;
1098 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1099
1100 ublen = xfer_size >> dwidth;
1101 remaining_size -= xfer_size;
1102
1103 desc->lld.mbr_sa = src_addr;
1104 desc->lld.mbr_da = dst_addr;
1105 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
1106 | AT_XDMAC_MBR_UBC_NDEN
1107 | AT_XDMAC_MBR_UBC_NSEN
1108 | ublen;
1109 desc->lld.mbr_cfg = chan_cc;
1110
1111 dev_dbg(chan2dev(chan),
1112 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1113 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
1114
1115 /* Chain lld. */
1116 if (prev)
1117 at_xdmac_queue_desc(chan, prev, desc);
1118
1119 prev = desc;
1120 if (!first)
1121 first = desc;
1122
1123 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1124 __func__, desc, first);
1125 list_add_tail(&desc->desc_node, &first->descs_list);
1126 }
1127
1128 first->tx_dma_desc.flags = flags;
1129 first->xfer_size = len;
1130
1131 return &first->tx_dma_desc;
1132 }
1133
at_xdmac_memset_create_desc(struct dma_chan * chan,struct at_xdmac_chan * atchan,dma_addr_t dst_addr,size_t len,int value)1134 static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
1135 struct at_xdmac_chan *atchan,
1136 dma_addr_t dst_addr,
1137 size_t len,
1138 int value)
1139 {
1140 struct at_xdmac_desc *desc;
1141 unsigned long flags;
1142 size_t ublen;
1143 u32 dwidth;
1144 /*
1145 * WARNING: The channel configuration is set here since there is no
1146 * dmaengine_slave_config call in this case. Moreover we don't know the
1147 * direction, it involves we can't dynamically set the source and dest
1148 * interface so we have to use the same one. Only interface 0 allows EBI
1149 * access. Hopefully we can access DDR through both ports (at least on
1150 * SAMA5D4x), so we can use the same interface for source and dest,
1151 * that solves the fact we don't know the direction.
1152 * ERRATA: Even if useless for memory transfers, the PERID has to not
1153 * match the one of another channel. If not, it could lead to spurious
1154 * flag status.
1155 */
1156 u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
1157 | AT_XDMAC_CC_DAM_UBS_AM
1158 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1159 | AT_XDMAC_CC_DIF(0)
1160 | AT_XDMAC_CC_SIF(0)
1161 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1162 | AT_XDMAC_CC_MEMSET_HW_MODE
1163 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1164
1165 dwidth = at_xdmac_align_width(chan, dst_addr);
1166
1167 if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
1168 dev_err(chan2dev(chan),
1169 "%s: Transfer too large, aborting...\n",
1170 __func__);
1171 return NULL;
1172 }
1173
1174 spin_lock_irqsave(&atchan->lock, flags);
1175 desc = at_xdmac_get_desc(atchan);
1176 spin_unlock_irqrestore(&atchan->lock, flags);
1177 if (!desc) {
1178 dev_err(chan2dev(chan), "can't get descriptor\n");
1179 return NULL;
1180 }
1181
1182 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1183
1184 ublen = len >> dwidth;
1185
1186 desc->lld.mbr_da = dst_addr;
1187 desc->lld.mbr_ds = value;
1188 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
1189 | AT_XDMAC_MBR_UBC_NDEN
1190 | AT_XDMAC_MBR_UBC_NSEN
1191 | ublen;
1192 desc->lld.mbr_cfg = chan_cc;
1193
1194 dev_dbg(chan2dev(chan),
1195 "%s: lld: mbr_da=%pad, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1196 __func__, &desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc,
1197 desc->lld.mbr_cfg);
1198
1199 return desc;
1200 }
1201
1202 static struct dma_async_tx_descriptor *
at_xdmac_prep_dma_memset(struct dma_chan * chan,dma_addr_t dest,int value,size_t len,unsigned long flags)1203 at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
1204 size_t len, unsigned long flags)
1205 {
1206 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1207 struct at_xdmac_desc *desc;
1208
1209 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%zu, pattern=0x%x, flags=0x%lx\n",
1210 __func__, &dest, len, value, flags);
1211
1212 if (unlikely(!len))
1213 return NULL;
1214
1215 desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value);
1216 list_add_tail(&desc->desc_node, &desc->descs_list);
1217
1218 desc->tx_dma_desc.cookie = -EBUSY;
1219 desc->tx_dma_desc.flags = flags;
1220 desc->xfer_size = len;
1221
1222 return &desc->tx_dma_desc;
1223 }
1224
1225 static struct dma_async_tx_descriptor *
at_xdmac_prep_dma_memset_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,int value,unsigned long flags)1226 at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl,
1227 unsigned int sg_len, int value,
1228 unsigned long flags)
1229 {
1230 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1231 struct at_xdmac_desc *desc, *pdesc = NULL,
1232 *ppdesc = NULL, *first = NULL;
1233 struct scatterlist *sg, *psg = NULL, *ppsg = NULL;
1234 size_t stride = 0, pstride = 0, len = 0;
1235 int i;
1236
1237 if (!sgl)
1238 return NULL;
1239
1240 dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n",
1241 __func__, sg_len, value, flags);
1242
1243 /* Prepare descriptors. */
1244 for_each_sg(sgl, sg, sg_len, i) {
1245 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n",
1246 __func__, &sg_dma_address(sg), sg_dma_len(sg),
1247 value, flags);
1248 desc = at_xdmac_memset_create_desc(chan, atchan,
1249 sg_dma_address(sg),
1250 sg_dma_len(sg),
1251 value);
1252 if (!desc && first)
1253 list_splice_init(&first->descs_list,
1254 &atchan->free_descs_list);
1255
1256 if (!first)
1257 first = desc;
1258
1259 /* Update our strides */
1260 pstride = stride;
1261 if (psg)
1262 stride = sg_dma_address(sg) -
1263 (sg_dma_address(psg) + sg_dma_len(psg));
1264
1265 /*
1266 * The scatterlist API gives us only the address and
1267 * length of each elements.
1268 *
1269 * Unfortunately, we don't have the stride, which we
1270 * will need to compute.
1271 *
1272 * That make us end up in a situation like this one:
1273 * len stride len stride len
1274 * +-------+ +-------+ +-------+
1275 * | N-2 | | N-1 | | N |
1276 * +-------+ +-------+ +-------+
1277 *
1278 * We need all these three elements (N-2, N-1 and N)
1279 * to actually take the decision on whether we need to
1280 * queue N-1 or reuse N-2.
1281 *
1282 * We will only consider N if it is the last element.
1283 */
1284 if (ppdesc && pdesc) {
1285 if ((stride == pstride) &&
1286 (sg_dma_len(ppsg) == sg_dma_len(psg))) {
1287 dev_dbg(chan2dev(chan),
1288 "%s: desc 0x%p can be merged with desc 0x%p\n",
1289 __func__, pdesc, ppdesc);
1290
1291 /*
1292 * Increment the block count of the
1293 * N-2 descriptor
1294 */
1295 at_xdmac_increment_block_count(chan, ppdesc);
1296 ppdesc->lld.mbr_dus = stride;
1297
1298 /*
1299 * Put back the N-1 descriptor in the
1300 * free descriptor list
1301 */
1302 list_add_tail(&pdesc->desc_node,
1303 &atchan->free_descs_list);
1304
1305 /*
1306 * Make our N-1 descriptor pointer
1307 * point to the N-2 since they were
1308 * actually merged.
1309 */
1310 pdesc = ppdesc;
1311
1312 /*
1313 * Rule out the case where we don't have
1314 * pstride computed yet (our second sg
1315 * element)
1316 *
1317 * We also want to catch the case where there
1318 * would be a negative stride,
1319 */
1320 } else if (pstride ||
1321 sg_dma_address(sg) < sg_dma_address(psg)) {
1322 /*
1323 * Queue the N-1 descriptor after the
1324 * N-2
1325 */
1326 at_xdmac_queue_desc(chan, ppdesc, pdesc);
1327
1328 /*
1329 * Add the N-1 descriptor to the list
1330 * of the descriptors used for this
1331 * transfer
1332 */
1333 list_add_tail(&desc->desc_node,
1334 &first->descs_list);
1335 dev_dbg(chan2dev(chan),
1336 "%s: add desc 0x%p to descs_list 0x%p\n",
1337 __func__, desc, first);
1338 }
1339 }
1340
1341 /*
1342 * If we are the last element, just see if we have the
1343 * same size than the previous element.
1344 *
1345 * If so, we can merge it with the previous descriptor
1346 * since we don't care about the stride anymore.
1347 */
1348 if ((i == (sg_len - 1)) &&
1349 sg_dma_len(psg) == sg_dma_len(sg)) {
1350 dev_dbg(chan2dev(chan),
1351 "%s: desc 0x%p can be merged with desc 0x%p\n",
1352 __func__, desc, pdesc);
1353
1354 /*
1355 * Increment the block count of the N-1
1356 * descriptor
1357 */
1358 at_xdmac_increment_block_count(chan, pdesc);
1359 pdesc->lld.mbr_dus = stride;
1360
1361 /*
1362 * Put back the N descriptor in the free
1363 * descriptor list
1364 */
1365 list_add_tail(&desc->desc_node,
1366 &atchan->free_descs_list);
1367 }
1368
1369 /* Update our descriptors */
1370 ppdesc = pdesc;
1371 pdesc = desc;
1372
1373 /* Update our scatter pointers */
1374 ppsg = psg;
1375 psg = sg;
1376
1377 len += sg_dma_len(sg);
1378 }
1379
1380 first->tx_dma_desc.cookie = -EBUSY;
1381 first->tx_dma_desc.flags = flags;
1382 first->xfer_size = len;
1383
1384 return &first->tx_dma_desc;
1385 }
1386
1387 static enum dma_status
at_xdmac_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)1388 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1389 struct dma_tx_state *txstate)
1390 {
1391 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1392 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1393 struct at_xdmac_desc *desc, *_desc, *iter;
1394 struct list_head *descs_list;
1395 enum dma_status ret;
1396 int residue, retry;
1397 u32 cur_nda, check_nda, cur_ubc, mask, value;
1398 u8 dwidth = 0;
1399 unsigned long flags;
1400 bool initd;
1401
1402 ret = dma_cookie_status(chan, cookie, txstate);
1403 if (ret == DMA_COMPLETE)
1404 return ret;
1405
1406 if (!txstate)
1407 return ret;
1408
1409 spin_lock_irqsave(&atchan->lock, flags);
1410
1411 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1412
1413 /*
1414 * If the transfer has not been started yet, don't need to compute the
1415 * residue, it's the transfer length.
1416 */
1417 if (!desc->active_xfer) {
1418 dma_set_residue(txstate, desc->xfer_size);
1419 goto spin_unlock;
1420 }
1421
1422 residue = desc->xfer_size;
1423 /*
1424 * Flush FIFO: only relevant when the transfer is source peripheral
1425 * synchronized. Flush is needed before reading CUBC because data in
1426 * the FIFO are not reported by CUBC. Reporting a residue of the
1427 * transfer length while we have data in FIFO can cause issue.
1428 * Usecase: atmel USART has a timeout which means I have received
1429 * characters but there is no more character received for a while. On
1430 * timeout, it requests the residue. If the data are in the DMA FIFO,
1431 * we will return a residue of the transfer length. It means no data
1432 * received. If an application is waiting for these data, it will hang
1433 * since we won't have another USART timeout without receiving new
1434 * data.
1435 */
1436 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
1437 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
1438 if ((desc->lld.mbr_cfg & mask) == value) {
1439 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
1440 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1441 cpu_relax();
1442 }
1443
1444 /*
1445 * The easiest way to compute the residue should be to pause the DMA
1446 * but doing this can lead to miss some data as some devices don't
1447 * have FIFO.
1448 * We need to read several registers because:
1449 * - DMA is running therefore a descriptor change is possible while
1450 * reading these registers
1451 * - When the block transfer is done, the value of the CUBC register
1452 * is set to its initial value until the fetch of the next descriptor.
1453 * This value will corrupt the residue calculation so we have to skip
1454 * it.
1455 *
1456 * INITD -------- ------------
1457 * |____________________|
1458 * _______________________ _______________
1459 * NDA @desc2 \/ @desc3
1460 * _______________________/\_______________
1461 * __________ ___________ _______________
1462 * CUBC 0 \/ MAX desc1 \/ MAX desc2
1463 * __________/\___________/\_______________
1464 *
1465 * Since descriptors are aligned on 64 bits, we can assume that
1466 * the update of NDA and CUBC is atomic.
1467 * Memory barriers are used to ensure the read order of the registers.
1468 * A max number of retries is set because unlikely it could never ends.
1469 */
1470 for (retry = 0; retry < AT_XDMAC_RESIDUE_MAX_RETRIES; retry++) {
1471 check_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1472 rmb();
1473 cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC);
1474 rmb();
1475 initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD);
1476 rmb();
1477 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1478 rmb();
1479
1480 if ((check_nda == cur_nda) && initd)
1481 break;
1482 }
1483
1484 if (unlikely(retry >= AT_XDMAC_RESIDUE_MAX_RETRIES)) {
1485 ret = DMA_ERROR;
1486 goto spin_unlock;
1487 }
1488
1489 /*
1490 * Flush FIFO: only relevant when the transfer is source peripheral
1491 * synchronized. Another flush is needed here because CUBC is updated
1492 * when the controller sends the data write command. It can lead to
1493 * report data that are not written in the memory or the device. The
1494 * FIFO flush ensures that data are really written.
1495 */
1496 if ((desc->lld.mbr_cfg & mask) == value) {
1497 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
1498 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1499 cpu_relax();
1500 }
1501
1502 /*
1503 * Remove size of all microblocks already transferred and the current
1504 * one. Then add the remaining size to transfer of the current
1505 * microblock.
1506 */
1507 descs_list = &desc->descs_list;
1508 list_for_each_entry_safe(iter, _desc, descs_list, desc_node) {
1509 dwidth = at_xdmac_get_dwidth(iter->lld.mbr_cfg);
1510 residue -= (iter->lld.mbr_ubc & 0xffffff) << dwidth;
1511 if ((iter->lld.mbr_nda & 0xfffffffc) == cur_nda) {
1512 desc = iter;
1513 break;
1514 }
1515 }
1516 residue += cur_ubc << dwidth;
1517
1518 dma_set_residue(txstate, residue);
1519
1520 dev_dbg(chan2dev(chan),
1521 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
1522 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
1523
1524 spin_unlock:
1525 spin_unlock_irqrestore(&atchan->lock, flags);
1526 return ret;
1527 }
1528
1529 /* Call must be protected by lock. */
at_xdmac_remove_xfer(struct at_xdmac_chan * atchan,struct at_xdmac_desc * desc)1530 static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
1531 struct at_xdmac_desc *desc)
1532 {
1533 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1534
1535 /*
1536 * Remove the transfer from the transfer list then move the transfer
1537 * descriptors into the free descriptors list.
1538 */
1539 list_del(&desc->xfer_node);
1540 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
1541 }
1542
at_xdmac_advance_work(struct at_xdmac_chan * atchan)1543 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
1544 {
1545 struct at_xdmac_desc *desc;
1546
1547 /*
1548 * If channel is enabled, do nothing, advance_work will be triggered
1549 * after the interruption.
1550 */
1551 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
1552 desc = list_first_entry(&atchan->xfers_list,
1553 struct at_xdmac_desc,
1554 xfer_node);
1555 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1556 if (!desc->active_xfer)
1557 at_xdmac_start_xfer(atchan, desc);
1558 }
1559 }
1560
at_xdmac_handle_cyclic(struct at_xdmac_chan * atchan)1561 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
1562 {
1563 struct at_xdmac_desc *desc;
1564 struct dma_async_tx_descriptor *txd;
1565
1566 spin_lock_irq(&atchan->lock);
1567 if (list_empty(&atchan->xfers_list)) {
1568 spin_unlock_irq(&atchan->lock);
1569 return;
1570 }
1571 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc,
1572 xfer_node);
1573 spin_unlock_irq(&atchan->lock);
1574 txd = &desc->tx_dma_desc;
1575 if (txd->flags & DMA_PREP_INTERRUPT)
1576 dmaengine_desc_get_callback_invoke(txd, NULL);
1577 }
1578
at_xdmac_handle_error(struct at_xdmac_chan * atchan)1579 static void at_xdmac_handle_error(struct at_xdmac_chan *atchan)
1580 {
1581 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1582 struct at_xdmac_desc *bad_desc;
1583
1584 /*
1585 * The descriptor currently at the head of the active list is
1586 * broken. Since we don't have any way to report errors, we'll
1587 * just have to scream loudly and try to continue with other
1588 * descriptors queued (if any).
1589 */
1590 if (atchan->irq_status & AT_XDMAC_CIS_RBEIS)
1591 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1592 if (atchan->irq_status & AT_XDMAC_CIS_WBEIS)
1593 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1594 if (atchan->irq_status & AT_XDMAC_CIS_ROIS)
1595 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1596
1597 spin_lock_irq(&atchan->lock);
1598
1599 /* Channel must be disabled first as it's not done automatically */
1600 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1601 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1602 cpu_relax();
1603
1604 bad_desc = list_first_entry(&atchan->xfers_list,
1605 struct at_xdmac_desc,
1606 xfer_node);
1607
1608 spin_unlock_irq(&atchan->lock);
1609
1610 /* Print bad descriptor's details if needed */
1611 dev_dbg(chan2dev(&atchan->chan),
1612 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
1613 __func__, &bad_desc->lld.mbr_sa, &bad_desc->lld.mbr_da,
1614 bad_desc->lld.mbr_ubc);
1615
1616 /* Then continue with usual descriptor management */
1617 }
1618
at_xdmac_tasklet(struct tasklet_struct * t)1619 static void at_xdmac_tasklet(struct tasklet_struct *t)
1620 {
1621 struct at_xdmac_chan *atchan = from_tasklet(atchan, t, tasklet);
1622 struct at_xdmac_desc *desc;
1623 u32 error_mask;
1624
1625 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08x\n",
1626 __func__, atchan->irq_status);
1627
1628 error_mask = AT_XDMAC_CIS_RBEIS
1629 | AT_XDMAC_CIS_WBEIS
1630 | AT_XDMAC_CIS_ROIS;
1631
1632 if (at_xdmac_chan_is_cyclic(atchan)) {
1633 at_xdmac_handle_cyclic(atchan);
1634 } else if ((atchan->irq_status & AT_XDMAC_CIS_LIS)
1635 || (atchan->irq_status & error_mask)) {
1636 struct dma_async_tx_descriptor *txd;
1637
1638 if (atchan->irq_status & error_mask)
1639 at_xdmac_handle_error(atchan);
1640
1641 spin_lock_irq(&atchan->lock);
1642 desc = list_first_entry(&atchan->xfers_list,
1643 struct at_xdmac_desc,
1644 xfer_node);
1645 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1646 if (!desc->active_xfer) {
1647 dev_err(chan2dev(&atchan->chan), "Xfer not active: exiting");
1648 spin_unlock_irq(&atchan->lock);
1649 return;
1650 }
1651
1652 txd = &desc->tx_dma_desc;
1653
1654 at_xdmac_remove_xfer(atchan, desc);
1655 spin_unlock_irq(&atchan->lock);
1656
1657 dma_cookie_complete(txd);
1658 if (txd->flags & DMA_PREP_INTERRUPT)
1659 dmaengine_desc_get_callback_invoke(txd, NULL);
1660
1661 dma_run_dependencies(txd);
1662
1663 spin_lock_irq(&atchan->lock);
1664 at_xdmac_advance_work(atchan);
1665 spin_unlock_irq(&atchan->lock);
1666 }
1667 }
1668
at_xdmac_interrupt(int irq,void * dev_id)1669 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1670 {
1671 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1672 struct at_xdmac_chan *atchan;
1673 u32 imr, status, pending;
1674 u32 chan_imr, chan_status;
1675 int i, ret = IRQ_NONE;
1676
1677 do {
1678 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1679 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1680 pending = status & imr;
1681
1682 dev_vdbg(atxdmac->dma.dev,
1683 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1684 __func__, status, imr, pending);
1685
1686 if (!pending)
1687 break;
1688
1689 /* We have to find which channel has generated the interrupt. */
1690 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1691 if (!((1 << i) & pending))
1692 continue;
1693
1694 atchan = &atxdmac->chan[i];
1695 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1696 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1697 atchan->irq_status = chan_status & chan_imr;
1698 dev_vdbg(atxdmac->dma.dev,
1699 "%s: chan%d: imr=0x%x, status=0x%x\n",
1700 __func__, i, chan_imr, chan_status);
1701 dev_vdbg(chan2dev(&atchan->chan),
1702 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1703 __func__,
1704 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1705 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1706 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1707 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1708 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1709 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1710
1711 if (atchan->irq_status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1712 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1713
1714 tasklet_schedule(&atchan->tasklet);
1715 ret = IRQ_HANDLED;
1716 }
1717
1718 } while (pending);
1719
1720 return ret;
1721 }
1722
at_xdmac_issue_pending(struct dma_chan * chan)1723 static void at_xdmac_issue_pending(struct dma_chan *chan)
1724 {
1725 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1726 unsigned long flags;
1727
1728 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1729
1730 spin_lock_irqsave(&atchan->lock, flags);
1731 at_xdmac_advance_work(atchan);
1732 spin_unlock_irqrestore(&atchan->lock, flags);
1733
1734 return;
1735 }
1736
at_xdmac_device_config(struct dma_chan * chan,struct dma_slave_config * config)1737 static int at_xdmac_device_config(struct dma_chan *chan,
1738 struct dma_slave_config *config)
1739 {
1740 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1741 int ret;
1742 unsigned long flags;
1743
1744 dev_dbg(chan2dev(chan), "%s\n", __func__);
1745
1746 spin_lock_irqsave(&atchan->lock, flags);
1747 ret = at_xdmac_set_slave_config(chan, config);
1748 spin_unlock_irqrestore(&atchan->lock, flags);
1749
1750 return ret;
1751 }
1752
at_xdmac_device_pause(struct dma_chan * chan)1753 static int at_xdmac_device_pause(struct dma_chan *chan)
1754 {
1755 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1756 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1757 unsigned long flags;
1758
1759 dev_dbg(chan2dev(chan), "%s\n", __func__);
1760
1761 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1762 return 0;
1763
1764 spin_lock_irqsave(&atchan->lock, flags);
1765 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
1766 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1767 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1768 cpu_relax();
1769 spin_unlock_irqrestore(&atchan->lock, flags);
1770
1771 return 0;
1772 }
1773
at_xdmac_device_resume(struct dma_chan * chan)1774 static int at_xdmac_device_resume(struct dma_chan *chan)
1775 {
1776 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1777 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1778 unsigned long flags;
1779
1780 dev_dbg(chan2dev(chan), "%s\n", __func__);
1781
1782 spin_lock_irqsave(&atchan->lock, flags);
1783 if (!at_xdmac_chan_is_paused(atchan)) {
1784 spin_unlock_irqrestore(&atchan->lock, flags);
1785 return 0;
1786 }
1787
1788 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1789 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1790 spin_unlock_irqrestore(&atchan->lock, flags);
1791
1792 return 0;
1793 }
1794
at_xdmac_device_terminate_all(struct dma_chan * chan)1795 static int at_xdmac_device_terminate_all(struct dma_chan *chan)
1796 {
1797 struct at_xdmac_desc *desc, *_desc;
1798 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1799 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1800 unsigned long flags;
1801
1802 dev_dbg(chan2dev(chan), "%s\n", __func__);
1803
1804 spin_lock_irqsave(&atchan->lock, flags);
1805 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1806 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1807 cpu_relax();
1808
1809 /* Cancel all pending transfers. */
1810 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1811 at_xdmac_remove_xfer(atchan, desc);
1812
1813 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1814 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1815 spin_unlock_irqrestore(&atchan->lock, flags);
1816
1817 return 0;
1818 }
1819
at_xdmac_alloc_chan_resources(struct dma_chan * chan)1820 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1821 {
1822 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1823 struct at_xdmac_desc *desc;
1824 int i;
1825
1826 if (at_xdmac_chan_is_enabled(atchan)) {
1827 dev_err(chan2dev(chan),
1828 "can't allocate channel resources (channel enabled)\n");
1829 return -EIO;
1830 }
1831
1832 if (!list_empty(&atchan->free_descs_list)) {
1833 dev_err(chan2dev(chan),
1834 "can't allocate channel resources (channel not free from a previous use)\n");
1835 return -EIO;
1836 }
1837
1838 for (i = 0; i < init_nr_desc_per_channel; i++) {
1839 desc = at_xdmac_alloc_desc(chan, GFP_KERNEL);
1840 if (!desc) {
1841 if (i == 0) {
1842 dev_warn(chan2dev(chan),
1843 "can't allocate any descriptors\n");
1844 return -EIO;
1845 }
1846 dev_warn(chan2dev(chan),
1847 "only %d descriptors have been allocated\n", i);
1848 break;
1849 }
1850 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1851 }
1852
1853 dma_cookie_init(chan);
1854
1855 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1856
1857 return i;
1858 }
1859
at_xdmac_free_chan_resources(struct dma_chan * chan)1860 static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1861 {
1862 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1863 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1864 struct at_xdmac_desc *desc, *_desc;
1865
1866 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1867 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1868 list_del(&desc->desc_node);
1869 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1870 }
1871
1872 return;
1873 }
1874
1875 #ifdef CONFIG_PM
atmel_xdmac_prepare(struct device * dev)1876 static int atmel_xdmac_prepare(struct device *dev)
1877 {
1878 struct at_xdmac *atxdmac = dev_get_drvdata(dev);
1879 struct dma_chan *chan, *_chan;
1880
1881 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1882 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1883
1884 /* Wait for transfer completion, except in cyclic case. */
1885 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1886 return -EAGAIN;
1887 }
1888 return 0;
1889 }
1890 #else
1891 # define atmel_xdmac_prepare NULL
1892 #endif
1893
1894 #ifdef CONFIG_PM_SLEEP
atmel_xdmac_suspend(struct device * dev)1895 static int atmel_xdmac_suspend(struct device *dev)
1896 {
1897 struct at_xdmac *atxdmac = dev_get_drvdata(dev);
1898 struct dma_chan *chan, *_chan;
1899
1900 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1901 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1902
1903 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
1904 if (at_xdmac_chan_is_cyclic(atchan)) {
1905 if (!at_xdmac_chan_is_paused(atchan))
1906 at_xdmac_device_pause(chan);
1907 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1908 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1909 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1910 }
1911 }
1912 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1913
1914 at_xdmac_off(atxdmac);
1915 clk_disable_unprepare(atxdmac->clk);
1916 return 0;
1917 }
1918
atmel_xdmac_resume(struct device * dev)1919 static int atmel_xdmac_resume(struct device *dev)
1920 {
1921 struct at_xdmac *atxdmac = dev_get_drvdata(dev);
1922 struct at_xdmac_chan *atchan;
1923 struct dma_chan *chan, *_chan;
1924 int i;
1925 int ret;
1926
1927 ret = clk_prepare_enable(atxdmac->clk);
1928 if (ret)
1929 return ret;
1930
1931 /* Clear pending interrupts. */
1932 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1933 atchan = &atxdmac->chan[i];
1934 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1935 cpu_relax();
1936 }
1937
1938 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1939 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1940 atchan = to_at_xdmac_chan(chan);
1941 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
1942 if (at_xdmac_chan_is_cyclic(atchan)) {
1943 if (at_xdmac_chan_is_paused(atchan))
1944 at_xdmac_device_resume(chan);
1945 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1946 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1947 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1948 wmb();
1949 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1950 }
1951 }
1952 return 0;
1953 }
1954 #endif /* CONFIG_PM_SLEEP */
1955
at_xdmac_probe(struct platform_device * pdev)1956 static int at_xdmac_probe(struct platform_device *pdev)
1957 {
1958 struct at_xdmac *atxdmac;
1959 int irq, size, nr_channels, i, ret;
1960 void __iomem *base;
1961 u32 reg;
1962
1963 irq = platform_get_irq(pdev, 0);
1964 if (irq < 0)
1965 return irq;
1966
1967 base = devm_platform_ioremap_resource(pdev, 0);
1968 if (IS_ERR(base))
1969 return PTR_ERR(base);
1970
1971 /*
1972 * Read number of xdmac channels, read helper function can't be used
1973 * since atxdmac is not yet allocated and we need to know the number
1974 * of channels to do the allocation.
1975 */
1976 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1977 nr_channels = AT_XDMAC_NB_CH(reg);
1978 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1979 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1980 nr_channels);
1981 return -EINVAL;
1982 }
1983
1984 size = sizeof(*atxdmac);
1985 size += nr_channels * sizeof(struct at_xdmac_chan);
1986 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1987 if (!atxdmac) {
1988 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1989 return -ENOMEM;
1990 }
1991
1992 atxdmac->regs = base;
1993 atxdmac->irq = irq;
1994
1995 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1996 if (IS_ERR(atxdmac->clk)) {
1997 dev_err(&pdev->dev, "can't get dma_clk\n");
1998 return PTR_ERR(atxdmac->clk);
1999 }
2000
2001 /* Do not use dev res to prevent races with tasklet */
2002 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
2003 if (ret) {
2004 dev_err(&pdev->dev, "can't request irq\n");
2005 return ret;
2006 }
2007
2008 ret = clk_prepare_enable(atxdmac->clk);
2009 if (ret) {
2010 dev_err(&pdev->dev, "can't prepare or enable clock\n");
2011 goto err_free_irq;
2012 }
2013
2014 atxdmac->at_xdmac_desc_pool =
2015 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
2016 sizeof(struct at_xdmac_desc), 4, 0);
2017 if (!atxdmac->at_xdmac_desc_pool) {
2018 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
2019 ret = -ENOMEM;
2020 goto err_clk_disable;
2021 }
2022
2023 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
2024 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
2025 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
2026 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
2027 dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask);
2028 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
2029 /*
2030 * Without DMA_PRIVATE the driver is not able to allocate more than
2031 * one channel, second allocation fails in private_candidate.
2032 */
2033 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
2034 atxdmac->dma.dev = &pdev->dev;
2035 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
2036 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
2037 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
2038 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
2039 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
2040 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
2041 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
2042 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
2043 atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg;
2044 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
2045 atxdmac->dma.device_config = at_xdmac_device_config;
2046 atxdmac->dma.device_pause = at_xdmac_device_pause;
2047 atxdmac->dma.device_resume = at_xdmac_device_resume;
2048 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
2049 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2050 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2051 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2052 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2053
2054 /* Disable all chans and interrupts. */
2055 at_xdmac_off(atxdmac);
2056
2057 /* Init channels. */
2058 INIT_LIST_HEAD(&atxdmac->dma.channels);
2059 for (i = 0; i < nr_channels; i++) {
2060 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2061
2062 atchan->chan.device = &atxdmac->dma;
2063 list_add_tail(&atchan->chan.device_node,
2064 &atxdmac->dma.channels);
2065
2066 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
2067 atchan->mask = 1 << i;
2068
2069 spin_lock_init(&atchan->lock);
2070 INIT_LIST_HEAD(&atchan->xfers_list);
2071 INIT_LIST_HEAD(&atchan->free_descs_list);
2072 tasklet_setup(&atchan->tasklet, at_xdmac_tasklet);
2073
2074 /* Clear pending interrupts. */
2075 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
2076 cpu_relax();
2077 }
2078 platform_set_drvdata(pdev, atxdmac);
2079
2080 ret = dma_async_device_register(&atxdmac->dma);
2081 if (ret) {
2082 dev_err(&pdev->dev, "fail to register DMA engine device\n");
2083 goto err_clk_disable;
2084 }
2085
2086 ret = of_dma_controller_register(pdev->dev.of_node,
2087 at_xdmac_xlate, atxdmac);
2088 if (ret) {
2089 dev_err(&pdev->dev, "could not register of dma controller\n");
2090 goto err_dma_unregister;
2091 }
2092
2093 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
2094 nr_channels, atxdmac->regs);
2095
2096 return 0;
2097
2098 err_dma_unregister:
2099 dma_async_device_unregister(&atxdmac->dma);
2100 err_clk_disable:
2101 clk_disable_unprepare(atxdmac->clk);
2102 err_free_irq:
2103 free_irq(atxdmac->irq, atxdmac);
2104 return ret;
2105 }
2106
at_xdmac_remove(struct platform_device * pdev)2107 static int at_xdmac_remove(struct platform_device *pdev)
2108 {
2109 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
2110 int i;
2111
2112 at_xdmac_off(atxdmac);
2113 of_dma_controller_free(pdev->dev.of_node);
2114 dma_async_device_unregister(&atxdmac->dma);
2115 clk_disable_unprepare(atxdmac->clk);
2116
2117 free_irq(atxdmac->irq, atxdmac);
2118
2119 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2120 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2121
2122 tasklet_kill(&atchan->tasklet);
2123 at_xdmac_free_chan_resources(&atchan->chan);
2124 }
2125
2126 return 0;
2127 }
2128
2129 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
2130 .prepare = atmel_xdmac_prepare,
2131 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
2132 };
2133
2134 static const struct of_device_id atmel_xdmac_dt_ids[] = {
2135 {
2136 .compatible = "atmel,sama5d4-dma",
2137 }, {
2138 /* sentinel */
2139 }
2140 };
2141 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
2142
2143 static struct platform_driver at_xdmac_driver = {
2144 .probe = at_xdmac_probe,
2145 .remove = at_xdmac_remove,
2146 .driver = {
2147 .name = "at_xdmac",
2148 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
2149 .pm = &atmel_xdmac_dev_pm_ops,
2150 }
2151 };
2152
at_xdmac_init(void)2153 static int __init at_xdmac_init(void)
2154 {
2155 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
2156 }
2157 subsys_initcall(at_xdmac_init);
2158
2159 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
2160 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
2161 MODULE_LICENSE("GPL");
2162