1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // drivers/dma/imx-dma.c
4 //
5 // This file contains a driver for the Freescale i.MX DMA engine
6 // found on i.MX1/21/27
7 //
8 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
9 // Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
10
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/mm.h>
15 #include <linux/interrupt.h>
16 #include <linux/spinlock.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/dmaengine.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/of_dma.h>
26
27 #include <asm/irq.h>
28 #include <linux/platform_data/dma-imx.h>
29
30 #include "dmaengine.h"
31 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
32 #define IMX_DMA_CHANNELS 16
33
34 #define IMX_DMA_2D_SLOTS 2
35 #define IMX_DMA_2D_SLOT_A 0
36 #define IMX_DMA_2D_SLOT_B 1
37
38 #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
39 #define IMX_DMA_MEMSIZE_32 (0 << 4)
40 #define IMX_DMA_MEMSIZE_8 (1 << 4)
41 #define IMX_DMA_MEMSIZE_16 (2 << 4)
42 #define IMX_DMA_TYPE_LINEAR (0 << 10)
43 #define IMX_DMA_TYPE_2D (1 << 10)
44 #define IMX_DMA_TYPE_FIFO (2 << 10)
45
46 #define IMX_DMA_ERR_BURST (1 << 0)
47 #define IMX_DMA_ERR_REQUEST (1 << 1)
48 #define IMX_DMA_ERR_TRANSFER (1 << 2)
49 #define IMX_DMA_ERR_BUFFER (1 << 3)
50 #define IMX_DMA_ERR_TIMEOUT (1 << 4)
51
52 #define DMA_DCR 0x00 /* Control Register */
53 #define DMA_DISR 0x04 /* Interrupt status Register */
54 #define DMA_DIMR 0x08 /* Interrupt mask Register */
55 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
56 #define DMA_DRTOSR 0x10 /* Request timeout Register */
57 #define DMA_DSESR 0x14 /* Transfer Error Status Register */
58 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
59 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
60 #define DMA_WSRA 0x40 /* W-Size Register A */
61 #define DMA_XSRA 0x44 /* X-Size Register A */
62 #define DMA_YSRA 0x48 /* Y-Size Register A */
63 #define DMA_WSRB 0x4c /* W-Size Register B */
64 #define DMA_XSRB 0x50 /* X-Size Register B */
65 #define DMA_YSRB 0x54 /* Y-Size Register B */
66 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
67 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
68 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
69 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
70 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
71 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
72 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
73 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
74 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
75
76 #define DCR_DRST (1<<1)
77 #define DCR_DEN (1<<0)
78 #define DBTOCR_EN (1<<15)
79 #define DBTOCR_CNT(x) ((x) & 0x7fff)
80 #define CNTR_CNT(x) ((x) & 0xffffff)
81 #define CCR_ACRPT (1<<14)
82 #define CCR_DMOD_LINEAR (0x0 << 12)
83 #define CCR_DMOD_2D (0x1 << 12)
84 #define CCR_DMOD_FIFO (0x2 << 12)
85 #define CCR_DMOD_EOBFIFO (0x3 << 12)
86 #define CCR_SMOD_LINEAR (0x0 << 10)
87 #define CCR_SMOD_2D (0x1 << 10)
88 #define CCR_SMOD_FIFO (0x2 << 10)
89 #define CCR_SMOD_EOBFIFO (0x3 << 10)
90 #define CCR_MDIR_DEC (1<<9)
91 #define CCR_MSEL_B (1<<8)
92 #define CCR_DSIZ_32 (0x0 << 6)
93 #define CCR_DSIZ_8 (0x1 << 6)
94 #define CCR_DSIZ_16 (0x2 << 6)
95 #define CCR_SSIZ_32 (0x0 << 4)
96 #define CCR_SSIZ_8 (0x1 << 4)
97 #define CCR_SSIZ_16 (0x2 << 4)
98 #define CCR_REN (1<<3)
99 #define CCR_RPT (1<<2)
100 #define CCR_FRC (1<<1)
101 #define CCR_CEN (1<<0)
102 #define RTOR_EN (1<<15)
103 #define RTOR_CLK (1<<14)
104 #define RTOR_PSC (1<<13)
105
106 enum imxdma_prep_type {
107 IMXDMA_DESC_MEMCPY,
108 IMXDMA_DESC_INTERLEAVED,
109 IMXDMA_DESC_SLAVE_SG,
110 IMXDMA_DESC_CYCLIC,
111 };
112
113 struct imx_dma_2d_config {
114 u16 xsr;
115 u16 ysr;
116 u16 wsr;
117 int count;
118 };
119
120 struct imxdma_desc {
121 struct list_head node;
122 struct dma_async_tx_descriptor desc;
123 enum dma_status status;
124 dma_addr_t src;
125 dma_addr_t dest;
126 size_t len;
127 enum dma_transfer_direction direction;
128 enum imxdma_prep_type type;
129 /* For memcpy and interleaved */
130 unsigned int config_port;
131 unsigned int config_mem;
132 /* For interleaved transfers */
133 unsigned int x;
134 unsigned int y;
135 unsigned int w;
136 /* For slave sg and cyclic */
137 struct scatterlist *sg;
138 unsigned int sgcount;
139 };
140
141 struct imxdma_channel {
142 int hw_chaining;
143 struct timer_list watchdog;
144 struct imxdma_engine *imxdma;
145 unsigned int channel;
146
147 struct tasklet_struct dma_tasklet;
148 struct list_head ld_free;
149 struct list_head ld_queue;
150 struct list_head ld_active;
151 int descs_allocated;
152 enum dma_slave_buswidth word_size;
153 dma_addr_t per_address;
154 u32 watermark_level;
155 struct dma_chan chan;
156 struct dma_async_tx_descriptor desc;
157 enum dma_status status;
158 int dma_request;
159 struct scatterlist *sg_list;
160 u32 ccr_from_device;
161 u32 ccr_to_device;
162 bool enabled_2d;
163 int slot_2d;
164 unsigned int irq;
165 struct dma_slave_config config;
166 };
167
168 enum imx_dma_type {
169 IMX1_DMA,
170 IMX21_DMA,
171 IMX27_DMA,
172 };
173
174 struct imxdma_engine {
175 struct device *dev;
176 struct dma_device dma_device;
177 void __iomem *base;
178 struct clk *dma_ahb;
179 struct clk *dma_ipg;
180 spinlock_t lock;
181 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
182 struct imxdma_channel channel[IMX_DMA_CHANNELS];
183 enum imx_dma_type devtype;
184 unsigned int irq;
185 unsigned int irq_err;
186
187 };
188
189 struct imxdma_filter_data {
190 struct imxdma_engine *imxdma;
191 int request;
192 };
193
194 static const struct platform_device_id imx_dma_devtype[] = {
195 {
196 .name = "imx1-dma",
197 .driver_data = IMX1_DMA,
198 }, {
199 .name = "imx21-dma",
200 .driver_data = IMX21_DMA,
201 }, {
202 .name = "imx27-dma",
203 .driver_data = IMX27_DMA,
204 }, {
205 /* sentinel */
206 }
207 };
208 MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
209
210 static const struct of_device_id imx_dma_of_dev_id[] = {
211 {
212 .compatible = "fsl,imx1-dma",
213 .data = &imx_dma_devtype[IMX1_DMA],
214 }, {
215 .compatible = "fsl,imx21-dma",
216 .data = &imx_dma_devtype[IMX21_DMA],
217 }, {
218 .compatible = "fsl,imx27-dma",
219 .data = &imx_dma_devtype[IMX27_DMA],
220 }, {
221 /* sentinel */
222 }
223 };
224 MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);
225
is_imx1_dma(struct imxdma_engine * imxdma)226 static inline int is_imx1_dma(struct imxdma_engine *imxdma)
227 {
228 return imxdma->devtype == IMX1_DMA;
229 }
230
is_imx27_dma(struct imxdma_engine * imxdma)231 static inline int is_imx27_dma(struct imxdma_engine *imxdma)
232 {
233 return imxdma->devtype == IMX27_DMA;
234 }
235
to_imxdma_chan(struct dma_chan * chan)236 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
237 {
238 return container_of(chan, struct imxdma_channel, chan);
239 }
240
imxdma_chan_is_doing_cyclic(struct imxdma_channel * imxdmac)241 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
242 {
243 struct imxdma_desc *desc;
244
245 if (!list_empty(&imxdmac->ld_active)) {
246 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
247 node);
248 if (desc->type == IMXDMA_DESC_CYCLIC)
249 return true;
250 }
251 return false;
252 }
253
254
255
imx_dmav1_writel(struct imxdma_engine * imxdma,unsigned val,unsigned offset)256 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
257 unsigned offset)
258 {
259 __raw_writel(val, imxdma->base + offset);
260 }
261
imx_dmav1_readl(struct imxdma_engine * imxdma,unsigned offset)262 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
263 {
264 return __raw_readl(imxdma->base + offset);
265 }
266
imxdma_hw_chain(struct imxdma_channel * imxdmac)267 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
268 {
269 struct imxdma_engine *imxdma = imxdmac->imxdma;
270
271 if (is_imx27_dma(imxdma))
272 return imxdmac->hw_chaining;
273 else
274 return 0;
275 }
276
277 /*
278 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
279 */
imxdma_sg_next(struct imxdma_desc * d)280 static inline void imxdma_sg_next(struct imxdma_desc *d)
281 {
282 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
283 struct imxdma_engine *imxdma = imxdmac->imxdma;
284 struct scatterlist *sg = d->sg;
285 size_t now;
286
287 now = min_t(size_t, d->len, sg_dma_len(sg));
288 if (d->len != IMX_DMA_LENGTH_LOOP)
289 d->len -= now;
290
291 if (d->direction == DMA_DEV_TO_MEM)
292 imx_dmav1_writel(imxdma, sg->dma_address,
293 DMA_DAR(imxdmac->channel));
294 else
295 imx_dmav1_writel(imxdma, sg->dma_address,
296 DMA_SAR(imxdmac->channel));
297
298 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
299
300 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
301 "size 0x%08x\n", __func__, imxdmac->channel,
302 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
303 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
304 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
305 }
306
imxdma_enable_hw(struct imxdma_desc * d)307 static void imxdma_enable_hw(struct imxdma_desc *d)
308 {
309 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
310 struct imxdma_engine *imxdma = imxdmac->imxdma;
311 int channel = imxdmac->channel;
312 unsigned long flags;
313
314 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
315
316 local_irq_save(flags);
317
318 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
319 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
320 ~(1 << channel), DMA_DIMR);
321 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
322 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
323
324 if (!is_imx1_dma(imxdma) &&
325 d->sg && imxdma_hw_chain(imxdmac)) {
326 d->sg = sg_next(d->sg);
327 if (d->sg) {
328 u32 tmp;
329 imxdma_sg_next(d);
330 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
331 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
332 DMA_CCR(channel));
333 }
334 }
335
336 local_irq_restore(flags);
337 }
338
imxdma_disable_hw(struct imxdma_channel * imxdmac)339 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
340 {
341 struct imxdma_engine *imxdma = imxdmac->imxdma;
342 int channel = imxdmac->channel;
343 unsigned long flags;
344
345 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
346
347 if (imxdma_hw_chain(imxdmac))
348 del_timer(&imxdmac->watchdog);
349
350 local_irq_save(flags);
351 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
352 (1 << channel), DMA_DIMR);
353 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
354 ~CCR_CEN, DMA_CCR(channel));
355 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
356 local_irq_restore(flags);
357 }
358
imxdma_watchdog(struct timer_list * t)359 static void imxdma_watchdog(struct timer_list *t)
360 {
361 struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog);
362 struct imxdma_engine *imxdma = imxdmac->imxdma;
363 int channel = imxdmac->channel;
364
365 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
366
367 /* Tasklet watchdog error handler */
368 tasklet_schedule(&imxdmac->dma_tasklet);
369 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
370 imxdmac->channel);
371 }
372
imxdma_err_handler(int irq,void * dev_id)373 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
374 {
375 struct imxdma_engine *imxdma = dev_id;
376 unsigned int err_mask;
377 int i, disr;
378 int errcode;
379
380 disr = imx_dmav1_readl(imxdma, DMA_DISR);
381
382 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
383 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
384 imx_dmav1_readl(imxdma, DMA_DSESR) |
385 imx_dmav1_readl(imxdma, DMA_DBOSR);
386
387 if (!err_mask)
388 return IRQ_HANDLED;
389
390 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
391
392 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
393 if (!(err_mask & (1 << i)))
394 continue;
395 errcode = 0;
396
397 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
398 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
399 errcode |= IMX_DMA_ERR_BURST;
400 }
401 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
402 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
403 errcode |= IMX_DMA_ERR_REQUEST;
404 }
405 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
406 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
407 errcode |= IMX_DMA_ERR_TRANSFER;
408 }
409 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
410 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
411 errcode |= IMX_DMA_ERR_BUFFER;
412 }
413 /* Tasklet error handler */
414 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
415
416 dev_warn(imxdma->dev,
417 "DMA timeout on channel %d -%s%s%s%s\n", i,
418 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
419 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
420 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
421 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
422 }
423 return IRQ_HANDLED;
424 }
425
dma_irq_handle_channel(struct imxdma_channel * imxdmac)426 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
427 {
428 struct imxdma_engine *imxdma = imxdmac->imxdma;
429 int chno = imxdmac->channel;
430 struct imxdma_desc *desc;
431 unsigned long flags;
432
433 spin_lock_irqsave(&imxdma->lock, flags);
434 if (list_empty(&imxdmac->ld_active)) {
435 spin_unlock_irqrestore(&imxdma->lock, flags);
436 goto out;
437 }
438
439 desc = list_first_entry(&imxdmac->ld_active,
440 struct imxdma_desc,
441 node);
442 spin_unlock_irqrestore(&imxdma->lock, flags);
443
444 if (desc->sg) {
445 u32 tmp;
446 desc->sg = sg_next(desc->sg);
447
448 if (desc->sg) {
449 imxdma_sg_next(desc);
450
451 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
452
453 if (imxdma_hw_chain(imxdmac)) {
454 /* FIXME: The timeout should probably be
455 * configurable
456 */
457 mod_timer(&imxdmac->watchdog,
458 jiffies + msecs_to_jiffies(500));
459
460 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
461 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
462 } else {
463 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
464 DMA_CCR(chno));
465 tmp |= CCR_CEN;
466 }
467
468 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
469
470 if (imxdma_chan_is_doing_cyclic(imxdmac))
471 /* Tasklet progression */
472 tasklet_schedule(&imxdmac->dma_tasklet);
473
474 return;
475 }
476
477 if (imxdma_hw_chain(imxdmac)) {
478 del_timer(&imxdmac->watchdog);
479 return;
480 }
481 }
482
483 out:
484 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
485 /* Tasklet irq */
486 tasklet_schedule(&imxdmac->dma_tasklet);
487 }
488
dma_irq_handler(int irq,void * dev_id)489 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
490 {
491 struct imxdma_engine *imxdma = dev_id;
492 int i, disr;
493
494 if (!is_imx1_dma(imxdma))
495 imxdma_err_handler(irq, dev_id);
496
497 disr = imx_dmav1_readl(imxdma, DMA_DISR);
498
499 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
500
501 imx_dmav1_writel(imxdma, disr, DMA_DISR);
502 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
503 if (disr & (1 << i))
504 dma_irq_handle_channel(&imxdma->channel[i]);
505 }
506
507 return IRQ_HANDLED;
508 }
509
imxdma_xfer_desc(struct imxdma_desc * d)510 static int imxdma_xfer_desc(struct imxdma_desc *d)
511 {
512 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
513 struct imxdma_engine *imxdma = imxdmac->imxdma;
514 int slot = -1;
515 int i;
516
517 /* Configure and enable */
518 switch (d->type) {
519 case IMXDMA_DESC_INTERLEAVED:
520 /* Try to get a free 2D slot */
521 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
522 if ((imxdma->slots_2d[i].count > 0) &&
523 ((imxdma->slots_2d[i].xsr != d->x) ||
524 (imxdma->slots_2d[i].ysr != d->y) ||
525 (imxdma->slots_2d[i].wsr != d->w)))
526 continue;
527 slot = i;
528 break;
529 }
530 if (slot < 0)
531 return -EBUSY;
532
533 imxdma->slots_2d[slot].xsr = d->x;
534 imxdma->slots_2d[slot].ysr = d->y;
535 imxdma->slots_2d[slot].wsr = d->w;
536 imxdma->slots_2d[slot].count++;
537
538 imxdmac->slot_2d = slot;
539 imxdmac->enabled_2d = true;
540
541 if (slot == IMX_DMA_2D_SLOT_A) {
542 d->config_mem &= ~CCR_MSEL_B;
543 d->config_port &= ~CCR_MSEL_B;
544 imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
545 imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
546 imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
547 } else {
548 d->config_mem |= CCR_MSEL_B;
549 d->config_port |= CCR_MSEL_B;
550 imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
551 imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
552 imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
553 }
554 /*
555 * We fall-through here intentionally, since a 2D transfer is
556 * similar to MEMCPY just adding the 2D slot configuration.
557 */
558 fallthrough;
559 case IMXDMA_DESC_MEMCPY:
560 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
561 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
562 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
563 DMA_CCR(imxdmac->channel));
564
565 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
566
567 dev_dbg(imxdma->dev,
568 "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n",
569 __func__, imxdmac->channel,
570 (unsigned long long)d->dest,
571 (unsigned long long)d->src, d->len);
572
573 break;
574 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
575 case IMXDMA_DESC_CYCLIC:
576 case IMXDMA_DESC_SLAVE_SG:
577 if (d->direction == DMA_DEV_TO_MEM) {
578 imx_dmav1_writel(imxdma, imxdmac->per_address,
579 DMA_SAR(imxdmac->channel));
580 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
581 DMA_CCR(imxdmac->channel));
582
583 dev_dbg(imxdma->dev,
584 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n",
585 __func__, imxdmac->channel,
586 d->sg, d->sgcount, d->len,
587 (unsigned long long)imxdmac->per_address);
588 } else if (d->direction == DMA_MEM_TO_DEV) {
589 imx_dmav1_writel(imxdma, imxdmac->per_address,
590 DMA_DAR(imxdmac->channel));
591 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
592 DMA_CCR(imxdmac->channel));
593
594 dev_dbg(imxdma->dev,
595 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n",
596 __func__, imxdmac->channel,
597 d->sg, d->sgcount, d->len,
598 (unsigned long long)imxdmac->per_address);
599 } else {
600 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
601 __func__, imxdmac->channel);
602 return -EINVAL;
603 }
604
605 imxdma_sg_next(d);
606
607 break;
608 default:
609 return -EINVAL;
610 }
611 imxdma_enable_hw(d);
612 return 0;
613 }
614
imxdma_tasklet(struct tasklet_struct * t)615 static void imxdma_tasklet(struct tasklet_struct *t)
616 {
617 struct imxdma_channel *imxdmac = from_tasklet(imxdmac, t, dma_tasklet);
618 struct imxdma_engine *imxdma = imxdmac->imxdma;
619 struct imxdma_desc *desc, *next_desc;
620 unsigned long flags;
621
622 spin_lock_irqsave(&imxdma->lock, flags);
623
624 if (list_empty(&imxdmac->ld_active)) {
625 /* Someone might have called terminate all */
626 spin_unlock_irqrestore(&imxdma->lock, flags);
627 return;
628 }
629 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
630
631 /* If we are dealing with a cyclic descriptor, keep it on ld_active
632 * and dont mark the descriptor as complete.
633 * Only in non-cyclic cases it would be marked as complete
634 */
635 if (imxdma_chan_is_doing_cyclic(imxdmac))
636 goto out;
637 else
638 dma_cookie_complete(&desc->desc);
639
640 /* Free 2D slot if it was an interleaved transfer */
641 if (imxdmac->enabled_2d) {
642 imxdma->slots_2d[imxdmac->slot_2d].count--;
643 imxdmac->enabled_2d = false;
644 }
645
646 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
647
648 if (!list_empty(&imxdmac->ld_queue)) {
649 next_desc = list_first_entry(&imxdmac->ld_queue,
650 struct imxdma_desc, node);
651 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
652 if (imxdma_xfer_desc(next_desc) < 0)
653 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
654 __func__, imxdmac->channel);
655 }
656 out:
657 spin_unlock_irqrestore(&imxdma->lock, flags);
658
659 dmaengine_desc_get_callback_invoke(&desc->desc, NULL);
660 }
661
imxdma_terminate_all(struct dma_chan * chan)662 static int imxdma_terminate_all(struct dma_chan *chan)
663 {
664 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
665 struct imxdma_engine *imxdma = imxdmac->imxdma;
666 unsigned long flags;
667
668 imxdma_disable_hw(imxdmac);
669
670 spin_lock_irqsave(&imxdma->lock, flags);
671 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
672 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
673 spin_unlock_irqrestore(&imxdma->lock, flags);
674 return 0;
675 }
676
imxdma_config_write(struct dma_chan * chan,struct dma_slave_config * dmaengine_cfg,enum dma_transfer_direction direction)677 static int imxdma_config_write(struct dma_chan *chan,
678 struct dma_slave_config *dmaengine_cfg,
679 enum dma_transfer_direction direction)
680 {
681 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
682 struct imxdma_engine *imxdma = imxdmac->imxdma;
683 unsigned int mode = 0;
684
685 if (direction == DMA_DEV_TO_MEM) {
686 imxdmac->per_address = dmaengine_cfg->src_addr;
687 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
688 imxdmac->word_size = dmaengine_cfg->src_addr_width;
689 } else {
690 imxdmac->per_address = dmaengine_cfg->dst_addr;
691 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
692 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
693 }
694
695 switch (imxdmac->word_size) {
696 case DMA_SLAVE_BUSWIDTH_1_BYTE:
697 mode = IMX_DMA_MEMSIZE_8;
698 break;
699 case DMA_SLAVE_BUSWIDTH_2_BYTES:
700 mode = IMX_DMA_MEMSIZE_16;
701 break;
702 default:
703 case DMA_SLAVE_BUSWIDTH_4_BYTES:
704 mode = IMX_DMA_MEMSIZE_32;
705 break;
706 }
707
708 imxdmac->hw_chaining = 0;
709
710 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
711 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
712 CCR_REN;
713 imxdmac->ccr_to_device =
714 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
715 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
716 imx_dmav1_writel(imxdma, imxdmac->dma_request,
717 DMA_RSSR(imxdmac->channel));
718
719 /* Set burst length */
720 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
721 imxdmac->word_size, DMA_BLR(imxdmac->channel));
722
723 return 0;
724 }
725
imxdma_config(struct dma_chan * chan,struct dma_slave_config * dmaengine_cfg)726 static int imxdma_config(struct dma_chan *chan,
727 struct dma_slave_config *dmaengine_cfg)
728 {
729 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
730
731 memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg));
732
733 return 0;
734 }
735
imxdma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)736 static enum dma_status imxdma_tx_status(struct dma_chan *chan,
737 dma_cookie_t cookie,
738 struct dma_tx_state *txstate)
739 {
740 return dma_cookie_status(chan, cookie, txstate);
741 }
742
imxdma_tx_submit(struct dma_async_tx_descriptor * tx)743 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
744 {
745 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
746 struct imxdma_engine *imxdma = imxdmac->imxdma;
747 dma_cookie_t cookie;
748 unsigned long flags;
749
750 spin_lock_irqsave(&imxdma->lock, flags);
751 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
752 cookie = dma_cookie_assign(tx);
753 spin_unlock_irqrestore(&imxdma->lock, flags);
754
755 return cookie;
756 }
757
imxdma_alloc_chan_resources(struct dma_chan * chan)758 static int imxdma_alloc_chan_resources(struct dma_chan *chan)
759 {
760 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
761 struct imx_dma_data *data = chan->private;
762
763 if (data != NULL)
764 imxdmac->dma_request = data->dma_request;
765
766 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
767 struct imxdma_desc *desc;
768
769 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
770 if (!desc)
771 break;
772 memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor));
773 dma_async_tx_descriptor_init(&desc->desc, chan);
774 desc->desc.tx_submit = imxdma_tx_submit;
775 /* txd.flags will be overwritten in prep funcs */
776 desc->desc.flags = DMA_CTRL_ACK;
777 desc->status = DMA_COMPLETE;
778
779 list_add_tail(&desc->node, &imxdmac->ld_free);
780 imxdmac->descs_allocated++;
781 }
782
783 if (!imxdmac->descs_allocated)
784 return -ENOMEM;
785
786 return imxdmac->descs_allocated;
787 }
788
imxdma_free_chan_resources(struct dma_chan * chan)789 static void imxdma_free_chan_resources(struct dma_chan *chan)
790 {
791 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
792 struct imxdma_engine *imxdma = imxdmac->imxdma;
793 struct imxdma_desc *desc, *_desc;
794 unsigned long flags;
795
796 spin_lock_irqsave(&imxdma->lock, flags);
797
798 imxdma_disable_hw(imxdmac);
799 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
800 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
801
802 spin_unlock_irqrestore(&imxdma->lock, flags);
803
804 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
805 kfree(desc);
806 imxdmac->descs_allocated--;
807 }
808 INIT_LIST_HEAD(&imxdmac->ld_free);
809
810 kfree(imxdmac->sg_list);
811 imxdmac->sg_list = NULL;
812 }
813
imxdma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)814 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
815 struct dma_chan *chan, struct scatterlist *sgl,
816 unsigned int sg_len, enum dma_transfer_direction direction,
817 unsigned long flags, void *context)
818 {
819 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
820 struct scatterlist *sg;
821 int i, dma_length = 0;
822 struct imxdma_desc *desc;
823
824 if (list_empty(&imxdmac->ld_free) ||
825 imxdma_chan_is_doing_cyclic(imxdmac))
826 return NULL;
827
828 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
829
830 for_each_sg(sgl, sg, sg_len, i) {
831 dma_length += sg_dma_len(sg);
832 }
833
834 imxdma_config_write(chan, &imxdmac->config, direction);
835
836 switch (imxdmac->word_size) {
837 case DMA_SLAVE_BUSWIDTH_4_BYTES:
838 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
839 return NULL;
840 break;
841 case DMA_SLAVE_BUSWIDTH_2_BYTES:
842 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
843 return NULL;
844 break;
845 case DMA_SLAVE_BUSWIDTH_1_BYTE:
846 break;
847 default:
848 return NULL;
849 }
850
851 desc->type = IMXDMA_DESC_SLAVE_SG;
852 desc->sg = sgl;
853 desc->sgcount = sg_len;
854 desc->len = dma_length;
855 desc->direction = direction;
856 if (direction == DMA_DEV_TO_MEM) {
857 desc->src = imxdmac->per_address;
858 } else {
859 desc->dest = imxdmac->per_address;
860 }
861 desc->desc.callback = NULL;
862 desc->desc.callback_param = NULL;
863
864 return &desc->desc;
865 }
866
imxdma_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t dma_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)867 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
868 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
869 size_t period_len, enum dma_transfer_direction direction,
870 unsigned long flags)
871 {
872 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
873 struct imxdma_engine *imxdma = imxdmac->imxdma;
874 struct imxdma_desc *desc;
875 int i;
876 unsigned int periods = buf_len / period_len;
877
878 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n",
879 __func__, imxdmac->channel, buf_len, period_len);
880
881 if (list_empty(&imxdmac->ld_free) ||
882 imxdma_chan_is_doing_cyclic(imxdmac))
883 return NULL;
884
885 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
886
887 kfree(imxdmac->sg_list);
888
889 imxdmac->sg_list = kcalloc(periods + 1,
890 sizeof(struct scatterlist), GFP_ATOMIC);
891 if (!imxdmac->sg_list)
892 return NULL;
893
894 sg_init_table(imxdmac->sg_list, periods);
895
896 for (i = 0; i < periods; i++) {
897 sg_assign_page(&imxdmac->sg_list[i], NULL);
898 imxdmac->sg_list[i].offset = 0;
899 imxdmac->sg_list[i].dma_address = dma_addr;
900 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
901 dma_addr += period_len;
902 }
903
904 /* close the loop */
905 sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list);
906
907 desc->type = IMXDMA_DESC_CYCLIC;
908 desc->sg = imxdmac->sg_list;
909 desc->sgcount = periods;
910 desc->len = IMX_DMA_LENGTH_LOOP;
911 desc->direction = direction;
912 if (direction == DMA_DEV_TO_MEM) {
913 desc->src = imxdmac->per_address;
914 } else {
915 desc->dest = imxdmac->per_address;
916 }
917 desc->desc.callback = NULL;
918 desc->desc.callback_param = NULL;
919
920 imxdma_config_write(chan, &imxdmac->config, direction);
921
922 return &desc->desc;
923 }
924
imxdma_prep_dma_memcpy(struct dma_chan * chan,dma_addr_t dest,dma_addr_t src,size_t len,unsigned long flags)925 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
926 struct dma_chan *chan, dma_addr_t dest,
927 dma_addr_t src, size_t len, unsigned long flags)
928 {
929 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
930 struct imxdma_engine *imxdma = imxdmac->imxdma;
931 struct imxdma_desc *desc;
932
933 dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n",
934 __func__, imxdmac->channel, (unsigned long long)src,
935 (unsigned long long)dest, len);
936
937 if (list_empty(&imxdmac->ld_free) ||
938 imxdma_chan_is_doing_cyclic(imxdmac))
939 return NULL;
940
941 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
942
943 desc->type = IMXDMA_DESC_MEMCPY;
944 desc->src = src;
945 desc->dest = dest;
946 desc->len = len;
947 desc->direction = DMA_MEM_TO_MEM;
948 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
949 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
950 desc->desc.callback = NULL;
951 desc->desc.callback_param = NULL;
952
953 return &desc->desc;
954 }
955
imxdma_prep_dma_interleaved(struct dma_chan * chan,struct dma_interleaved_template * xt,unsigned long flags)956 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
957 struct dma_chan *chan, struct dma_interleaved_template *xt,
958 unsigned long flags)
959 {
960 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
961 struct imxdma_engine *imxdma = imxdmac->imxdma;
962 struct imxdma_desc *desc;
963
964 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n"
965 " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
966 imxdmac->channel, (unsigned long long)xt->src_start,
967 (unsigned long long) xt->dst_start,
968 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
969 xt->numf, xt->frame_size);
970
971 if (list_empty(&imxdmac->ld_free) ||
972 imxdma_chan_is_doing_cyclic(imxdmac))
973 return NULL;
974
975 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
976 return NULL;
977
978 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
979
980 desc->type = IMXDMA_DESC_INTERLEAVED;
981 desc->src = xt->src_start;
982 desc->dest = xt->dst_start;
983 desc->x = xt->sgl[0].size;
984 desc->y = xt->numf;
985 desc->w = xt->sgl[0].icg + desc->x;
986 desc->len = desc->x * desc->y;
987 desc->direction = DMA_MEM_TO_MEM;
988 desc->config_port = IMX_DMA_MEMSIZE_32;
989 desc->config_mem = IMX_DMA_MEMSIZE_32;
990 if (xt->src_sgl)
991 desc->config_mem |= IMX_DMA_TYPE_2D;
992 if (xt->dst_sgl)
993 desc->config_port |= IMX_DMA_TYPE_2D;
994 desc->desc.callback = NULL;
995 desc->desc.callback_param = NULL;
996
997 return &desc->desc;
998 }
999
imxdma_issue_pending(struct dma_chan * chan)1000 static void imxdma_issue_pending(struct dma_chan *chan)
1001 {
1002 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
1003 struct imxdma_engine *imxdma = imxdmac->imxdma;
1004 struct imxdma_desc *desc;
1005 unsigned long flags;
1006
1007 spin_lock_irqsave(&imxdma->lock, flags);
1008 if (list_empty(&imxdmac->ld_active) &&
1009 !list_empty(&imxdmac->ld_queue)) {
1010 desc = list_first_entry(&imxdmac->ld_queue,
1011 struct imxdma_desc, node);
1012
1013 if (imxdma_xfer_desc(desc) < 0) {
1014 dev_warn(imxdma->dev,
1015 "%s: channel: %d couldn't issue DMA xfer\n",
1016 __func__, imxdmac->channel);
1017 } else {
1018 list_move_tail(imxdmac->ld_queue.next,
1019 &imxdmac->ld_active);
1020 }
1021 }
1022 spin_unlock_irqrestore(&imxdma->lock, flags);
1023 }
1024
imxdma_filter_fn(struct dma_chan * chan,void * param)1025 static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
1026 {
1027 struct imxdma_filter_data *fdata = param;
1028 struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);
1029
1030 if (chan->device->dev != fdata->imxdma->dev)
1031 return false;
1032
1033 imxdma_chan->dma_request = fdata->request;
1034 chan->private = NULL;
1035
1036 return true;
1037 }
1038
imxdma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1039 static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
1040 struct of_dma *ofdma)
1041 {
1042 int count = dma_spec->args_count;
1043 struct imxdma_engine *imxdma = ofdma->of_dma_data;
1044 struct imxdma_filter_data fdata = {
1045 .imxdma = imxdma,
1046 };
1047
1048 if (count != 1)
1049 return NULL;
1050
1051 fdata.request = dma_spec->args[0];
1052
1053 return dma_request_channel(imxdma->dma_device.cap_mask,
1054 imxdma_filter_fn, &fdata);
1055 }
1056
imxdma_probe(struct platform_device * pdev)1057 static int __init imxdma_probe(struct platform_device *pdev)
1058 {
1059 struct imxdma_engine *imxdma;
1060 struct resource *res;
1061 const struct of_device_id *of_id;
1062 int ret, i;
1063 int irq, irq_err;
1064
1065 of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
1066 if (of_id)
1067 pdev->id_entry = of_id->data;
1068
1069 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
1070 if (!imxdma)
1071 return -ENOMEM;
1072
1073 imxdma->dev = &pdev->dev;
1074 imxdma->devtype = pdev->id_entry->driver_data;
1075
1076 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1077 imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1078 if (IS_ERR(imxdma->base))
1079 return PTR_ERR(imxdma->base);
1080
1081 irq = platform_get_irq(pdev, 0);
1082 if (irq < 0)
1083 return irq;
1084
1085 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
1086 if (IS_ERR(imxdma->dma_ipg))
1087 return PTR_ERR(imxdma->dma_ipg);
1088
1089 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
1090 if (IS_ERR(imxdma->dma_ahb))
1091 return PTR_ERR(imxdma->dma_ahb);
1092
1093 ret = clk_prepare_enable(imxdma->dma_ipg);
1094 if (ret)
1095 return ret;
1096 ret = clk_prepare_enable(imxdma->dma_ahb);
1097 if (ret)
1098 goto disable_dma_ipg_clk;
1099
1100 /* reset DMA module */
1101 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
1102
1103 if (is_imx1_dma(imxdma)) {
1104 ret = devm_request_irq(&pdev->dev, irq,
1105 dma_irq_handler, 0, "DMA", imxdma);
1106 if (ret) {
1107 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
1108 goto disable_dma_ahb_clk;
1109 }
1110 imxdma->irq = irq;
1111
1112 irq_err = platform_get_irq(pdev, 1);
1113 if (irq_err < 0) {
1114 ret = irq_err;
1115 goto disable_dma_ahb_clk;
1116 }
1117
1118 ret = devm_request_irq(&pdev->dev, irq_err,
1119 imxdma_err_handler, 0, "DMA", imxdma);
1120 if (ret) {
1121 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
1122 goto disable_dma_ahb_clk;
1123 }
1124 imxdma->irq_err = irq_err;
1125 }
1126
1127 /* enable DMA module */
1128 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1129
1130 /* clear all interrupts */
1131 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1132
1133 /* disable interrupts */
1134 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1135
1136 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1137
1138 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1139 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1140 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1141 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1142
1143 /* Initialize 2D global parameters */
1144 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1145 imxdma->slots_2d[i].count = 0;
1146
1147 spin_lock_init(&imxdma->lock);
1148
1149 /* Initialize channel parameters */
1150 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1151 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1152
1153 if (!is_imx1_dma(imxdma)) {
1154 ret = devm_request_irq(&pdev->dev, irq + i,
1155 dma_irq_handler, 0, "DMA", imxdma);
1156 if (ret) {
1157 dev_warn(imxdma->dev, "Can't register IRQ %d "
1158 "for DMA channel %d\n",
1159 irq + i, i);
1160 goto disable_dma_ahb_clk;
1161 }
1162
1163 imxdmac->irq = irq + i;
1164 timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0);
1165 }
1166
1167 imxdmac->imxdma = imxdma;
1168
1169 INIT_LIST_HEAD(&imxdmac->ld_queue);
1170 INIT_LIST_HEAD(&imxdmac->ld_free);
1171 INIT_LIST_HEAD(&imxdmac->ld_active);
1172
1173 tasklet_setup(&imxdmac->dma_tasklet, imxdma_tasklet);
1174 imxdmac->chan.device = &imxdma->dma_device;
1175 dma_cookie_init(&imxdmac->chan);
1176 imxdmac->channel = i;
1177
1178 /* Add the channel to the DMAC list */
1179 list_add_tail(&imxdmac->chan.device_node,
1180 &imxdma->dma_device.channels);
1181 }
1182
1183 imxdma->dma_device.dev = &pdev->dev;
1184
1185 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1186 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1187 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1188 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1189 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1190 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1191 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1192 imxdma->dma_device.device_config = imxdma_config;
1193 imxdma->dma_device.device_terminate_all = imxdma_terminate_all;
1194 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1195
1196 platform_set_drvdata(pdev, imxdma);
1197
1198 imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES;
1199 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1200
1201 ret = dma_async_device_register(&imxdma->dma_device);
1202 if (ret) {
1203 dev_err(&pdev->dev, "unable to register\n");
1204 goto disable_dma_ahb_clk;
1205 }
1206
1207 if (pdev->dev.of_node) {
1208 ret = of_dma_controller_register(pdev->dev.of_node,
1209 imxdma_xlate, imxdma);
1210 if (ret) {
1211 dev_err(&pdev->dev, "unable to register of_dma_controller\n");
1212 goto err_of_dma_controller;
1213 }
1214 }
1215
1216 return 0;
1217
1218 err_of_dma_controller:
1219 dma_async_device_unregister(&imxdma->dma_device);
1220 disable_dma_ahb_clk:
1221 clk_disable_unprepare(imxdma->dma_ahb);
1222 disable_dma_ipg_clk:
1223 clk_disable_unprepare(imxdma->dma_ipg);
1224 return ret;
1225 }
1226
imxdma_free_irq(struct platform_device * pdev,struct imxdma_engine * imxdma)1227 static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma)
1228 {
1229 int i;
1230
1231 if (is_imx1_dma(imxdma)) {
1232 disable_irq(imxdma->irq);
1233 disable_irq(imxdma->irq_err);
1234 }
1235
1236 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1237 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1238
1239 if (!is_imx1_dma(imxdma))
1240 disable_irq(imxdmac->irq);
1241
1242 tasklet_kill(&imxdmac->dma_tasklet);
1243 }
1244 }
1245
imxdma_remove(struct platform_device * pdev)1246 static int imxdma_remove(struct platform_device *pdev)
1247 {
1248 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1249
1250 imxdma_free_irq(pdev, imxdma);
1251
1252 dma_async_device_unregister(&imxdma->dma_device);
1253
1254 if (pdev->dev.of_node)
1255 of_dma_controller_free(pdev->dev.of_node);
1256
1257 clk_disable_unprepare(imxdma->dma_ipg);
1258 clk_disable_unprepare(imxdma->dma_ahb);
1259
1260 return 0;
1261 }
1262
1263 static struct platform_driver imxdma_driver = {
1264 .driver = {
1265 .name = "imx-dma",
1266 .of_match_table = imx_dma_of_dev_id,
1267 },
1268 .id_table = imx_dma_devtype,
1269 .remove = imxdma_remove,
1270 };
1271
imxdma_module_init(void)1272 static int __init imxdma_module_init(void)
1273 {
1274 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1275 }
1276 subsys_initcall(imxdma_module_init);
1277
1278 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1279 MODULE_DESCRIPTION("i.MX dma driver");
1280 MODULE_LICENSE("GPL");
1281