1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
31
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
35
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
40
41 /**
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
56 */
57 struct panel_desc {
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
62
63 unsigned int bpc;
64
65 /**
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
68 */
69 struct {
70 unsigned int width;
71 unsigned int height;
72 } size;
73
74 /**
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
81 * video data
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
86 */
87 struct {
88 unsigned int prepare;
89 unsigned int hpd_absent_delay;
90 unsigned int enable;
91 unsigned int disable;
92 unsigned int unprepare;
93 } delay;
94
95 u32 bus_format;
96 u32 bus_flags;
97 int connector_type;
98 };
99
100 struct panel_simple {
101 struct drm_panel base;
102 bool prepared;
103 bool enabled;
104 bool no_hpd;
105
106 const struct panel_desc *desc;
107
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
110
111 struct gpio_desc *enable_gpio;
112 struct gpio_desc *hpd_gpio;
113
114 struct drm_display_mode override_mode;
115
116 enum drm_panel_orientation orientation;
117 };
118
to_panel_simple(struct drm_panel * panel)119 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
120 {
121 return container_of(panel, struct panel_simple, base);
122 }
123
panel_simple_get_timings_modes(struct panel_simple * panel,struct drm_connector * connector)124 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
125 struct drm_connector *connector)
126 {
127 struct drm_display_mode *mode;
128 unsigned int i, num = 0;
129
130 for (i = 0; i < panel->desc->num_timings; i++) {
131 const struct display_timing *dt = &panel->desc->timings[i];
132 struct videomode vm;
133
134 videomode_from_timing(dt, &vm);
135 mode = drm_mode_create(connector->dev);
136 if (!mode) {
137 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
138 dt->hactive.typ, dt->vactive.typ);
139 continue;
140 }
141
142 drm_display_mode_from_videomode(&vm, mode);
143
144 mode->type |= DRM_MODE_TYPE_DRIVER;
145
146 if (panel->desc->num_timings == 1)
147 mode->type |= DRM_MODE_TYPE_PREFERRED;
148
149 drm_mode_probed_add(connector, mode);
150 num++;
151 }
152
153 return num;
154 }
155
panel_simple_get_display_modes(struct panel_simple * panel,struct drm_connector * connector)156 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
157 struct drm_connector *connector)
158 {
159 struct drm_display_mode *mode;
160 unsigned int i, num = 0;
161
162 for (i = 0; i < panel->desc->num_modes; i++) {
163 const struct drm_display_mode *m = &panel->desc->modes[i];
164
165 mode = drm_mode_duplicate(connector->dev, m);
166 if (!mode) {
167 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
168 m->hdisplay, m->vdisplay,
169 drm_mode_vrefresh(m));
170 continue;
171 }
172
173 mode->type |= DRM_MODE_TYPE_DRIVER;
174
175 if (panel->desc->num_modes == 1)
176 mode->type |= DRM_MODE_TYPE_PREFERRED;
177
178 drm_mode_set_name(mode);
179
180 drm_mode_probed_add(connector, mode);
181 num++;
182 }
183
184 return num;
185 }
186
panel_simple_get_non_edid_modes(struct panel_simple * panel,struct drm_connector * connector)187 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
188 struct drm_connector *connector)
189 {
190 struct drm_display_mode *mode;
191 bool has_override = panel->override_mode.type;
192 unsigned int num = 0;
193
194 if (!panel->desc)
195 return 0;
196
197 if (has_override) {
198 mode = drm_mode_duplicate(connector->dev,
199 &panel->override_mode);
200 if (mode) {
201 drm_mode_probed_add(connector, mode);
202 num = 1;
203 } else {
204 dev_err(panel->base.dev, "failed to add override mode\n");
205 }
206 }
207
208 /* Only add timings if override was not there or failed to validate */
209 if (num == 0 && panel->desc->num_timings)
210 num = panel_simple_get_timings_modes(panel, connector);
211
212 /*
213 * Only add fixed modes if timings/override added no mode.
214 *
215 * We should only ever have either the display timings specified
216 * or a fixed mode. Anything else is rather bogus.
217 */
218 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
219 if (num == 0)
220 num = panel_simple_get_display_modes(panel, connector);
221
222 connector->display_info.bpc = panel->desc->bpc;
223 connector->display_info.width_mm = panel->desc->size.width;
224 connector->display_info.height_mm = panel->desc->size.height;
225 if (panel->desc->bus_format)
226 drm_display_info_set_bus_formats(&connector->display_info,
227 &panel->desc->bus_format, 1);
228 connector->display_info.bus_flags = panel->desc->bus_flags;
229
230 return num;
231 }
232
panel_simple_disable(struct drm_panel * panel)233 static int panel_simple_disable(struct drm_panel *panel)
234 {
235 struct panel_simple *p = to_panel_simple(panel);
236
237 if (!p->enabled)
238 return 0;
239
240 if (p->desc->delay.disable)
241 msleep(p->desc->delay.disable);
242
243 p->enabled = false;
244
245 return 0;
246 }
247
panel_simple_unprepare(struct drm_panel * panel)248 static int panel_simple_unprepare(struct drm_panel *panel)
249 {
250 struct panel_simple *p = to_panel_simple(panel);
251
252 if (!p->prepared)
253 return 0;
254
255 gpiod_set_value_cansleep(p->enable_gpio, 0);
256
257 regulator_disable(p->supply);
258
259 if (p->desc->delay.unprepare)
260 msleep(p->desc->delay.unprepare);
261
262 p->prepared = false;
263
264 return 0;
265 }
266
panel_simple_get_hpd_gpio(struct device * dev,struct panel_simple * p,bool from_probe)267 static int panel_simple_get_hpd_gpio(struct device *dev,
268 struct panel_simple *p, bool from_probe)
269 {
270 int err;
271
272 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
273 if (IS_ERR(p->hpd_gpio)) {
274 err = PTR_ERR(p->hpd_gpio);
275
276 /*
277 * If we're called from probe we won't consider '-EPROBE_DEFER'
278 * to be an error--we'll leave the error code in "hpd_gpio".
279 * When we try to use it we'll try again. This allows for
280 * circular dependencies where the component providing the
281 * hpd gpio needs the panel to init before probing.
282 */
283 if (err != -EPROBE_DEFER || !from_probe) {
284 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
285 return err;
286 }
287 }
288
289 return 0;
290 }
291
panel_simple_prepare(struct drm_panel * panel)292 static int panel_simple_prepare(struct drm_panel *panel)
293 {
294 struct panel_simple *p = to_panel_simple(panel);
295 unsigned int delay;
296 int err;
297 int hpd_asserted;
298
299 if (p->prepared)
300 return 0;
301
302 err = regulator_enable(p->supply);
303 if (err < 0) {
304 dev_err(panel->dev, "failed to enable supply: %d\n", err);
305 return err;
306 }
307
308 gpiod_set_value_cansleep(p->enable_gpio, 1);
309
310 delay = p->desc->delay.prepare;
311 if (p->no_hpd)
312 delay += p->desc->delay.hpd_absent_delay;
313 if (delay)
314 msleep(delay);
315
316 if (p->hpd_gpio) {
317 if (IS_ERR(p->hpd_gpio)) {
318 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
319 if (err)
320 return err;
321 }
322
323 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
324 hpd_asserted, hpd_asserted,
325 1000, 2000000);
326 if (hpd_asserted < 0)
327 err = hpd_asserted;
328
329 if (err) {
330 dev_err(panel->dev,
331 "error waiting for hpd GPIO: %d\n", err);
332 return err;
333 }
334 }
335
336 p->prepared = true;
337
338 return 0;
339 }
340
panel_simple_enable(struct drm_panel * panel)341 static int panel_simple_enable(struct drm_panel *panel)
342 {
343 struct panel_simple *p = to_panel_simple(panel);
344
345 if (p->enabled)
346 return 0;
347
348 if (p->desc->delay.enable)
349 msleep(p->desc->delay.enable);
350
351 p->enabled = true;
352
353 return 0;
354 }
355
panel_simple_get_modes(struct drm_panel * panel,struct drm_connector * connector)356 static int panel_simple_get_modes(struct drm_panel *panel,
357 struct drm_connector *connector)
358 {
359 struct panel_simple *p = to_panel_simple(panel);
360 int num = 0;
361
362 /* probe EDID if a DDC bus is available */
363 if (p->ddc) {
364 struct edid *edid = drm_get_edid(connector, p->ddc);
365
366 drm_connector_update_edid_property(connector, edid);
367 if (edid) {
368 num += drm_add_edid_modes(connector, edid);
369 kfree(edid);
370 }
371 }
372
373 /* add hard-coded panel modes */
374 num += panel_simple_get_non_edid_modes(p, connector);
375
376 /* set up connector's "panel orientation" property */
377 drm_connector_set_panel_orientation(connector, p->orientation);
378
379 return num;
380 }
381
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)382 static int panel_simple_get_timings(struct drm_panel *panel,
383 unsigned int num_timings,
384 struct display_timing *timings)
385 {
386 struct panel_simple *p = to_panel_simple(panel);
387 unsigned int i;
388
389 if (p->desc->num_timings < num_timings)
390 num_timings = p->desc->num_timings;
391
392 if (timings)
393 for (i = 0; i < num_timings; i++)
394 timings[i] = p->desc->timings[i];
395
396 return p->desc->num_timings;
397 }
398
399 static const struct drm_panel_funcs panel_simple_funcs = {
400 .disable = panel_simple_disable,
401 .unprepare = panel_simple_unprepare,
402 .prepare = panel_simple_prepare,
403 .enable = panel_simple_enable,
404 .get_modes = panel_simple_get_modes,
405 .get_timings = panel_simple_get_timings,
406 };
407
408 static struct panel_desc panel_dpi;
409
panel_dpi_probe(struct device * dev,struct panel_simple * panel)410 static int panel_dpi_probe(struct device *dev,
411 struct panel_simple *panel)
412 {
413 struct display_timing *timing;
414 const struct device_node *np;
415 struct panel_desc *desc;
416 unsigned int bus_flags;
417 struct videomode vm;
418 int ret;
419
420 np = dev->of_node;
421 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
422 if (!desc)
423 return -ENOMEM;
424
425 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
426 if (!timing)
427 return -ENOMEM;
428
429 ret = of_get_display_timing(np, "panel-timing", timing);
430 if (ret < 0) {
431 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
432 np);
433 return ret;
434 }
435
436 desc->timings = timing;
437 desc->num_timings = 1;
438
439 of_property_read_u32(np, "width-mm", &desc->size.width);
440 of_property_read_u32(np, "height-mm", &desc->size.height);
441
442 /* Extract bus_flags from display_timing */
443 bus_flags = 0;
444 vm.flags = timing->flags;
445 drm_bus_flags_from_videomode(&vm, &bus_flags);
446 desc->bus_flags = bus_flags;
447
448 /* We do not know the connector for the DT node, so guess it */
449 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
450
451 panel->desc = desc;
452
453 return 0;
454 }
455
456 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
457 (to_check->field.typ >= bounds->field.min && \
458 to_check->field.typ <= bounds->field.max)
panel_simple_parse_panel_timing_node(struct device * dev,struct panel_simple * panel,const struct display_timing * ot)459 static void panel_simple_parse_panel_timing_node(struct device *dev,
460 struct panel_simple *panel,
461 const struct display_timing *ot)
462 {
463 const struct panel_desc *desc = panel->desc;
464 struct videomode vm;
465 unsigned int i;
466
467 if (WARN_ON(desc->num_modes)) {
468 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
469 return;
470 }
471 if (WARN_ON(!desc->num_timings)) {
472 dev_err(dev, "Reject override mode: no timings specified\n");
473 return;
474 }
475
476 for (i = 0; i < panel->desc->num_timings; i++) {
477 const struct display_timing *dt = &panel->desc->timings[i];
478
479 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
487 continue;
488
489 if (ot->flags != dt->flags)
490 continue;
491
492 videomode_from_timing(ot, &vm);
493 drm_display_mode_from_videomode(&vm, &panel->override_mode);
494 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
495 DRM_MODE_TYPE_PREFERRED;
496 break;
497 }
498
499 if (WARN_ON(!panel->override_mode.type))
500 dev_err(dev, "Reject override mode: No display_timing found\n");
501 }
502
panel_simple_probe(struct device * dev,const struct panel_desc * desc)503 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
504 {
505 struct panel_simple *panel;
506 struct display_timing dt;
507 struct device_node *ddc;
508 int connector_type;
509 u32 bus_flags;
510 int err;
511
512 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
513 if (!panel)
514 return -ENOMEM;
515
516 panel->enabled = false;
517 panel->prepared = false;
518 panel->desc = desc;
519
520 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
521 if (!panel->no_hpd) {
522 err = panel_simple_get_hpd_gpio(dev, panel, true);
523 if (err)
524 return err;
525 }
526
527 panel->supply = devm_regulator_get(dev, "power");
528 if (IS_ERR(panel->supply))
529 return PTR_ERR(panel->supply);
530
531 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
532 GPIOD_OUT_LOW);
533 if (IS_ERR(panel->enable_gpio)) {
534 err = PTR_ERR(panel->enable_gpio);
535 if (err != -EPROBE_DEFER)
536 dev_err(dev, "failed to request GPIO: %d\n", err);
537 return err;
538 }
539
540 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
541 if (err) {
542 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
543 return err;
544 }
545
546 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
547 if (ddc) {
548 panel->ddc = of_find_i2c_adapter_by_node(ddc);
549 of_node_put(ddc);
550
551 if (!panel->ddc)
552 return -EPROBE_DEFER;
553 }
554
555 if (desc == &panel_dpi) {
556 /* Handle the generic panel-dpi binding */
557 err = panel_dpi_probe(dev, panel);
558 if (err)
559 goto free_ddc;
560 desc = panel->desc;
561 } else {
562 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
563 panel_simple_parse_panel_timing_node(dev, panel, &dt);
564 }
565
566 connector_type = desc->connector_type;
567 /* Catch common mistakes for panels. */
568 switch (connector_type) {
569 case 0:
570 dev_warn(dev, "Specify missing connector_type\n");
571 connector_type = DRM_MODE_CONNECTOR_DPI;
572 break;
573 case DRM_MODE_CONNECTOR_LVDS:
574 WARN_ON(desc->bus_flags &
575 ~(DRM_BUS_FLAG_DE_LOW |
576 DRM_BUS_FLAG_DE_HIGH |
577 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
578 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
579 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
580 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
581 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
582 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
583 desc->bpc != 6);
584 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
585 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
586 desc->bpc != 8);
587 break;
588 case DRM_MODE_CONNECTOR_eDP:
589 if (desc->bus_format == 0)
590 dev_warn(dev, "Specify missing bus_format\n");
591 if (desc->bpc != 6 && desc->bpc != 8)
592 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
593 break;
594 case DRM_MODE_CONNECTOR_DSI:
595 if (desc->bpc != 6 && desc->bpc != 8)
596 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
597 break;
598 case DRM_MODE_CONNECTOR_DPI:
599 bus_flags = DRM_BUS_FLAG_DE_LOW |
600 DRM_BUS_FLAG_DE_HIGH |
601 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
602 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
603 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
604 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
605 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
606 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
607 if (desc->bus_flags & ~bus_flags)
608 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
609 if (!(desc->bus_flags & bus_flags))
610 dev_warn(dev, "Specify missing bus_flags\n");
611 if (desc->bus_format == 0)
612 dev_warn(dev, "Specify missing bus_format\n");
613 if (desc->bpc != 6 && desc->bpc != 8)
614 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
615 break;
616 default:
617 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
618 connector_type = DRM_MODE_CONNECTOR_DPI;
619 break;
620 }
621
622 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
623
624 err = drm_panel_of_backlight(&panel->base);
625 if (err)
626 goto free_ddc;
627
628 drm_panel_add(&panel->base);
629
630 dev_set_drvdata(dev, panel);
631
632 return 0;
633
634 free_ddc:
635 if (panel->ddc)
636 put_device(&panel->ddc->dev);
637
638 return err;
639 }
640
panel_simple_remove(struct device * dev)641 static int panel_simple_remove(struct device *dev)
642 {
643 struct panel_simple *panel = dev_get_drvdata(dev);
644
645 drm_panel_remove(&panel->base);
646 drm_panel_disable(&panel->base);
647 drm_panel_unprepare(&panel->base);
648
649 if (panel->ddc)
650 put_device(&panel->ddc->dev);
651
652 return 0;
653 }
654
panel_simple_shutdown(struct device * dev)655 static void panel_simple_shutdown(struct device *dev)
656 {
657 struct panel_simple *panel = dev_get_drvdata(dev);
658
659 drm_panel_disable(&panel->base);
660 drm_panel_unprepare(&panel->base);
661 }
662
663 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
664 .clock = 71100,
665 .hdisplay = 1280,
666 .hsync_start = 1280 + 40,
667 .hsync_end = 1280 + 40 + 80,
668 .htotal = 1280 + 40 + 80 + 40,
669 .vdisplay = 800,
670 .vsync_start = 800 + 3,
671 .vsync_end = 800 + 3 + 10,
672 .vtotal = 800 + 3 + 10 + 10,
673 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
674 };
675
676 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
677 .modes = &ire_am_1280800n3tzqw_t00h_mode,
678 .num_modes = 1,
679 .bpc = 8,
680 .size = {
681 .width = 217,
682 .height = 136,
683 },
684 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
685 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
686 .connector_type = DRM_MODE_CONNECTOR_LVDS,
687 };
688
689 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
690 .clock = 9000,
691 .hdisplay = 480,
692 .hsync_start = 480 + 2,
693 .hsync_end = 480 + 2 + 41,
694 .htotal = 480 + 2 + 41 + 2,
695 .vdisplay = 272,
696 .vsync_start = 272 + 2,
697 .vsync_end = 272 + 2 + 10,
698 .vtotal = 272 + 2 + 10 + 2,
699 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
700 };
701
702 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
703 .modes = &ire_am_480272h3tmqw_t01h_mode,
704 .num_modes = 1,
705 .bpc = 8,
706 .size = {
707 .width = 105,
708 .height = 67,
709 },
710 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
711 };
712
713 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
714 .clock = 33333,
715 .hdisplay = 800,
716 .hsync_start = 800 + 0,
717 .hsync_end = 800 + 0 + 255,
718 .htotal = 800 + 0 + 255 + 0,
719 .vdisplay = 480,
720 .vsync_start = 480 + 2,
721 .vsync_end = 480 + 2 + 45,
722 .vtotal = 480 + 2 + 45 + 0,
723 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
724 };
725
726 static const struct panel_desc ampire_am800480r3tmqwa1h = {
727 .modes = &ire_am800480r3tmqwa1h_mode,
728 .num_modes = 1,
729 .bpc = 6,
730 .size = {
731 .width = 152,
732 .height = 91,
733 },
734 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
735 };
736
737 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
738 .pixelclock = { 26400000, 33300000, 46800000 },
739 .hactive = { 800, 800, 800 },
740 .hfront_porch = { 16, 210, 354 },
741 .hback_porch = { 45, 36, 6 },
742 .hsync_len = { 1, 10, 40 },
743 .vactive = { 480, 480, 480 },
744 .vfront_porch = { 7, 22, 147 },
745 .vback_porch = { 22, 13, 3 },
746 .vsync_len = { 1, 10, 20 },
747 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
748 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
749 };
750
751 static const struct panel_desc armadeus_st0700_adapt = {
752 .timings = &santek_st0700i5y_rbslw_f_timing,
753 .num_timings = 1,
754 .bpc = 6,
755 .size = {
756 .width = 154,
757 .height = 86,
758 },
759 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
760 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
761 };
762
763 static const struct drm_display_mode auo_b101aw03_mode = {
764 .clock = 51450,
765 .hdisplay = 1024,
766 .hsync_start = 1024 + 156,
767 .hsync_end = 1024 + 156 + 8,
768 .htotal = 1024 + 156 + 8 + 156,
769 .vdisplay = 600,
770 .vsync_start = 600 + 16,
771 .vsync_end = 600 + 16 + 6,
772 .vtotal = 600 + 16 + 6 + 16,
773 };
774
775 static const struct panel_desc auo_b101aw03 = {
776 .modes = &auo_b101aw03_mode,
777 .num_modes = 1,
778 .bpc = 6,
779 .size = {
780 .width = 223,
781 .height = 125,
782 },
783 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
784 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
785 .connector_type = DRM_MODE_CONNECTOR_LVDS,
786 };
787
788 static const struct display_timing auo_b101ean01_timing = {
789 .pixelclock = { 65300000, 72500000, 75000000 },
790 .hactive = { 1280, 1280, 1280 },
791 .hfront_porch = { 18, 119, 119 },
792 .hback_porch = { 21, 21, 21 },
793 .hsync_len = { 32, 32, 32 },
794 .vactive = { 800, 800, 800 },
795 .vfront_porch = { 4, 4, 4 },
796 .vback_porch = { 8, 8, 8 },
797 .vsync_len = { 18, 20, 20 },
798 };
799
800 static const struct panel_desc auo_b101ean01 = {
801 .timings = &auo_b101ean01_timing,
802 .num_timings = 1,
803 .bpc = 6,
804 .size = {
805 .width = 217,
806 .height = 136,
807 },
808 };
809
810 static const struct drm_display_mode auo_b101xtn01_mode = {
811 .clock = 72000,
812 .hdisplay = 1366,
813 .hsync_start = 1366 + 20,
814 .hsync_end = 1366 + 20 + 70,
815 .htotal = 1366 + 20 + 70,
816 .vdisplay = 768,
817 .vsync_start = 768 + 14,
818 .vsync_end = 768 + 14 + 42,
819 .vtotal = 768 + 14 + 42,
820 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
821 };
822
823 static const struct panel_desc auo_b101xtn01 = {
824 .modes = &auo_b101xtn01_mode,
825 .num_modes = 1,
826 .bpc = 6,
827 .size = {
828 .width = 223,
829 .height = 125,
830 },
831 };
832
833 static const struct drm_display_mode auo_b116xak01_mode = {
834 .clock = 69300,
835 .hdisplay = 1366,
836 .hsync_start = 1366 + 48,
837 .hsync_end = 1366 + 48 + 32,
838 .htotal = 1366 + 48 + 32 + 10,
839 .vdisplay = 768,
840 .vsync_start = 768 + 4,
841 .vsync_end = 768 + 4 + 6,
842 .vtotal = 768 + 4 + 6 + 15,
843 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
844 };
845
846 static const struct panel_desc auo_b116xak01 = {
847 .modes = &auo_b116xak01_mode,
848 .num_modes = 1,
849 .bpc = 6,
850 .size = {
851 .width = 256,
852 .height = 144,
853 },
854 .delay = {
855 .hpd_absent_delay = 200,
856 },
857 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
858 .connector_type = DRM_MODE_CONNECTOR_eDP,
859 };
860
861 static const struct drm_display_mode auo_b116xw03_mode = {
862 .clock = 70589,
863 .hdisplay = 1366,
864 .hsync_start = 1366 + 40,
865 .hsync_end = 1366 + 40 + 40,
866 .htotal = 1366 + 40 + 40 + 32,
867 .vdisplay = 768,
868 .vsync_start = 768 + 10,
869 .vsync_end = 768 + 10 + 12,
870 .vtotal = 768 + 10 + 12 + 6,
871 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
872 };
873
874 static const struct panel_desc auo_b116xw03 = {
875 .modes = &auo_b116xw03_mode,
876 .num_modes = 1,
877 .bpc = 6,
878 .size = {
879 .width = 256,
880 .height = 144,
881 },
882 .delay = {
883 .enable = 400,
884 },
885 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
886 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
887 .connector_type = DRM_MODE_CONNECTOR_eDP,
888 };
889
890 static const struct drm_display_mode auo_b133xtn01_mode = {
891 .clock = 69500,
892 .hdisplay = 1366,
893 .hsync_start = 1366 + 48,
894 .hsync_end = 1366 + 48 + 32,
895 .htotal = 1366 + 48 + 32 + 20,
896 .vdisplay = 768,
897 .vsync_start = 768 + 3,
898 .vsync_end = 768 + 3 + 6,
899 .vtotal = 768 + 3 + 6 + 13,
900 };
901
902 static const struct panel_desc auo_b133xtn01 = {
903 .modes = &auo_b133xtn01_mode,
904 .num_modes = 1,
905 .bpc = 6,
906 .size = {
907 .width = 293,
908 .height = 165,
909 },
910 };
911
912 static const struct drm_display_mode auo_b133htn01_mode = {
913 .clock = 150660,
914 .hdisplay = 1920,
915 .hsync_start = 1920 + 172,
916 .hsync_end = 1920 + 172 + 80,
917 .htotal = 1920 + 172 + 80 + 60,
918 .vdisplay = 1080,
919 .vsync_start = 1080 + 25,
920 .vsync_end = 1080 + 25 + 10,
921 .vtotal = 1080 + 25 + 10 + 10,
922 };
923
924 static const struct panel_desc auo_b133htn01 = {
925 .modes = &auo_b133htn01_mode,
926 .num_modes = 1,
927 .bpc = 6,
928 .size = {
929 .width = 293,
930 .height = 165,
931 },
932 .delay = {
933 .prepare = 105,
934 .enable = 20,
935 .unprepare = 50,
936 },
937 };
938
939 static const struct display_timing auo_g070vvn01_timings = {
940 .pixelclock = { 33300000, 34209000, 45000000 },
941 .hactive = { 800, 800, 800 },
942 .hfront_porch = { 20, 40, 200 },
943 .hback_porch = { 87, 40, 1 },
944 .hsync_len = { 1, 48, 87 },
945 .vactive = { 480, 480, 480 },
946 .vfront_porch = { 5, 13, 200 },
947 .vback_porch = { 31, 31, 29 },
948 .vsync_len = { 1, 1, 3 },
949 };
950
951 static const struct panel_desc auo_g070vvn01 = {
952 .timings = &auo_g070vvn01_timings,
953 .num_timings = 1,
954 .bpc = 8,
955 .size = {
956 .width = 152,
957 .height = 91,
958 },
959 .delay = {
960 .prepare = 200,
961 .enable = 50,
962 .disable = 50,
963 .unprepare = 1000,
964 },
965 };
966
967 static const struct drm_display_mode auo_g101evn010_mode = {
968 .clock = 68930,
969 .hdisplay = 1280,
970 .hsync_start = 1280 + 82,
971 .hsync_end = 1280 + 82 + 2,
972 .htotal = 1280 + 82 + 2 + 84,
973 .vdisplay = 800,
974 .vsync_start = 800 + 8,
975 .vsync_end = 800 + 8 + 2,
976 .vtotal = 800 + 8 + 2 + 6,
977 };
978
979 static const struct panel_desc auo_g101evn010 = {
980 .modes = &auo_g101evn010_mode,
981 .num_modes = 1,
982 .bpc = 6,
983 .size = {
984 .width = 216,
985 .height = 135,
986 },
987 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
988 .connector_type = DRM_MODE_CONNECTOR_LVDS,
989 };
990
991 static const struct drm_display_mode auo_g104sn02_mode = {
992 .clock = 40000,
993 .hdisplay = 800,
994 .hsync_start = 800 + 40,
995 .hsync_end = 800 + 40 + 216,
996 .htotal = 800 + 40 + 216 + 128,
997 .vdisplay = 600,
998 .vsync_start = 600 + 10,
999 .vsync_end = 600 + 10 + 35,
1000 .vtotal = 600 + 10 + 35 + 2,
1001 };
1002
1003 static const struct panel_desc auo_g104sn02 = {
1004 .modes = &auo_g104sn02_mode,
1005 .num_modes = 1,
1006 .bpc = 8,
1007 .size = {
1008 .width = 211,
1009 .height = 158,
1010 },
1011 };
1012
1013 static const struct drm_display_mode auo_g121ean01_mode = {
1014 .clock = 66700,
1015 .hdisplay = 1280,
1016 .hsync_start = 1280 + 58,
1017 .hsync_end = 1280 + 58 + 8,
1018 .htotal = 1280 + 58 + 8 + 70,
1019 .vdisplay = 800,
1020 .vsync_start = 800 + 6,
1021 .vsync_end = 800 + 6 + 4,
1022 .vtotal = 800 + 6 + 4 + 10,
1023 };
1024
1025 static const struct panel_desc auo_g121ean01 = {
1026 .modes = &auo_g121ean01_mode,
1027 .num_modes = 1,
1028 .bpc = 8,
1029 .size = {
1030 .width = 261,
1031 .height = 163,
1032 },
1033 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1034 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1035 };
1036
1037 static const struct display_timing auo_g133han01_timings = {
1038 .pixelclock = { 134000000, 141200000, 149000000 },
1039 .hactive = { 1920, 1920, 1920 },
1040 .hfront_porch = { 39, 58, 77 },
1041 .hback_porch = { 59, 88, 117 },
1042 .hsync_len = { 28, 42, 56 },
1043 .vactive = { 1080, 1080, 1080 },
1044 .vfront_porch = { 3, 8, 11 },
1045 .vback_porch = { 5, 14, 19 },
1046 .vsync_len = { 4, 14, 19 },
1047 };
1048
1049 static const struct panel_desc auo_g133han01 = {
1050 .timings = &auo_g133han01_timings,
1051 .num_timings = 1,
1052 .bpc = 8,
1053 .size = {
1054 .width = 293,
1055 .height = 165,
1056 },
1057 .delay = {
1058 .prepare = 200,
1059 .enable = 50,
1060 .disable = 50,
1061 .unprepare = 1000,
1062 },
1063 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1064 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1065 };
1066
1067 static const struct drm_display_mode auo_g156xtn01_mode = {
1068 .clock = 76000,
1069 .hdisplay = 1366,
1070 .hsync_start = 1366 + 33,
1071 .hsync_end = 1366 + 33 + 67,
1072 .htotal = 1560,
1073 .vdisplay = 768,
1074 .vsync_start = 768 + 4,
1075 .vsync_end = 768 + 4 + 4,
1076 .vtotal = 806,
1077 };
1078
1079 static const struct panel_desc auo_g156xtn01 = {
1080 .modes = &auo_g156xtn01_mode,
1081 .num_modes = 1,
1082 .bpc = 8,
1083 .size = {
1084 .width = 344,
1085 .height = 194,
1086 },
1087 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1088 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1089 };
1090
1091 static const struct display_timing auo_g185han01_timings = {
1092 .pixelclock = { 120000000, 144000000, 175000000 },
1093 .hactive = { 1920, 1920, 1920 },
1094 .hfront_porch = { 36, 120, 148 },
1095 .hback_porch = { 24, 88, 108 },
1096 .hsync_len = { 20, 48, 64 },
1097 .vactive = { 1080, 1080, 1080 },
1098 .vfront_porch = { 6, 10, 40 },
1099 .vback_porch = { 2, 5, 20 },
1100 .vsync_len = { 2, 5, 20 },
1101 };
1102
1103 static const struct panel_desc auo_g185han01 = {
1104 .timings = &auo_g185han01_timings,
1105 .num_timings = 1,
1106 .bpc = 8,
1107 .size = {
1108 .width = 409,
1109 .height = 230,
1110 },
1111 .delay = {
1112 .prepare = 50,
1113 .enable = 200,
1114 .disable = 110,
1115 .unprepare = 1000,
1116 },
1117 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1118 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1119 };
1120
1121 static const struct display_timing auo_g190ean01_timings = {
1122 .pixelclock = { 90000000, 108000000, 135000000 },
1123 .hactive = { 1280, 1280, 1280 },
1124 .hfront_porch = { 126, 184, 1266 },
1125 .hback_porch = { 84, 122, 844 },
1126 .hsync_len = { 70, 102, 704 },
1127 .vactive = { 1024, 1024, 1024 },
1128 .vfront_porch = { 4, 26, 76 },
1129 .vback_porch = { 2, 8, 25 },
1130 .vsync_len = { 2, 8, 25 },
1131 };
1132
1133 static const struct panel_desc auo_g190ean01 = {
1134 .timings = &auo_g190ean01_timings,
1135 .num_timings = 1,
1136 .bpc = 8,
1137 .size = {
1138 .width = 376,
1139 .height = 301,
1140 },
1141 .delay = {
1142 .prepare = 50,
1143 .enable = 200,
1144 .disable = 110,
1145 .unprepare = 1000,
1146 },
1147 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1148 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1149 };
1150
1151 static const struct display_timing auo_p320hvn03_timings = {
1152 .pixelclock = { 106000000, 148500000, 164000000 },
1153 .hactive = { 1920, 1920, 1920 },
1154 .hfront_porch = { 25, 50, 130 },
1155 .hback_porch = { 25, 50, 130 },
1156 .hsync_len = { 20, 40, 105 },
1157 .vactive = { 1080, 1080, 1080 },
1158 .vfront_porch = { 8, 17, 150 },
1159 .vback_porch = { 8, 17, 150 },
1160 .vsync_len = { 4, 11, 100 },
1161 };
1162
1163 static const struct panel_desc auo_p320hvn03 = {
1164 .timings = &auo_p320hvn03_timings,
1165 .num_timings = 1,
1166 .bpc = 8,
1167 .size = {
1168 .width = 698,
1169 .height = 393,
1170 },
1171 .delay = {
1172 .prepare = 1,
1173 .enable = 450,
1174 .unprepare = 500,
1175 },
1176 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1177 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1178 };
1179
1180 static const struct drm_display_mode auo_t215hvn01_mode = {
1181 .clock = 148800,
1182 .hdisplay = 1920,
1183 .hsync_start = 1920 + 88,
1184 .hsync_end = 1920 + 88 + 44,
1185 .htotal = 1920 + 88 + 44 + 148,
1186 .vdisplay = 1080,
1187 .vsync_start = 1080 + 4,
1188 .vsync_end = 1080 + 4 + 5,
1189 .vtotal = 1080 + 4 + 5 + 36,
1190 };
1191
1192 static const struct panel_desc auo_t215hvn01 = {
1193 .modes = &auo_t215hvn01_mode,
1194 .num_modes = 1,
1195 .bpc = 8,
1196 .size = {
1197 .width = 430,
1198 .height = 270,
1199 },
1200 .delay = {
1201 .disable = 5,
1202 .unprepare = 1000,
1203 }
1204 };
1205
1206 static const struct drm_display_mode avic_tm070ddh03_mode = {
1207 .clock = 51200,
1208 .hdisplay = 1024,
1209 .hsync_start = 1024 + 160,
1210 .hsync_end = 1024 + 160 + 4,
1211 .htotal = 1024 + 160 + 4 + 156,
1212 .vdisplay = 600,
1213 .vsync_start = 600 + 17,
1214 .vsync_end = 600 + 17 + 1,
1215 .vtotal = 600 + 17 + 1 + 17,
1216 };
1217
1218 static const struct panel_desc avic_tm070ddh03 = {
1219 .modes = &avic_tm070ddh03_mode,
1220 .num_modes = 1,
1221 .bpc = 8,
1222 .size = {
1223 .width = 154,
1224 .height = 90,
1225 },
1226 .delay = {
1227 .prepare = 20,
1228 .enable = 200,
1229 .disable = 200,
1230 },
1231 };
1232
1233 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1234 .clock = 30000,
1235 .hdisplay = 800,
1236 .hsync_start = 800 + 40,
1237 .hsync_end = 800 + 40 + 48,
1238 .htotal = 800 + 40 + 48 + 40,
1239 .vdisplay = 480,
1240 .vsync_start = 480 + 13,
1241 .vsync_end = 480 + 13 + 3,
1242 .vtotal = 480 + 13 + 3 + 29,
1243 };
1244
1245 static const struct panel_desc bananapi_s070wv20_ct16 = {
1246 .modes = &bananapi_s070wv20_ct16_mode,
1247 .num_modes = 1,
1248 .bpc = 6,
1249 .size = {
1250 .width = 154,
1251 .height = 86,
1252 },
1253 };
1254
1255 static const struct drm_display_mode boe_hv070wsa_mode = {
1256 .clock = 42105,
1257 .hdisplay = 1024,
1258 .hsync_start = 1024 + 30,
1259 .hsync_end = 1024 + 30 + 30,
1260 .htotal = 1024 + 30 + 30 + 30,
1261 .vdisplay = 600,
1262 .vsync_start = 600 + 10,
1263 .vsync_end = 600 + 10 + 10,
1264 .vtotal = 600 + 10 + 10 + 10,
1265 };
1266
1267 static const struct panel_desc boe_hv070wsa = {
1268 .modes = &boe_hv070wsa_mode,
1269 .num_modes = 1,
1270 .bpc = 8,
1271 .size = {
1272 .width = 154,
1273 .height = 90,
1274 },
1275 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1276 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1277 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1278 };
1279
1280 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1281 {
1282 .clock = 71900,
1283 .hdisplay = 1280,
1284 .hsync_start = 1280 + 48,
1285 .hsync_end = 1280 + 48 + 32,
1286 .htotal = 1280 + 48 + 32 + 80,
1287 .vdisplay = 800,
1288 .vsync_start = 800 + 3,
1289 .vsync_end = 800 + 3 + 5,
1290 .vtotal = 800 + 3 + 5 + 24,
1291 },
1292 {
1293 .clock = 57500,
1294 .hdisplay = 1280,
1295 .hsync_start = 1280 + 48,
1296 .hsync_end = 1280 + 48 + 32,
1297 .htotal = 1280 + 48 + 32 + 80,
1298 .vdisplay = 800,
1299 .vsync_start = 800 + 3,
1300 .vsync_end = 800 + 3 + 5,
1301 .vtotal = 800 + 3 + 5 + 24,
1302 },
1303 };
1304
1305 static const struct panel_desc boe_nv101wxmn51 = {
1306 .modes = boe_nv101wxmn51_modes,
1307 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1308 .bpc = 8,
1309 .size = {
1310 .width = 217,
1311 .height = 136,
1312 },
1313 .delay = {
1314 .prepare = 210,
1315 .enable = 50,
1316 .unprepare = 160,
1317 },
1318 };
1319
1320 /* Also used for boe_nv133fhm_n62 */
1321 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1322 .clock = 147840,
1323 .hdisplay = 1920,
1324 .hsync_start = 1920 + 48,
1325 .hsync_end = 1920 + 48 + 32,
1326 .htotal = 1920 + 48 + 32 + 200,
1327 .vdisplay = 1080,
1328 .vsync_start = 1080 + 3,
1329 .vsync_end = 1080 + 3 + 6,
1330 .vtotal = 1080 + 3 + 6 + 31,
1331 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1332 };
1333
1334 /* Also used for boe_nv133fhm_n62 */
1335 static const struct panel_desc boe_nv133fhm_n61 = {
1336 .modes = &boe_nv133fhm_n61_modes,
1337 .num_modes = 1,
1338 .bpc = 6,
1339 .size = {
1340 .width = 294,
1341 .height = 165,
1342 },
1343 .delay = {
1344 /*
1345 * When power is first given to the panel there's a short
1346 * spike on the HPD line. It was explained that this spike
1347 * was until the TCON data download was complete. On
1348 * one system this was measured at 8 ms. We'll put 15 ms
1349 * in the prepare delay just to be safe and take it away
1350 * from the hpd_absent_delay (which would otherwise be 200 ms)
1351 * to handle this. That means:
1352 * - If HPD isn't hooked up you still have 200 ms delay.
1353 * - If HPD is hooked up we won't try to look at it for the
1354 * first 15 ms.
1355 */
1356 .prepare = 15,
1357 .hpd_absent_delay = 185,
1358
1359 .unprepare = 500,
1360 },
1361 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1362 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1363 .connector_type = DRM_MODE_CONNECTOR_eDP,
1364 };
1365
1366 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1367 {
1368 .clock = 148500,
1369 .hdisplay = 1920,
1370 .hsync_start = 1920 + 48,
1371 .hsync_end = 1920 + 48 + 32,
1372 .htotal = 2200,
1373 .vdisplay = 1080,
1374 .vsync_start = 1080 + 3,
1375 .vsync_end = 1080 + 3 + 5,
1376 .vtotal = 1125,
1377 },
1378 };
1379
1380 static const struct panel_desc boe_nv140fhmn49 = {
1381 .modes = boe_nv140fhmn49_modes,
1382 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1383 .bpc = 6,
1384 .size = {
1385 .width = 309,
1386 .height = 174,
1387 },
1388 .delay = {
1389 .prepare = 210,
1390 .enable = 50,
1391 .unprepare = 160,
1392 },
1393 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1394 .connector_type = DRM_MODE_CONNECTOR_eDP,
1395 };
1396
1397 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1398 .clock = 9000,
1399 .hdisplay = 480,
1400 .hsync_start = 480 + 5,
1401 .hsync_end = 480 + 5 + 5,
1402 .htotal = 480 + 5 + 5 + 40,
1403 .vdisplay = 272,
1404 .vsync_start = 272 + 8,
1405 .vsync_end = 272 + 8 + 8,
1406 .vtotal = 272 + 8 + 8 + 8,
1407 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1408 };
1409
1410 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1411 .modes = &cdtech_s043wq26h_ct7_mode,
1412 .num_modes = 1,
1413 .bpc = 8,
1414 .size = {
1415 .width = 95,
1416 .height = 54,
1417 },
1418 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1419 };
1420
1421 /* S070PWS19HP-FC21 2017/04/22 */
1422 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1423 .clock = 51200,
1424 .hdisplay = 1024,
1425 .hsync_start = 1024 + 160,
1426 .hsync_end = 1024 + 160 + 20,
1427 .htotal = 1024 + 160 + 20 + 140,
1428 .vdisplay = 600,
1429 .vsync_start = 600 + 12,
1430 .vsync_end = 600 + 12 + 3,
1431 .vtotal = 600 + 12 + 3 + 20,
1432 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1433 };
1434
1435 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1436 .modes = &cdtech_s070pws19hp_fc21_mode,
1437 .num_modes = 1,
1438 .bpc = 6,
1439 .size = {
1440 .width = 154,
1441 .height = 86,
1442 },
1443 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1444 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1445 .connector_type = DRM_MODE_CONNECTOR_DPI,
1446 };
1447
1448 /* S070SWV29HG-DC44 2017/09/21 */
1449 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1450 .clock = 33300,
1451 .hdisplay = 800,
1452 .hsync_start = 800 + 210,
1453 .hsync_end = 800 + 210 + 2,
1454 .htotal = 800 + 210 + 2 + 44,
1455 .vdisplay = 480,
1456 .vsync_start = 480 + 22,
1457 .vsync_end = 480 + 22 + 2,
1458 .vtotal = 480 + 22 + 2 + 21,
1459 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1460 };
1461
1462 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1463 .modes = &cdtech_s070swv29hg_dc44_mode,
1464 .num_modes = 1,
1465 .bpc = 6,
1466 .size = {
1467 .width = 154,
1468 .height = 86,
1469 },
1470 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1471 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1472 .connector_type = DRM_MODE_CONNECTOR_DPI,
1473 };
1474
1475 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1476 .clock = 35000,
1477 .hdisplay = 800,
1478 .hsync_start = 800 + 40,
1479 .hsync_end = 800 + 40 + 40,
1480 .htotal = 800 + 40 + 40 + 48,
1481 .vdisplay = 480,
1482 .vsync_start = 480 + 29,
1483 .vsync_end = 480 + 29 + 13,
1484 .vtotal = 480 + 29 + 13 + 3,
1485 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1486 };
1487
1488 static const struct panel_desc cdtech_s070wv95_ct16 = {
1489 .modes = &cdtech_s070wv95_ct16_mode,
1490 .num_modes = 1,
1491 .bpc = 8,
1492 .size = {
1493 .width = 154,
1494 .height = 85,
1495 },
1496 };
1497
1498 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1499 .pixelclock = { 68900000, 71100000, 73400000 },
1500 .hactive = { 1280, 1280, 1280 },
1501 .hfront_porch = { 65, 80, 95 },
1502 .hback_porch = { 64, 79, 94 },
1503 .hsync_len = { 1, 1, 1 },
1504 .vactive = { 800, 800, 800 },
1505 .vfront_porch = { 7, 11, 14 },
1506 .vback_porch = { 7, 11, 14 },
1507 .vsync_len = { 1, 1, 1 },
1508 .flags = DISPLAY_FLAGS_DE_HIGH,
1509 };
1510
1511 static const struct panel_desc chefree_ch101olhlwh_002 = {
1512 .timings = &chefree_ch101olhlwh_002_timing,
1513 .num_timings = 1,
1514 .bpc = 8,
1515 .size = {
1516 .width = 217,
1517 .height = 135,
1518 },
1519 .delay = {
1520 .enable = 200,
1521 .disable = 200,
1522 },
1523 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1524 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1525 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1526 };
1527
1528 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1529 .clock = 66770,
1530 .hdisplay = 800,
1531 .hsync_start = 800 + 49,
1532 .hsync_end = 800 + 49 + 33,
1533 .htotal = 800 + 49 + 33 + 17,
1534 .vdisplay = 1280,
1535 .vsync_start = 1280 + 1,
1536 .vsync_end = 1280 + 1 + 7,
1537 .vtotal = 1280 + 1 + 7 + 15,
1538 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1539 };
1540
1541 static const struct panel_desc chunghwa_claa070wp03xg = {
1542 .modes = &chunghwa_claa070wp03xg_mode,
1543 .num_modes = 1,
1544 .bpc = 6,
1545 .size = {
1546 .width = 94,
1547 .height = 150,
1548 },
1549 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1550 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1551 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1552 };
1553
1554 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1555 .clock = 72070,
1556 .hdisplay = 1366,
1557 .hsync_start = 1366 + 58,
1558 .hsync_end = 1366 + 58 + 58,
1559 .htotal = 1366 + 58 + 58 + 58,
1560 .vdisplay = 768,
1561 .vsync_start = 768 + 4,
1562 .vsync_end = 768 + 4 + 4,
1563 .vtotal = 768 + 4 + 4 + 4,
1564 };
1565
1566 static const struct panel_desc chunghwa_claa101wa01a = {
1567 .modes = &chunghwa_claa101wa01a_mode,
1568 .num_modes = 1,
1569 .bpc = 6,
1570 .size = {
1571 .width = 220,
1572 .height = 120,
1573 },
1574 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1575 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1576 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1577 };
1578
1579 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1580 .clock = 69300,
1581 .hdisplay = 1366,
1582 .hsync_start = 1366 + 48,
1583 .hsync_end = 1366 + 48 + 32,
1584 .htotal = 1366 + 48 + 32 + 20,
1585 .vdisplay = 768,
1586 .vsync_start = 768 + 16,
1587 .vsync_end = 768 + 16 + 8,
1588 .vtotal = 768 + 16 + 8 + 16,
1589 };
1590
1591 static const struct panel_desc chunghwa_claa101wb01 = {
1592 .modes = &chunghwa_claa101wb01_mode,
1593 .num_modes = 1,
1594 .bpc = 6,
1595 .size = {
1596 .width = 223,
1597 .height = 125,
1598 },
1599 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1600 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1601 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1602 };
1603
1604 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1605 .clock = 33260,
1606 .hdisplay = 800,
1607 .hsync_start = 800 + 40,
1608 .hsync_end = 800 + 40 + 128,
1609 .htotal = 800 + 40 + 128 + 88,
1610 .vdisplay = 480,
1611 .vsync_start = 480 + 10,
1612 .vsync_end = 480 + 10 + 2,
1613 .vtotal = 480 + 10 + 2 + 33,
1614 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1615 };
1616
1617 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1618 .modes = &dataimage_scf0700c48ggu18_mode,
1619 .num_modes = 1,
1620 .bpc = 8,
1621 .size = {
1622 .width = 152,
1623 .height = 91,
1624 },
1625 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1626 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1627 };
1628
1629 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1630 .pixelclock = { 45000000, 51200000, 57000000 },
1631 .hactive = { 1024, 1024, 1024 },
1632 .hfront_porch = { 100, 106, 113 },
1633 .hback_porch = { 100, 106, 113 },
1634 .hsync_len = { 100, 108, 114 },
1635 .vactive = { 600, 600, 600 },
1636 .vfront_porch = { 8, 11, 15 },
1637 .vback_porch = { 8, 11, 15 },
1638 .vsync_len = { 9, 13, 15 },
1639 .flags = DISPLAY_FLAGS_DE_HIGH,
1640 };
1641
1642 static const struct panel_desc dlc_dlc0700yzg_1 = {
1643 .timings = &dlc_dlc0700yzg_1_timing,
1644 .num_timings = 1,
1645 .bpc = 6,
1646 .size = {
1647 .width = 154,
1648 .height = 86,
1649 },
1650 .delay = {
1651 .prepare = 30,
1652 .enable = 200,
1653 .disable = 200,
1654 },
1655 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1656 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1657 };
1658
1659 static const struct display_timing dlc_dlc1010gig_timing = {
1660 .pixelclock = { 68900000, 71100000, 73400000 },
1661 .hactive = { 1280, 1280, 1280 },
1662 .hfront_porch = { 43, 53, 63 },
1663 .hback_porch = { 43, 53, 63 },
1664 .hsync_len = { 44, 54, 64 },
1665 .vactive = { 800, 800, 800 },
1666 .vfront_porch = { 5, 8, 11 },
1667 .vback_porch = { 5, 8, 11 },
1668 .vsync_len = { 5, 7, 11 },
1669 .flags = DISPLAY_FLAGS_DE_HIGH,
1670 };
1671
1672 static const struct panel_desc dlc_dlc1010gig = {
1673 .timings = &dlc_dlc1010gig_timing,
1674 .num_timings = 1,
1675 .bpc = 8,
1676 .size = {
1677 .width = 216,
1678 .height = 135,
1679 },
1680 .delay = {
1681 .prepare = 60,
1682 .enable = 150,
1683 .disable = 100,
1684 .unprepare = 60,
1685 },
1686 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1687 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1688 };
1689
1690 static const struct drm_display_mode edt_et035012dm6_mode = {
1691 .clock = 6500,
1692 .hdisplay = 320,
1693 .hsync_start = 320 + 20,
1694 .hsync_end = 320 + 20 + 30,
1695 .htotal = 320 + 20 + 68,
1696 .vdisplay = 240,
1697 .vsync_start = 240 + 4,
1698 .vsync_end = 240 + 4 + 4,
1699 .vtotal = 240 + 4 + 4 + 14,
1700 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1701 };
1702
1703 static const struct panel_desc edt_et035012dm6 = {
1704 .modes = &edt_et035012dm6_mode,
1705 .num_modes = 1,
1706 .bpc = 8,
1707 .size = {
1708 .width = 70,
1709 .height = 52,
1710 },
1711 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1712 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1713 };
1714
1715 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1716 .clock = 10870,
1717 .hdisplay = 480,
1718 .hsync_start = 480 + 8,
1719 .hsync_end = 480 + 8 + 4,
1720 .htotal = 480 + 8 + 4 + 41,
1721
1722 /*
1723 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1724 * fb_align
1725 */
1726
1727 .vdisplay = 288,
1728 .vsync_start = 288 + 2,
1729 .vsync_end = 288 + 2 + 4,
1730 .vtotal = 288 + 2 + 4 + 10,
1731 };
1732
1733 static const struct panel_desc edt_etm043080dh6gp = {
1734 .modes = &edt_etm043080dh6gp_mode,
1735 .num_modes = 1,
1736 .bpc = 8,
1737 .size = {
1738 .width = 100,
1739 .height = 65,
1740 },
1741 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1742 .connector_type = DRM_MODE_CONNECTOR_DPI,
1743 };
1744
1745 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1746 .clock = 9000,
1747 .hdisplay = 480,
1748 .hsync_start = 480 + 2,
1749 .hsync_end = 480 + 2 + 41,
1750 .htotal = 480 + 2 + 41 + 2,
1751 .vdisplay = 272,
1752 .vsync_start = 272 + 2,
1753 .vsync_end = 272 + 2 + 10,
1754 .vtotal = 272 + 2 + 10 + 2,
1755 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1756 };
1757
1758 static const struct panel_desc edt_etm0430g0dh6 = {
1759 .modes = &edt_etm0430g0dh6_mode,
1760 .num_modes = 1,
1761 .bpc = 6,
1762 .size = {
1763 .width = 95,
1764 .height = 54,
1765 },
1766 };
1767
1768 static const struct drm_display_mode edt_et057090dhu_mode = {
1769 .clock = 25175,
1770 .hdisplay = 640,
1771 .hsync_start = 640 + 16,
1772 .hsync_end = 640 + 16 + 30,
1773 .htotal = 640 + 16 + 30 + 114,
1774 .vdisplay = 480,
1775 .vsync_start = 480 + 10,
1776 .vsync_end = 480 + 10 + 3,
1777 .vtotal = 480 + 10 + 3 + 32,
1778 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1779 };
1780
1781 static const struct panel_desc edt_et057090dhu = {
1782 .modes = &edt_et057090dhu_mode,
1783 .num_modes = 1,
1784 .bpc = 6,
1785 .size = {
1786 .width = 115,
1787 .height = 86,
1788 },
1789 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1790 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1791 .connector_type = DRM_MODE_CONNECTOR_DPI,
1792 };
1793
1794 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1795 .clock = 33260,
1796 .hdisplay = 800,
1797 .hsync_start = 800 + 40,
1798 .hsync_end = 800 + 40 + 128,
1799 .htotal = 800 + 40 + 128 + 88,
1800 .vdisplay = 480,
1801 .vsync_start = 480 + 10,
1802 .vsync_end = 480 + 10 + 2,
1803 .vtotal = 480 + 10 + 2 + 33,
1804 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1805 };
1806
1807 static const struct panel_desc edt_etm0700g0dh6 = {
1808 .modes = &edt_etm0700g0dh6_mode,
1809 .num_modes = 1,
1810 .bpc = 6,
1811 .size = {
1812 .width = 152,
1813 .height = 91,
1814 },
1815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1816 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1817 };
1818
1819 static const struct panel_desc edt_etm0700g0bdh6 = {
1820 .modes = &edt_etm0700g0dh6_mode,
1821 .num_modes = 1,
1822 .bpc = 6,
1823 .size = {
1824 .width = 152,
1825 .height = 91,
1826 },
1827 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1828 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1829 };
1830
1831 static const struct display_timing evervision_vgg804821_timing = {
1832 .pixelclock = { 27600000, 33300000, 50000000 },
1833 .hactive = { 800, 800, 800 },
1834 .hfront_porch = { 40, 66, 70 },
1835 .hback_porch = { 40, 67, 70 },
1836 .hsync_len = { 40, 67, 70 },
1837 .vactive = { 480, 480, 480 },
1838 .vfront_porch = { 6, 10, 10 },
1839 .vback_porch = { 7, 11, 11 },
1840 .vsync_len = { 7, 11, 11 },
1841 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1842 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1843 DISPLAY_FLAGS_SYNC_NEGEDGE,
1844 };
1845
1846 static const struct panel_desc evervision_vgg804821 = {
1847 .timings = &evervision_vgg804821_timing,
1848 .num_timings = 1,
1849 .bpc = 8,
1850 .size = {
1851 .width = 108,
1852 .height = 64,
1853 },
1854 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1855 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1856 };
1857
1858 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1859 .clock = 32260,
1860 .hdisplay = 800,
1861 .hsync_start = 800 + 168,
1862 .hsync_end = 800 + 168 + 64,
1863 .htotal = 800 + 168 + 64 + 88,
1864 .vdisplay = 480,
1865 .vsync_start = 480 + 37,
1866 .vsync_end = 480 + 37 + 2,
1867 .vtotal = 480 + 37 + 2 + 8,
1868 };
1869
1870 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1871 .modes = &foxlink_fl500wvr00_a0t_mode,
1872 .num_modes = 1,
1873 .bpc = 8,
1874 .size = {
1875 .width = 108,
1876 .height = 65,
1877 },
1878 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1879 };
1880
1881 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1882 { /* 60 Hz */
1883 .clock = 6000,
1884 .hdisplay = 320,
1885 .hsync_start = 320 + 44,
1886 .hsync_end = 320 + 44 + 16,
1887 .htotal = 320 + 44 + 16 + 20,
1888 .vdisplay = 240,
1889 .vsync_start = 240 + 2,
1890 .vsync_end = 240 + 2 + 6,
1891 .vtotal = 240 + 2 + 6 + 2,
1892 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1893 },
1894 { /* 50 Hz */
1895 .clock = 5400,
1896 .hdisplay = 320,
1897 .hsync_start = 320 + 56,
1898 .hsync_end = 320 + 56 + 16,
1899 .htotal = 320 + 56 + 16 + 40,
1900 .vdisplay = 240,
1901 .vsync_start = 240 + 2,
1902 .vsync_end = 240 + 2 + 6,
1903 .vtotal = 240 + 2 + 6 + 2,
1904 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1905 },
1906 };
1907
1908 static const struct panel_desc frida_frd350h54004 = {
1909 .modes = frida_frd350h54004_modes,
1910 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1911 .bpc = 8,
1912 .size = {
1913 .width = 77,
1914 .height = 64,
1915 },
1916 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1917 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1918 .connector_type = DRM_MODE_CONNECTOR_DPI,
1919 };
1920
1921 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1922 .clock = 67185,
1923 .hdisplay = 800,
1924 .hsync_start = 800 + 20,
1925 .hsync_end = 800 + 20 + 24,
1926 .htotal = 800 + 20 + 24 + 20,
1927 .vdisplay = 1280,
1928 .vsync_start = 1280 + 4,
1929 .vsync_end = 1280 + 4 + 8,
1930 .vtotal = 1280 + 4 + 8 + 4,
1931 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1932 };
1933
1934 static const struct panel_desc friendlyarm_hd702e = {
1935 .modes = &friendlyarm_hd702e_mode,
1936 .num_modes = 1,
1937 .size = {
1938 .width = 94,
1939 .height = 151,
1940 },
1941 };
1942
1943 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1944 .clock = 9000,
1945 .hdisplay = 480,
1946 .hsync_start = 480 + 5,
1947 .hsync_end = 480 + 5 + 1,
1948 .htotal = 480 + 5 + 1 + 40,
1949 .vdisplay = 272,
1950 .vsync_start = 272 + 8,
1951 .vsync_end = 272 + 8 + 1,
1952 .vtotal = 272 + 8 + 1 + 8,
1953 };
1954
1955 static const struct panel_desc giantplus_gpg482739qs5 = {
1956 .modes = &giantplus_gpg482739qs5_mode,
1957 .num_modes = 1,
1958 .bpc = 8,
1959 .size = {
1960 .width = 95,
1961 .height = 54,
1962 },
1963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1964 };
1965
1966 static const struct display_timing giantplus_gpm940b0_timing = {
1967 .pixelclock = { 13500000, 27000000, 27500000 },
1968 .hactive = { 320, 320, 320 },
1969 .hfront_porch = { 14, 686, 718 },
1970 .hback_porch = { 50, 70, 255 },
1971 .hsync_len = { 1, 1, 1 },
1972 .vactive = { 240, 240, 240 },
1973 .vfront_porch = { 1, 1, 179 },
1974 .vback_porch = { 1, 21, 31 },
1975 .vsync_len = { 1, 1, 6 },
1976 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1977 };
1978
1979 static const struct panel_desc giantplus_gpm940b0 = {
1980 .timings = &giantplus_gpm940b0_timing,
1981 .num_timings = 1,
1982 .bpc = 8,
1983 .size = {
1984 .width = 60,
1985 .height = 45,
1986 },
1987 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1988 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1989 };
1990
1991 static const struct display_timing hannstar_hsd070pww1_timing = {
1992 .pixelclock = { 64300000, 71100000, 82000000 },
1993 .hactive = { 1280, 1280, 1280 },
1994 .hfront_porch = { 1, 1, 10 },
1995 .hback_porch = { 1, 1, 10 },
1996 /*
1997 * According to the data sheet, the minimum horizontal blanking interval
1998 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1999 * minimum working horizontal blanking interval to be 60 clocks.
2000 */
2001 .hsync_len = { 58, 158, 661 },
2002 .vactive = { 800, 800, 800 },
2003 .vfront_porch = { 1, 1, 10 },
2004 .vback_porch = { 1, 1, 10 },
2005 .vsync_len = { 1, 21, 203 },
2006 .flags = DISPLAY_FLAGS_DE_HIGH,
2007 };
2008
2009 static const struct panel_desc hannstar_hsd070pww1 = {
2010 .timings = &hannstar_hsd070pww1_timing,
2011 .num_timings = 1,
2012 .bpc = 6,
2013 .size = {
2014 .width = 151,
2015 .height = 94,
2016 },
2017 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2018 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2019 };
2020
2021 static const struct display_timing hannstar_hsd100pxn1_timing = {
2022 .pixelclock = { 55000000, 65000000, 75000000 },
2023 .hactive = { 1024, 1024, 1024 },
2024 .hfront_porch = { 40, 40, 40 },
2025 .hback_porch = { 220, 220, 220 },
2026 .hsync_len = { 20, 60, 100 },
2027 .vactive = { 768, 768, 768 },
2028 .vfront_porch = { 7, 7, 7 },
2029 .vback_porch = { 21, 21, 21 },
2030 .vsync_len = { 10, 10, 10 },
2031 .flags = DISPLAY_FLAGS_DE_HIGH,
2032 };
2033
2034 static const struct panel_desc hannstar_hsd100pxn1 = {
2035 .timings = &hannstar_hsd100pxn1_timing,
2036 .num_timings = 1,
2037 .bpc = 6,
2038 .size = {
2039 .width = 203,
2040 .height = 152,
2041 },
2042 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2043 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2044 };
2045
2046 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2047 .clock = 33333,
2048 .hdisplay = 800,
2049 .hsync_start = 800 + 85,
2050 .hsync_end = 800 + 85 + 86,
2051 .htotal = 800 + 85 + 86 + 85,
2052 .vdisplay = 480,
2053 .vsync_start = 480 + 16,
2054 .vsync_end = 480 + 16 + 13,
2055 .vtotal = 480 + 16 + 13 + 16,
2056 };
2057
2058 static const struct panel_desc hitachi_tx23d38vm0caa = {
2059 .modes = &hitachi_tx23d38vm0caa_mode,
2060 .num_modes = 1,
2061 .bpc = 6,
2062 .size = {
2063 .width = 195,
2064 .height = 117,
2065 },
2066 .delay = {
2067 .enable = 160,
2068 .disable = 160,
2069 },
2070 };
2071
2072 static const struct drm_display_mode innolux_at043tn24_mode = {
2073 .clock = 9000,
2074 .hdisplay = 480,
2075 .hsync_start = 480 + 2,
2076 .hsync_end = 480 + 2 + 41,
2077 .htotal = 480 + 2 + 41 + 2,
2078 .vdisplay = 272,
2079 .vsync_start = 272 + 2,
2080 .vsync_end = 272 + 2 + 10,
2081 .vtotal = 272 + 2 + 10 + 2,
2082 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2083 };
2084
2085 static const struct panel_desc innolux_at043tn24 = {
2086 .modes = &innolux_at043tn24_mode,
2087 .num_modes = 1,
2088 .bpc = 8,
2089 .size = {
2090 .width = 95,
2091 .height = 54,
2092 },
2093 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2094 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2095 };
2096
2097 static const struct drm_display_mode innolux_at070tn92_mode = {
2098 .clock = 33333,
2099 .hdisplay = 800,
2100 .hsync_start = 800 + 210,
2101 .hsync_end = 800 + 210 + 20,
2102 .htotal = 800 + 210 + 20 + 46,
2103 .vdisplay = 480,
2104 .vsync_start = 480 + 22,
2105 .vsync_end = 480 + 22 + 10,
2106 .vtotal = 480 + 22 + 23 + 10,
2107 };
2108
2109 static const struct panel_desc innolux_at070tn92 = {
2110 .modes = &innolux_at070tn92_mode,
2111 .num_modes = 1,
2112 .size = {
2113 .width = 154,
2114 .height = 86,
2115 },
2116 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2117 };
2118
2119 static const struct display_timing innolux_g070y2_l01_timing = {
2120 .pixelclock = { 28000000, 29500000, 32000000 },
2121 .hactive = { 800, 800, 800 },
2122 .hfront_porch = { 61, 91, 141 },
2123 .hback_porch = { 60, 90, 140 },
2124 .hsync_len = { 12, 12, 12 },
2125 .vactive = { 480, 480, 480 },
2126 .vfront_porch = { 4, 9, 30 },
2127 .vback_porch = { 4, 8, 28 },
2128 .vsync_len = { 2, 2, 2 },
2129 .flags = DISPLAY_FLAGS_DE_HIGH,
2130 };
2131
2132 static const struct panel_desc innolux_g070y2_l01 = {
2133 .timings = &innolux_g070y2_l01_timing,
2134 .num_timings = 1,
2135 .bpc = 8,
2136 .size = {
2137 .width = 152,
2138 .height = 91,
2139 },
2140 .delay = {
2141 .prepare = 10,
2142 .enable = 100,
2143 .disable = 100,
2144 .unprepare = 800,
2145 },
2146 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2147 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2148 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2149 };
2150
2151 static const struct display_timing innolux_g101ice_l01_timing = {
2152 .pixelclock = { 60400000, 71100000, 74700000 },
2153 .hactive = { 1280, 1280, 1280 },
2154 .hfront_porch = { 41, 80, 100 },
2155 .hback_porch = { 40, 79, 99 },
2156 .hsync_len = { 1, 1, 1 },
2157 .vactive = { 800, 800, 800 },
2158 .vfront_porch = { 5, 11, 14 },
2159 .vback_porch = { 4, 11, 14 },
2160 .vsync_len = { 1, 1, 1 },
2161 .flags = DISPLAY_FLAGS_DE_HIGH,
2162 };
2163
2164 static const struct panel_desc innolux_g101ice_l01 = {
2165 .timings = &innolux_g101ice_l01_timing,
2166 .num_timings = 1,
2167 .bpc = 8,
2168 .size = {
2169 .width = 217,
2170 .height = 135,
2171 },
2172 .delay = {
2173 .enable = 200,
2174 .disable = 200,
2175 },
2176 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2177 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2178 };
2179
2180 static const struct display_timing innolux_g121i1_l01_timing = {
2181 .pixelclock = { 67450000, 71000000, 74550000 },
2182 .hactive = { 1280, 1280, 1280 },
2183 .hfront_porch = { 40, 80, 160 },
2184 .hback_porch = { 39, 79, 159 },
2185 .hsync_len = { 1, 1, 1 },
2186 .vactive = { 800, 800, 800 },
2187 .vfront_porch = { 5, 11, 100 },
2188 .vback_porch = { 4, 11, 99 },
2189 .vsync_len = { 1, 1, 1 },
2190 };
2191
2192 static const struct panel_desc innolux_g121i1_l01 = {
2193 .timings = &innolux_g121i1_l01_timing,
2194 .num_timings = 1,
2195 .bpc = 6,
2196 .size = {
2197 .width = 261,
2198 .height = 163,
2199 },
2200 .delay = {
2201 .enable = 200,
2202 .disable = 20,
2203 },
2204 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2205 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2206 };
2207
2208 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2209 .clock = 65000,
2210 .hdisplay = 1024,
2211 .hsync_start = 1024 + 0,
2212 .hsync_end = 1024 + 1,
2213 .htotal = 1024 + 0 + 1 + 320,
2214 .vdisplay = 768,
2215 .vsync_start = 768 + 38,
2216 .vsync_end = 768 + 38 + 1,
2217 .vtotal = 768 + 38 + 1 + 0,
2218 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2219 };
2220
2221 static const struct panel_desc innolux_g121x1_l03 = {
2222 .modes = &innolux_g121x1_l03_mode,
2223 .num_modes = 1,
2224 .bpc = 6,
2225 .size = {
2226 .width = 246,
2227 .height = 185,
2228 },
2229 .delay = {
2230 .enable = 200,
2231 .unprepare = 200,
2232 .disable = 400,
2233 },
2234 };
2235
2236 /*
2237 * Datasheet specifies that at 60 Hz refresh rate:
2238 * - total horizontal time: { 1506, 1592, 1716 }
2239 * - total vertical time: { 788, 800, 868 }
2240 *
2241 * ...but doesn't go into exactly how that should be split into a front
2242 * porch, back porch, or sync length. For now we'll leave a single setting
2243 * here which allows a bit of tweaking of the pixel clock at the expense of
2244 * refresh rate.
2245 */
2246 static const struct display_timing innolux_n116bge_timing = {
2247 .pixelclock = { 72600000, 76420000, 80240000 },
2248 .hactive = { 1366, 1366, 1366 },
2249 .hfront_porch = { 136, 136, 136 },
2250 .hback_porch = { 60, 60, 60 },
2251 .hsync_len = { 30, 30, 30 },
2252 .vactive = { 768, 768, 768 },
2253 .vfront_porch = { 8, 8, 8 },
2254 .vback_porch = { 12, 12, 12 },
2255 .vsync_len = { 12, 12, 12 },
2256 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2257 };
2258
2259 static const struct panel_desc innolux_n116bge = {
2260 .timings = &innolux_n116bge_timing,
2261 .num_timings = 1,
2262 .bpc = 6,
2263 .size = {
2264 .width = 256,
2265 .height = 144,
2266 },
2267 };
2268
2269 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2270 .clock = 69300,
2271 .hdisplay = 1366,
2272 .hsync_start = 1366 + 16,
2273 .hsync_end = 1366 + 16 + 34,
2274 .htotal = 1366 + 16 + 34 + 50,
2275 .vdisplay = 768,
2276 .vsync_start = 768 + 2,
2277 .vsync_end = 768 + 2 + 6,
2278 .vtotal = 768 + 2 + 6 + 12,
2279 };
2280
2281 static const struct panel_desc innolux_n156bge_l21 = {
2282 .modes = &innolux_n156bge_l21_mode,
2283 .num_modes = 1,
2284 .bpc = 6,
2285 .size = {
2286 .width = 344,
2287 .height = 193,
2288 },
2289 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2290 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2291 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2292 };
2293
2294 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2295 .clock = 206016,
2296 .hdisplay = 2160,
2297 .hsync_start = 2160 + 48,
2298 .hsync_end = 2160 + 48 + 32,
2299 .htotal = 2160 + 48 + 32 + 80,
2300 .vdisplay = 1440,
2301 .vsync_start = 1440 + 3,
2302 .vsync_end = 1440 + 3 + 10,
2303 .vtotal = 1440 + 3 + 10 + 27,
2304 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2305 };
2306
2307 static const struct panel_desc innolux_p120zdg_bf1 = {
2308 .modes = &innolux_p120zdg_bf1_mode,
2309 .num_modes = 1,
2310 .bpc = 8,
2311 .size = {
2312 .width = 254,
2313 .height = 169,
2314 },
2315 .delay = {
2316 .hpd_absent_delay = 200,
2317 .unprepare = 500,
2318 },
2319 };
2320
2321 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2322 .clock = 51501,
2323 .hdisplay = 1024,
2324 .hsync_start = 1024 + 128,
2325 .hsync_end = 1024 + 128 + 64,
2326 .htotal = 1024 + 128 + 64 + 128,
2327 .vdisplay = 600,
2328 .vsync_start = 600 + 16,
2329 .vsync_end = 600 + 16 + 4,
2330 .vtotal = 600 + 16 + 4 + 16,
2331 };
2332
2333 static const struct panel_desc innolux_zj070na_01p = {
2334 .modes = &innolux_zj070na_01p_mode,
2335 .num_modes = 1,
2336 .bpc = 6,
2337 .size = {
2338 .width = 154,
2339 .height = 90,
2340 },
2341 };
2342
2343 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2344 .clock = 138778,
2345 .hdisplay = 1920,
2346 .hsync_start = 1920 + 24,
2347 .hsync_end = 1920 + 24 + 48,
2348 .htotal = 1920 + 24 + 48 + 88,
2349 .vdisplay = 1080,
2350 .vsync_start = 1080 + 3,
2351 .vsync_end = 1080 + 3 + 12,
2352 .vtotal = 1080 + 3 + 12 + 17,
2353 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2354 };
2355
2356 static const struct panel_desc ivo_m133nwf4_r0 = {
2357 .modes = &ivo_m133nwf4_r0_mode,
2358 .num_modes = 1,
2359 .bpc = 8,
2360 .size = {
2361 .width = 294,
2362 .height = 165,
2363 },
2364 .delay = {
2365 .hpd_absent_delay = 200,
2366 .unprepare = 500,
2367 },
2368 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2369 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2370 .connector_type = DRM_MODE_CONNECTOR_eDP,
2371 };
2372
2373 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2374 .clock = 81000,
2375 .hdisplay = 1366,
2376 .hsync_start = 1366 + 40,
2377 .hsync_end = 1366 + 40 + 32,
2378 .htotal = 1366 + 40 + 32 + 62,
2379 .vdisplay = 768,
2380 .vsync_start = 768 + 5,
2381 .vsync_end = 768 + 5 + 5,
2382 .vtotal = 768 + 5 + 5 + 122,
2383 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2384 };
2385
2386 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2387 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2388 .num_modes = 1,
2389 .bpc = 6,
2390 .size = {
2391 .width = 256,
2392 .height = 144,
2393 },
2394 .delay = {
2395 .hpd_absent_delay = 200,
2396 },
2397 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2398 .connector_type = DRM_MODE_CONNECTOR_eDP,
2399 };
2400
2401 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2402 .pixelclock = { 5580000, 5850000, 6200000 },
2403 .hactive = { 320, 320, 320 },
2404 .hfront_porch = { 30, 30, 30 },
2405 .hback_porch = { 30, 30, 30 },
2406 .hsync_len = { 1, 5, 17 },
2407 .vactive = { 240, 240, 240 },
2408 .vfront_porch = { 6, 6, 6 },
2409 .vback_porch = { 5, 5, 5 },
2410 .vsync_len = { 1, 2, 11 },
2411 .flags = DISPLAY_FLAGS_DE_HIGH,
2412 };
2413
2414 static const struct panel_desc koe_tx14d24vm1bpa = {
2415 .timings = &koe_tx14d24vm1bpa_timing,
2416 .num_timings = 1,
2417 .bpc = 6,
2418 .size = {
2419 .width = 115,
2420 .height = 86,
2421 },
2422 };
2423
2424 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2425 .pixelclock = { 151820000, 156720000, 159780000 },
2426 .hactive = { 1920, 1920, 1920 },
2427 .hfront_porch = { 105, 130, 142 },
2428 .hback_porch = { 45, 70, 82 },
2429 .hsync_len = { 30, 30, 30 },
2430 .vactive = { 1200, 1200, 1200},
2431 .vfront_porch = { 3, 5, 10 },
2432 .vback_porch = { 2, 5, 10 },
2433 .vsync_len = { 5, 5, 5 },
2434 };
2435
2436 static const struct panel_desc koe_tx26d202vm0bwa = {
2437 .timings = &koe_tx26d202vm0bwa_timing,
2438 .num_timings = 1,
2439 .bpc = 8,
2440 .size = {
2441 .width = 217,
2442 .height = 136,
2443 },
2444 .delay = {
2445 .prepare = 1000,
2446 .enable = 1000,
2447 .unprepare = 1000,
2448 .disable = 1000,
2449 },
2450 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2451 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2452 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2453 };
2454
2455 static const struct display_timing koe_tx31d200vm0baa_timing = {
2456 .pixelclock = { 39600000, 43200000, 48000000 },
2457 .hactive = { 1280, 1280, 1280 },
2458 .hfront_porch = { 16, 36, 56 },
2459 .hback_porch = { 16, 36, 56 },
2460 .hsync_len = { 8, 8, 8 },
2461 .vactive = { 480, 480, 480 },
2462 .vfront_porch = { 6, 21, 33 },
2463 .vback_porch = { 6, 21, 33 },
2464 .vsync_len = { 8, 8, 8 },
2465 .flags = DISPLAY_FLAGS_DE_HIGH,
2466 };
2467
2468 static const struct panel_desc koe_tx31d200vm0baa = {
2469 .timings = &koe_tx31d200vm0baa_timing,
2470 .num_timings = 1,
2471 .bpc = 6,
2472 .size = {
2473 .width = 292,
2474 .height = 109,
2475 },
2476 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2477 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2478 };
2479
2480 static const struct display_timing kyo_tcg121xglp_timing = {
2481 .pixelclock = { 52000000, 65000000, 71000000 },
2482 .hactive = { 1024, 1024, 1024 },
2483 .hfront_porch = { 2, 2, 2 },
2484 .hback_porch = { 2, 2, 2 },
2485 .hsync_len = { 86, 124, 244 },
2486 .vactive = { 768, 768, 768 },
2487 .vfront_porch = { 2, 2, 2 },
2488 .vback_porch = { 2, 2, 2 },
2489 .vsync_len = { 6, 34, 73 },
2490 .flags = DISPLAY_FLAGS_DE_HIGH,
2491 };
2492
2493 static const struct panel_desc kyo_tcg121xglp = {
2494 .timings = &kyo_tcg121xglp_timing,
2495 .num_timings = 1,
2496 .bpc = 8,
2497 .size = {
2498 .width = 246,
2499 .height = 184,
2500 },
2501 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2502 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2503 };
2504
2505 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2506 .clock = 7000,
2507 .hdisplay = 320,
2508 .hsync_start = 320 + 20,
2509 .hsync_end = 320 + 20 + 30,
2510 .htotal = 320 + 20 + 30 + 38,
2511 .vdisplay = 240,
2512 .vsync_start = 240 + 4,
2513 .vsync_end = 240 + 4 + 3,
2514 .vtotal = 240 + 4 + 3 + 15,
2515 };
2516
2517 static const struct panel_desc lemaker_bl035_rgb_002 = {
2518 .modes = &lemaker_bl035_rgb_002_mode,
2519 .num_modes = 1,
2520 .size = {
2521 .width = 70,
2522 .height = 52,
2523 },
2524 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2525 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2526 };
2527
2528 static const struct drm_display_mode lg_lb070wv8_mode = {
2529 .clock = 33246,
2530 .hdisplay = 800,
2531 .hsync_start = 800 + 88,
2532 .hsync_end = 800 + 88 + 80,
2533 .htotal = 800 + 88 + 80 + 88,
2534 .vdisplay = 480,
2535 .vsync_start = 480 + 10,
2536 .vsync_end = 480 + 10 + 25,
2537 .vtotal = 480 + 10 + 25 + 10,
2538 };
2539
2540 static const struct panel_desc lg_lb070wv8 = {
2541 .modes = &lg_lb070wv8_mode,
2542 .num_modes = 1,
2543 .bpc = 8,
2544 .size = {
2545 .width = 151,
2546 .height = 91,
2547 },
2548 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2549 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2550 };
2551
2552 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2553 .clock = 200000,
2554 .hdisplay = 1536,
2555 .hsync_start = 1536 + 12,
2556 .hsync_end = 1536 + 12 + 16,
2557 .htotal = 1536 + 12 + 16 + 48,
2558 .vdisplay = 2048,
2559 .vsync_start = 2048 + 8,
2560 .vsync_end = 2048 + 8 + 4,
2561 .vtotal = 2048 + 8 + 4 + 8,
2562 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2563 };
2564
2565 static const struct panel_desc lg_lp079qx1_sp0v = {
2566 .modes = &lg_lp079qx1_sp0v_mode,
2567 .num_modes = 1,
2568 .size = {
2569 .width = 129,
2570 .height = 171,
2571 },
2572 };
2573
2574 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2575 .clock = 205210,
2576 .hdisplay = 2048,
2577 .hsync_start = 2048 + 150,
2578 .hsync_end = 2048 + 150 + 5,
2579 .htotal = 2048 + 150 + 5 + 5,
2580 .vdisplay = 1536,
2581 .vsync_start = 1536 + 3,
2582 .vsync_end = 1536 + 3 + 1,
2583 .vtotal = 1536 + 3 + 1 + 9,
2584 };
2585
2586 static const struct panel_desc lg_lp097qx1_spa1 = {
2587 .modes = &lg_lp097qx1_spa1_mode,
2588 .num_modes = 1,
2589 .size = {
2590 .width = 208,
2591 .height = 147,
2592 },
2593 };
2594
2595 static const struct drm_display_mode lg_lp120up1_mode = {
2596 .clock = 162300,
2597 .hdisplay = 1920,
2598 .hsync_start = 1920 + 40,
2599 .hsync_end = 1920 + 40 + 40,
2600 .htotal = 1920 + 40 + 40+ 80,
2601 .vdisplay = 1280,
2602 .vsync_start = 1280 + 4,
2603 .vsync_end = 1280 + 4 + 4,
2604 .vtotal = 1280 + 4 + 4 + 12,
2605 };
2606
2607 static const struct panel_desc lg_lp120up1 = {
2608 .modes = &lg_lp120up1_mode,
2609 .num_modes = 1,
2610 .bpc = 8,
2611 .size = {
2612 .width = 267,
2613 .height = 183,
2614 },
2615 .connector_type = DRM_MODE_CONNECTOR_eDP,
2616 };
2617
2618 static const struct drm_display_mode lg_lp129qe_mode = {
2619 .clock = 285250,
2620 .hdisplay = 2560,
2621 .hsync_start = 2560 + 48,
2622 .hsync_end = 2560 + 48 + 32,
2623 .htotal = 2560 + 48 + 32 + 80,
2624 .vdisplay = 1700,
2625 .vsync_start = 1700 + 3,
2626 .vsync_end = 1700 + 3 + 10,
2627 .vtotal = 1700 + 3 + 10 + 36,
2628 };
2629
2630 static const struct panel_desc lg_lp129qe = {
2631 .modes = &lg_lp129qe_mode,
2632 .num_modes = 1,
2633 .bpc = 8,
2634 .size = {
2635 .width = 272,
2636 .height = 181,
2637 },
2638 };
2639
2640 static const struct display_timing logictechno_lt161010_2nh_timing = {
2641 .pixelclock = { 26400000, 33300000, 46800000 },
2642 .hactive = { 800, 800, 800 },
2643 .hfront_porch = { 16, 210, 354 },
2644 .hback_porch = { 46, 46, 46 },
2645 .hsync_len = { 1, 20, 40 },
2646 .vactive = { 480, 480, 480 },
2647 .vfront_porch = { 7, 22, 147 },
2648 .vback_porch = { 23, 23, 23 },
2649 .vsync_len = { 1, 10, 20 },
2650 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2651 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2652 DISPLAY_FLAGS_SYNC_POSEDGE,
2653 };
2654
2655 static const struct panel_desc logictechno_lt161010_2nh = {
2656 .timings = &logictechno_lt161010_2nh_timing,
2657 .num_timings = 1,
2658 .bpc = 6,
2659 .size = {
2660 .width = 154,
2661 .height = 86,
2662 },
2663 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2664 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2666 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2667 .connector_type = DRM_MODE_CONNECTOR_DPI,
2668 };
2669
2670 static const struct display_timing logictechno_lt170410_2whc_timing = {
2671 .pixelclock = { 68900000, 71100000, 73400000 },
2672 .hactive = { 1280, 1280, 1280 },
2673 .hfront_porch = { 23, 60, 71 },
2674 .hback_porch = { 23, 60, 71 },
2675 .hsync_len = { 15, 40, 47 },
2676 .vactive = { 800, 800, 800 },
2677 .vfront_porch = { 5, 7, 10 },
2678 .vback_porch = { 5, 7, 10 },
2679 .vsync_len = { 6, 9, 12 },
2680 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2681 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2682 DISPLAY_FLAGS_SYNC_POSEDGE,
2683 };
2684
2685 static const struct panel_desc logictechno_lt170410_2whc = {
2686 .timings = &logictechno_lt170410_2whc_timing,
2687 .num_timings = 1,
2688 .bpc = 8,
2689 .size = {
2690 .width = 217,
2691 .height = 136,
2692 },
2693 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2694 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2695 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2696 };
2697
2698 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2699 .clock = 30400,
2700 .hdisplay = 800,
2701 .hsync_start = 800 + 0,
2702 .hsync_end = 800 + 1,
2703 .htotal = 800 + 0 + 1 + 160,
2704 .vdisplay = 480,
2705 .vsync_start = 480 + 0,
2706 .vsync_end = 480 + 48 + 1,
2707 .vtotal = 480 + 48 + 1 + 0,
2708 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2709 };
2710
2711 static const struct drm_display_mode logicpd_type_28_mode = {
2712 .clock = 9107,
2713 .hdisplay = 480,
2714 .hsync_start = 480 + 3,
2715 .hsync_end = 480 + 3 + 42,
2716 .htotal = 480 + 3 + 42 + 2,
2717
2718 .vdisplay = 272,
2719 .vsync_start = 272 + 2,
2720 .vsync_end = 272 + 2 + 11,
2721 .vtotal = 272 + 2 + 11 + 3,
2722 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2723 };
2724
2725 static const struct panel_desc logicpd_type_28 = {
2726 .modes = &logicpd_type_28_mode,
2727 .num_modes = 1,
2728 .bpc = 8,
2729 .size = {
2730 .width = 105,
2731 .height = 67,
2732 },
2733 .delay = {
2734 .prepare = 200,
2735 .enable = 200,
2736 .unprepare = 200,
2737 .disable = 200,
2738 },
2739 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2740 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2741 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2742 .connector_type = DRM_MODE_CONNECTOR_DPI,
2743 };
2744
2745 static const struct panel_desc mitsubishi_aa070mc01 = {
2746 .modes = &mitsubishi_aa070mc01_mode,
2747 .num_modes = 1,
2748 .bpc = 8,
2749 .size = {
2750 .width = 152,
2751 .height = 91,
2752 },
2753
2754 .delay = {
2755 .enable = 200,
2756 .unprepare = 200,
2757 .disable = 400,
2758 },
2759 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2760 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2761 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2762 };
2763
2764 static const struct display_timing nec_nl12880bc20_05_timing = {
2765 .pixelclock = { 67000000, 71000000, 75000000 },
2766 .hactive = { 1280, 1280, 1280 },
2767 .hfront_porch = { 2, 30, 30 },
2768 .hback_porch = { 6, 100, 100 },
2769 .hsync_len = { 2, 30, 30 },
2770 .vactive = { 800, 800, 800 },
2771 .vfront_porch = { 5, 5, 5 },
2772 .vback_porch = { 11, 11, 11 },
2773 .vsync_len = { 7, 7, 7 },
2774 };
2775
2776 static const struct panel_desc nec_nl12880bc20_05 = {
2777 .timings = &nec_nl12880bc20_05_timing,
2778 .num_timings = 1,
2779 .bpc = 8,
2780 .size = {
2781 .width = 261,
2782 .height = 163,
2783 },
2784 .delay = {
2785 .enable = 50,
2786 .disable = 50,
2787 },
2788 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2789 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2790 };
2791
2792 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2793 .clock = 10870,
2794 .hdisplay = 480,
2795 .hsync_start = 480 + 2,
2796 .hsync_end = 480 + 2 + 41,
2797 .htotal = 480 + 2 + 41 + 2,
2798 .vdisplay = 272,
2799 .vsync_start = 272 + 2,
2800 .vsync_end = 272 + 2 + 4,
2801 .vtotal = 272 + 2 + 4 + 2,
2802 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2803 };
2804
2805 static const struct panel_desc nec_nl4827hc19_05b = {
2806 .modes = &nec_nl4827hc19_05b_mode,
2807 .num_modes = 1,
2808 .bpc = 8,
2809 .size = {
2810 .width = 95,
2811 .height = 54,
2812 },
2813 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2814 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2815 };
2816
2817 static const struct drm_display_mode netron_dy_e231732_mode = {
2818 .clock = 66000,
2819 .hdisplay = 1024,
2820 .hsync_start = 1024 + 160,
2821 .hsync_end = 1024 + 160 + 70,
2822 .htotal = 1024 + 160 + 70 + 90,
2823 .vdisplay = 600,
2824 .vsync_start = 600 + 127,
2825 .vsync_end = 600 + 127 + 20,
2826 .vtotal = 600 + 127 + 20 + 3,
2827 };
2828
2829 static const struct panel_desc netron_dy_e231732 = {
2830 .modes = &netron_dy_e231732_mode,
2831 .num_modes = 1,
2832 .size = {
2833 .width = 154,
2834 .height = 87,
2835 },
2836 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2837 };
2838
2839 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2840 {
2841 .clock = 138500,
2842 .hdisplay = 1920,
2843 .hsync_start = 1920 + 48,
2844 .hsync_end = 1920 + 48 + 32,
2845 .htotal = 1920 + 48 + 32 + 80,
2846 .vdisplay = 1080,
2847 .vsync_start = 1080 + 3,
2848 .vsync_end = 1080 + 3 + 5,
2849 .vtotal = 1080 + 3 + 5 + 23,
2850 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2851 }, {
2852 .clock = 110920,
2853 .hdisplay = 1920,
2854 .hsync_start = 1920 + 48,
2855 .hsync_end = 1920 + 48 + 32,
2856 .htotal = 1920 + 48 + 32 + 80,
2857 .vdisplay = 1080,
2858 .vsync_start = 1080 + 3,
2859 .vsync_end = 1080 + 3 + 5,
2860 .vtotal = 1080 + 3 + 5 + 23,
2861 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2862 }
2863 };
2864
2865 static const struct panel_desc neweast_wjfh116008a = {
2866 .modes = neweast_wjfh116008a_modes,
2867 .num_modes = 2,
2868 .bpc = 6,
2869 .size = {
2870 .width = 260,
2871 .height = 150,
2872 },
2873 .delay = {
2874 .prepare = 110,
2875 .enable = 20,
2876 .unprepare = 500,
2877 },
2878 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2879 .connector_type = DRM_MODE_CONNECTOR_eDP,
2880 };
2881
2882 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2883 .clock = 9000,
2884 .hdisplay = 480,
2885 .hsync_start = 480 + 2,
2886 .hsync_end = 480 + 2 + 41,
2887 .htotal = 480 + 2 + 41 + 2,
2888 .vdisplay = 272,
2889 .vsync_start = 272 + 2,
2890 .vsync_end = 272 + 2 + 10,
2891 .vtotal = 272 + 2 + 10 + 2,
2892 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2893 };
2894
2895 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2896 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2897 .num_modes = 1,
2898 .bpc = 8,
2899 .size = {
2900 .width = 95,
2901 .height = 54,
2902 },
2903 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2904 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2905 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2906 .connector_type = DRM_MODE_CONNECTOR_DPI,
2907 };
2908
2909 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2910 .pixelclock = { 130000000, 148350000, 163000000 },
2911 .hactive = { 1920, 1920, 1920 },
2912 .hfront_porch = { 80, 100, 100 },
2913 .hback_porch = { 100, 120, 120 },
2914 .hsync_len = { 50, 60, 60 },
2915 .vactive = { 1080, 1080, 1080 },
2916 .vfront_porch = { 12, 30, 30 },
2917 .vback_porch = { 4, 10, 10 },
2918 .vsync_len = { 4, 5, 5 },
2919 };
2920
2921 static const struct panel_desc nlt_nl192108ac18_02d = {
2922 .timings = &nlt_nl192108ac18_02d_timing,
2923 .num_timings = 1,
2924 .bpc = 8,
2925 .size = {
2926 .width = 344,
2927 .height = 194,
2928 },
2929 .delay = {
2930 .unprepare = 500,
2931 },
2932 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2933 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2934 };
2935
2936 static const struct drm_display_mode nvd_9128_mode = {
2937 .clock = 29500,
2938 .hdisplay = 800,
2939 .hsync_start = 800 + 130,
2940 .hsync_end = 800 + 130 + 98,
2941 .htotal = 800 + 0 + 130 + 98,
2942 .vdisplay = 480,
2943 .vsync_start = 480 + 10,
2944 .vsync_end = 480 + 10 + 50,
2945 .vtotal = 480 + 0 + 10 + 50,
2946 };
2947
2948 static const struct panel_desc nvd_9128 = {
2949 .modes = &nvd_9128_mode,
2950 .num_modes = 1,
2951 .bpc = 8,
2952 .size = {
2953 .width = 156,
2954 .height = 88,
2955 },
2956 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2957 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2958 };
2959
2960 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2961 .pixelclock = { 30000000, 30000000, 40000000 },
2962 .hactive = { 800, 800, 800 },
2963 .hfront_porch = { 40, 40, 40 },
2964 .hback_porch = { 40, 40, 40 },
2965 .hsync_len = { 1, 48, 48 },
2966 .vactive = { 480, 480, 480 },
2967 .vfront_porch = { 13, 13, 13 },
2968 .vback_porch = { 29, 29, 29 },
2969 .vsync_len = { 3, 3, 3 },
2970 .flags = DISPLAY_FLAGS_DE_HIGH,
2971 };
2972
2973 static const struct panel_desc okaya_rs800480t_7x0gp = {
2974 .timings = &okaya_rs800480t_7x0gp_timing,
2975 .num_timings = 1,
2976 .bpc = 6,
2977 .size = {
2978 .width = 154,
2979 .height = 87,
2980 },
2981 .delay = {
2982 .prepare = 41,
2983 .enable = 50,
2984 .unprepare = 41,
2985 .disable = 50,
2986 },
2987 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2988 };
2989
2990 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2991 .clock = 9000,
2992 .hdisplay = 480,
2993 .hsync_start = 480 + 5,
2994 .hsync_end = 480 + 5 + 30,
2995 .htotal = 480 + 5 + 30 + 10,
2996 .vdisplay = 272,
2997 .vsync_start = 272 + 8,
2998 .vsync_end = 272 + 8 + 5,
2999 .vtotal = 272 + 8 + 5 + 3,
3000 };
3001
3002 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3003 .modes = &olimex_lcd_olinuxino_43ts_mode,
3004 .num_modes = 1,
3005 .size = {
3006 .width = 95,
3007 .height = 54,
3008 },
3009 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3010 };
3011
3012 /*
3013 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3014 * pixel clocks, but this is the timing that was being used in the Adafruit
3015 * installation instructions.
3016 */
3017 static const struct drm_display_mode ontat_yx700wv03_mode = {
3018 .clock = 29500,
3019 .hdisplay = 800,
3020 .hsync_start = 824,
3021 .hsync_end = 896,
3022 .htotal = 992,
3023 .vdisplay = 480,
3024 .vsync_start = 483,
3025 .vsync_end = 493,
3026 .vtotal = 500,
3027 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3028 };
3029
3030 /*
3031 * Specification at:
3032 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3033 */
3034 static const struct panel_desc ontat_yx700wv03 = {
3035 .modes = &ontat_yx700wv03_mode,
3036 .num_modes = 1,
3037 .bpc = 8,
3038 .size = {
3039 .width = 154,
3040 .height = 83,
3041 },
3042 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3043 };
3044
3045 static const struct drm_display_mode ortustech_com37h3m_mode = {
3046 .clock = 22230,
3047 .hdisplay = 480,
3048 .hsync_start = 480 + 40,
3049 .hsync_end = 480 + 40 + 10,
3050 .htotal = 480 + 40 + 10 + 40,
3051 .vdisplay = 640,
3052 .vsync_start = 640 + 4,
3053 .vsync_end = 640 + 4 + 2,
3054 .vtotal = 640 + 4 + 2 + 4,
3055 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3056 };
3057
3058 static const struct panel_desc ortustech_com37h3m = {
3059 .modes = &ortustech_com37h3m_mode,
3060 .num_modes = 1,
3061 .bpc = 8,
3062 .size = {
3063 .width = 56, /* 56.16mm */
3064 .height = 75, /* 74.88mm */
3065 },
3066 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3067 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3068 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3069 };
3070
3071 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3072 .clock = 25000,
3073 .hdisplay = 480,
3074 .hsync_start = 480 + 10,
3075 .hsync_end = 480 + 10 + 10,
3076 .htotal = 480 + 10 + 10 + 15,
3077 .vdisplay = 800,
3078 .vsync_start = 800 + 3,
3079 .vsync_end = 800 + 3 + 3,
3080 .vtotal = 800 + 3 + 3 + 3,
3081 };
3082
3083 static const struct panel_desc ortustech_com43h4m85ulc = {
3084 .modes = &ortustech_com43h4m85ulc_mode,
3085 .num_modes = 1,
3086 .bpc = 6,
3087 .size = {
3088 .width = 56,
3089 .height = 93,
3090 },
3091 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3092 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3093 .connector_type = DRM_MODE_CONNECTOR_DPI,
3094 };
3095
3096 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3097 .clock = 33000,
3098 .hdisplay = 800,
3099 .hsync_start = 800 + 210,
3100 .hsync_end = 800 + 210 + 30,
3101 .htotal = 800 + 210 + 30 + 16,
3102 .vdisplay = 480,
3103 .vsync_start = 480 + 22,
3104 .vsync_end = 480 + 22 + 13,
3105 .vtotal = 480 + 22 + 13 + 10,
3106 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3107 };
3108
3109 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3110 .modes = &osddisplays_osd070t1718_19ts_mode,
3111 .num_modes = 1,
3112 .bpc = 8,
3113 .size = {
3114 .width = 152,
3115 .height = 91,
3116 },
3117 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3118 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3119 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3120 .connector_type = DRM_MODE_CONNECTOR_DPI,
3121 };
3122
3123 static const struct drm_display_mode pda_91_00156_a0_mode = {
3124 .clock = 33300,
3125 .hdisplay = 800,
3126 .hsync_start = 800 + 1,
3127 .hsync_end = 800 + 1 + 64,
3128 .htotal = 800 + 1 + 64 + 64,
3129 .vdisplay = 480,
3130 .vsync_start = 480 + 1,
3131 .vsync_end = 480 + 1 + 23,
3132 .vtotal = 480 + 1 + 23 + 22,
3133 };
3134
3135 static const struct panel_desc pda_91_00156_a0 = {
3136 .modes = &pda_91_00156_a0_mode,
3137 .num_modes = 1,
3138 .size = {
3139 .width = 152,
3140 .height = 91,
3141 },
3142 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3143 };
3144
3145 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3146 .clock = 24750,
3147 .hdisplay = 800,
3148 .hsync_start = 800 + 54,
3149 .hsync_end = 800 + 54 + 2,
3150 .htotal = 800 + 54 + 2 + 44,
3151 .vdisplay = 480,
3152 .vsync_start = 480 + 49,
3153 .vsync_end = 480 + 49 + 2,
3154 .vtotal = 480 + 49 + 2 + 22,
3155 };
3156
3157 static const struct panel_desc powertip_ph800480t013_idf02 = {
3158 .modes = &powertip_ph800480t013_idf02_mode,
3159 .num_modes = 1,
3160 .size = {
3161 .width = 152,
3162 .height = 91,
3163 },
3164 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3165 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3166 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3167 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3168 .connector_type = DRM_MODE_CONNECTOR_DPI,
3169 };
3170
3171 static const struct drm_display_mode qd43003c0_40_mode = {
3172 .clock = 9000,
3173 .hdisplay = 480,
3174 .hsync_start = 480 + 8,
3175 .hsync_end = 480 + 8 + 4,
3176 .htotal = 480 + 8 + 4 + 39,
3177 .vdisplay = 272,
3178 .vsync_start = 272 + 4,
3179 .vsync_end = 272 + 4 + 10,
3180 .vtotal = 272 + 4 + 10 + 2,
3181 };
3182
3183 static const struct panel_desc qd43003c0_40 = {
3184 .modes = &qd43003c0_40_mode,
3185 .num_modes = 1,
3186 .bpc = 8,
3187 .size = {
3188 .width = 95,
3189 .height = 53,
3190 },
3191 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3192 };
3193
3194 static const struct display_timing rocktech_rk070er9427_timing = {
3195 .pixelclock = { 26400000, 33300000, 46800000 },
3196 .hactive = { 800, 800, 800 },
3197 .hfront_porch = { 16, 210, 354 },
3198 .hback_porch = { 46, 46, 46 },
3199 .hsync_len = { 1, 1, 1 },
3200 .vactive = { 480, 480, 480 },
3201 .vfront_porch = { 7, 22, 147 },
3202 .vback_porch = { 23, 23, 23 },
3203 .vsync_len = { 1, 1, 1 },
3204 .flags = DISPLAY_FLAGS_DE_HIGH,
3205 };
3206
3207 static const struct panel_desc rocktech_rk070er9427 = {
3208 .timings = &rocktech_rk070er9427_timing,
3209 .num_timings = 1,
3210 .bpc = 6,
3211 .size = {
3212 .width = 154,
3213 .height = 86,
3214 },
3215 .delay = {
3216 .prepare = 41,
3217 .enable = 50,
3218 .unprepare = 41,
3219 .disable = 50,
3220 },
3221 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3222 };
3223
3224 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3225 .clock = 71100,
3226 .hdisplay = 1280,
3227 .hsync_start = 1280 + 48,
3228 .hsync_end = 1280 + 48 + 32,
3229 .htotal = 1280 + 48 + 32 + 80,
3230 .vdisplay = 800,
3231 .vsync_start = 800 + 2,
3232 .vsync_end = 800 + 2 + 5,
3233 .vtotal = 800 + 2 + 5 + 16,
3234 };
3235
3236 static const struct panel_desc rocktech_rk101ii01d_ct = {
3237 .modes = &rocktech_rk101ii01d_ct_mode,
3238 .num_modes = 1,
3239 .size = {
3240 .width = 217,
3241 .height = 136,
3242 },
3243 .delay = {
3244 .prepare = 50,
3245 .disable = 50,
3246 },
3247 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3249 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3250 };
3251
3252 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3253 .clock = 271560,
3254 .hdisplay = 2560,
3255 .hsync_start = 2560 + 48,
3256 .hsync_end = 2560 + 48 + 32,
3257 .htotal = 2560 + 48 + 32 + 80,
3258 .vdisplay = 1600,
3259 .vsync_start = 1600 + 2,
3260 .vsync_end = 1600 + 2 + 5,
3261 .vtotal = 1600 + 2 + 5 + 57,
3262 };
3263
3264 static const struct panel_desc samsung_lsn122dl01_c01 = {
3265 .modes = &samsung_lsn122dl01_c01_mode,
3266 .num_modes = 1,
3267 .size = {
3268 .width = 263,
3269 .height = 164,
3270 },
3271 };
3272
3273 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3274 .clock = 54030,
3275 .hdisplay = 1024,
3276 .hsync_start = 1024 + 24,
3277 .hsync_end = 1024 + 24 + 136,
3278 .htotal = 1024 + 24 + 136 + 160,
3279 .vdisplay = 600,
3280 .vsync_start = 600 + 3,
3281 .vsync_end = 600 + 3 + 6,
3282 .vtotal = 600 + 3 + 6 + 61,
3283 };
3284
3285 static const struct panel_desc samsung_ltn101nt05 = {
3286 .modes = &samsung_ltn101nt05_mode,
3287 .num_modes = 1,
3288 .bpc = 6,
3289 .size = {
3290 .width = 223,
3291 .height = 125,
3292 },
3293 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3294 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3295 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3296 };
3297
3298 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3299 .clock = 76300,
3300 .hdisplay = 1366,
3301 .hsync_start = 1366 + 64,
3302 .hsync_end = 1366 + 64 + 48,
3303 .htotal = 1366 + 64 + 48 + 128,
3304 .vdisplay = 768,
3305 .vsync_start = 768 + 2,
3306 .vsync_end = 768 + 2 + 5,
3307 .vtotal = 768 + 2 + 5 + 17,
3308 };
3309
3310 static const struct panel_desc samsung_ltn140at29_301 = {
3311 .modes = &samsung_ltn140at29_301_mode,
3312 .num_modes = 1,
3313 .bpc = 6,
3314 .size = {
3315 .width = 320,
3316 .height = 187,
3317 },
3318 };
3319
3320 static const struct display_timing satoz_sat050at40h12r2_timing = {
3321 .pixelclock = {33300000, 33300000, 50000000},
3322 .hactive = {800, 800, 800},
3323 .hfront_porch = {16, 210, 354},
3324 .hback_porch = {46, 46, 46},
3325 .hsync_len = {1, 1, 40},
3326 .vactive = {480, 480, 480},
3327 .vfront_porch = {7, 22, 147},
3328 .vback_porch = {23, 23, 23},
3329 .vsync_len = {1, 1, 20},
3330 };
3331
3332 static const struct panel_desc satoz_sat050at40h12r2 = {
3333 .timings = &satoz_sat050at40h12r2_timing,
3334 .num_timings = 1,
3335 .bpc = 8,
3336 .size = {
3337 .width = 108,
3338 .height = 65,
3339 },
3340 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3341 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3342 };
3343
3344 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3345 .clock = 168480,
3346 .hdisplay = 1920,
3347 .hsync_start = 1920 + 48,
3348 .hsync_end = 1920 + 48 + 32,
3349 .htotal = 1920 + 48 + 32 + 80,
3350 .vdisplay = 1280,
3351 .vsync_start = 1280 + 3,
3352 .vsync_end = 1280 + 3 + 10,
3353 .vtotal = 1280 + 3 + 10 + 57,
3354 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3355 };
3356
3357 static const struct panel_desc sharp_ld_d5116z01b = {
3358 .modes = &sharp_ld_d5116z01b_mode,
3359 .num_modes = 1,
3360 .bpc = 8,
3361 .size = {
3362 .width = 260,
3363 .height = 120,
3364 },
3365 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3366 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3367 };
3368
3369 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3370 .clock = 33260,
3371 .hdisplay = 800,
3372 .hsync_start = 800 + 64,
3373 .hsync_end = 800 + 64 + 128,
3374 .htotal = 800 + 64 + 128 + 64,
3375 .vdisplay = 480,
3376 .vsync_start = 480 + 8,
3377 .vsync_end = 480 + 8 + 2,
3378 .vtotal = 480 + 8 + 2 + 35,
3379 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3380 };
3381
3382 static const struct panel_desc sharp_lq070y3dg3b = {
3383 .modes = &sharp_lq070y3dg3b_mode,
3384 .num_modes = 1,
3385 .bpc = 8,
3386 .size = {
3387 .width = 152, /* 152.4mm */
3388 .height = 91, /* 91.4mm */
3389 },
3390 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3391 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3392 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3393 };
3394
3395 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3396 .clock = 5500,
3397 .hdisplay = 240,
3398 .hsync_start = 240 + 16,
3399 .hsync_end = 240 + 16 + 7,
3400 .htotal = 240 + 16 + 7 + 5,
3401 .vdisplay = 320,
3402 .vsync_start = 320 + 9,
3403 .vsync_end = 320 + 9 + 1,
3404 .vtotal = 320 + 9 + 1 + 7,
3405 };
3406
3407 static const struct panel_desc sharp_lq035q7db03 = {
3408 .modes = &sharp_lq035q7db03_mode,
3409 .num_modes = 1,
3410 .bpc = 6,
3411 .size = {
3412 .width = 54,
3413 .height = 72,
3414 },
3415 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3416 };
3417
3418 static const struct display_timing sharp_lq101k1ly04_timing = {
3419 .pixelclock = { 60000000, 65000000, 80000000 },
3420 .hactive = { 1280, 1280, 1280 },
3421 .hfront_porch = { 20, 20, 20 },
3422 .hback_porch = { 20, 20, 20 },
3423 .hsync_len = { 10, 10, 10 },
3424 .vactive = { 800, 800, 800 },
3425 .vfront_porch = { 4, 4, 4 },
3426 .vback_porch = { 4, 4, 4 },
3427 .vsync_len = { 4, 4, 4 },
3428 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3429 };
3430
3431 static const struct panel_desc sharp_lq101k1ly04 = {
3432 .timings = &sharp_lq101k1ly04_timing,
3433 .num_timings = 1,
3434 .bpc = 8,
3435 .size = {
3436 .width = 217,
3437 .height = 136,
3438 },
3439 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3440 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3441 };
3442
3443 static const struct display_timing sharp_lq123p1jx31_timing = {
3444 .pixelclock = { 252750000, 252750000, 266604720 },
3445 .hactive = { 2400, 2400, 2400 },
3446 .hfront_porch = { 48, 48, 48 },
3447 .hback_porch = { 80, 80, 84 },
3448 .hsync_len = { 32, 32, 32 },
3449 .vactive = { 1600, 1600, 1600 },
3450 .vfront_porch = { 3, 3, 3 },
3451 .vback_porch = { 33, 33, 120 },
3452 .vsync_len = { 10, 10, 10 },
3453 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3454 };
3455
3456 static const struct panel_desc sharp_lq123p1jx31 = {
3457 .timings = &sharp_lq123p1jx31_timing,
3458 .num_timings = 1,
3459 .bpc = 8,
3460 .size = {
3461 .width = 259,
3462 .height = 173,
3463 },
3464 .delay = {
3465 .prepare = 110,
3466 .enable = 50,
3467 .unprepare = 550,
3468 },
3469 };
3470
3471 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3472 { /* 50 Hz */
3473 .clock = 3000,
3474 .hdisplay = 240,
3475 .hsync_start = 240 + 58,
3476 .hsync_end = 240 + 58 + 1,
3477 .htotal = 240 + 58 + 1 + 1,
3478 .vdisplay = 160,
3479 .vsync_start = 160 + 24,
3480 .vsync_end = 160 + 24 + 10,
3481 .vtotal = 160 + 24 + 10 + 6,
3482 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3483 },
3484 { /* 60 Hz */
3485 .clock = 3000,
3486 .hdisplay = 240,
3487 .hsync_start = 240 + 8,
3488 .hsync_end = 240 + 8 + 1,
3489 .htotal = 240 + 8 + 1 + 1,
3490 .vdisplay = 160,
3491 .vsync_start = 160 + 24,
3492 .vsync_end = 160 + 24 + 10,
3493 .vtotal = 160 + 24 + 10 + 6,
3494 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3495 },
3496 };
3497
3498 static const struct panel_desc sharp_ls020b1dd01d = {
3499 .modes = sharp_ls020b1dd01d_modes,
3500 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3501 .bpc = 6,
3502 .size = {
3503 .width = 42,
3504 .height = 28,
3505 },
3506 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3507 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3508 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3509 | DRM_BUS_FLAG_SHARP_SIGNALS,
3510 };
3511
3512 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3513 .clock = 33300,
3514 .hdisplay = 800,
3515 .hsync_start = 800 + 1,
3516 .hsync_end = 800 + 1 + 64,
3517 .htotal = 800 + 1 + 64 + 64,
3518 .vdisplay = 480,
3519 .vsync_start = 480 + 1,
3520 .vsync_end = 480 + 1 + 23,
3521 .vtotal = 480 + 1 + 23 + 22,
3522 };
3523
3524 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3525 .modes = &shelly_sca07010_bfn_lnn_mode,
3526 .num_modes = 1,
3527 .size = {
3528 .width = 152,
3529 .height = 91,
3530 },
3531 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3532 };
3533
3534 static const struct drm_display_mode starry_kr070pe2t_mode = {
3535 .clock = 33000,
3536 .hdisplay = 800,
3537 .hsync_start = 800 + 209,
3538 .hsync_end = 800 + 209 + 1,
3539 .htotal = 800 + 209 + 1 + 45,
3540 .vdisplay = 480,
3541 .vsync_start = 480 + 22,
3542 .vsync_end = 480 + 22 + 1,
3543 .vtotal = 480 + 22 + 1 + 22,
3544 };
3545
3546 static const struct panel_desc starry_kr070pe2t = {
3547 .modes = &starry_kr070pe2t_mode,
3548 .num_modes = 1,
3549 .bpc = 8,
3550 .size = {
3551 .width = 152,
3552 .height = 86,
3553 },
3554 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3555 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3556 .connector_type = DRM_MODE_CONNECTOR_DPI,
3557 };
3558
3559 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3560 .clock = 147000,
3561 .hdisplay = 1920,
3562 .hsync_start = 1920 + 16,
3563 .hsync_end = 1920 + 16 + 16,
3564 .htotal = 1920 + 16 + 16 + 32,
3565 .vdisplay = 1200,
3566 .vsync_start = 1200 + 15,
3567 .vsync_end = 1200 + 15 + 2,
3568 .vtotal = 1200 + 15 + 2 + 18,
3569 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3570 };
3571
3572 static const struct panel_desc starry_kr122ea0sra = {
3573 .modes = &starry_kr122ea0sra_mode,
3574 .num_modes = 1,
3575 .size = {
3576 .width = 263,
3577 .height = 164,
3578 },
3579 .delay = {
3580 .prepare = 10 + 200,
3581 .enable = 50,
3582 .unprepare = 10 + 500,
3583 },
3584 };
3585
3586 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3587 .clock = 30000,
3588 .hdisplay = 800,
3589 .hsync_start = 800 + 39,
3590 .hsync_end = 800 + 39 + 47,
3591 .htotal = 800 + 39 + 47 + 39,
3592 .vdisplay = 480,
3593 .vsync_start = 480 + 13,
3594 .vsync_end = 480 + 13 + 2,
3595 .vtotal = 480 + 13 + 2 + 29,
3596 };
3597
3598 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3599 .modes = &tfc_s9700rtwv43tr_01b_mode,
3600 .num_modes = 1,
3601 .bpc = 8,
3602 .size = {
3603 .width = 155,
3604 .height = 90,
3605 },
3606 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3607 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3608 };
3609
3610 static const struct display_timing tianma_tm070jdhg30_timing = {
3611 .pixelclock = { 62600000, 68200000, 78100000 },
3612 .hactive = { 1280, 1280, 1280 },
3613 .hfront_porch = { 15, 64, 159 },
3614 .hback_porch = { 5, 5, 5 },
3615 .hsync_len = { 1, 1, 256 },
3616 .vactive = { 800, 800, 800 },
3617 .vfront_porch = { 3, 40, 99 },
3618 .vback_porch = { 2, 2, 2 },
3619 .vsync_len = { 1, 1, 128 },
3620 .flags = DISPLAY_FLAGS_DE_HIGH,
3621 };
3622
3623 static const struct panel_desc tianma_tm070jdhg30 = {
3624 .timings = &tianma_tm070jdhg30_timing,
3625 .num_timings = 1,
3626 .bpc = 8,
3627 .size = {
3628 .width = 151,
3629 .height = 95,
3630 },
3631 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3632 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3633 };
3634
3635 static const struct panel_desc tianma_tm070jvhg33 = {
3636 .timings = &tianma_tm070jdhg30_timing,
3637 .num_timings = 1,
3638 .bpc = 8,
3639 .size = {
3640 .width = 150,
3641 .height = 94,
3642 },
3643 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3644 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3645 };
3646
3647 static const struct display_timing tianma_tm070rvhg71_timing = {
3648 .pixelclock = { 27700000, 29200000, 39600000 },
3649 .hactive = { 800, 800, 800 },
3650 .hfront_porch = { 12, 40, 212 },
3651 .hback_porch = { 88, 88, 88 },
3652 .hsync_len = { 1, 1, 40 },
3653 .vactive = { 480, 480, 480 },
3654 .vfront_porch = { 1, 13, 88 },
3655 .vback_porch = { 32, 32, 32 },
3656 .vsync_len = { 1, 1, 3 },
3657 .flags = DISPLAY_FLAGS_DE_HIGH,
3658 };
3659
3660 static const struct panel_desc tianma_tm070rvhg71 = {
3661 .timings = &tianma_tm070rvhg71_timing,
3662 .num_timings = 1,
3663 .bpc = 8,
3664 .size = {
3665 .width = 154,
3666 .height = 86,
3667 },
3668 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3669 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3670 };
3671
3672 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3673 {
3674 .clock = 10000,
3675 .hdisplay = 320,
3676 .hsync_start = 320 + 50,
3677 .hsync_end = 320 + 50 + 6,
3678 .htotal = 320 + 50 + 6 + 38,
3679 .vdisplay = 240,
3680 .vsync_start = 240 + 3,
3681 .vsync_end = 240 + 3 + 1,
3682 .vtotal = 240 + 3 + 1 + 17,
3683 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3684 },
3685 };
3686
3687 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3688 .modes = ti_nspire_cx_lcd_mode,
3689 .num_modes = 1,
3690 .bpc = 8,
3691 .size = {
3692 .width = 65,
3693 .height = 49,
3694 },
3695 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3696 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3697 };
3698
3699 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3700 {
3701 .clock = 10000,
3702 .hdisplay = 320,
3703 .hsync_start = 320 + 6,
3704 .hsync_end = 320 + 6 + 6,
3705 .htotal = 320 + 6 + 6 + 6,
3706 .vdisplay = 240,
3707 .vsync_start = 240 + 0,
3708 .vsync_end = 240 + 0 + 1,
3709 .vtotal = 240 + 0 + 1 + 0,
3710 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3711 },
3712 };
3713
3714 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3715 .modes = ti_nspire_classic_lcd_mode,
3716 .num_modes = 1,
3717 /* The grayscale panel has 8 bit for the color .. Y (black) */
3718 .bpc = 8,
3719 .size = {
3720 .width = 71,
3721 .height = 53,
3722 },
3723 /* This is the grayscale bus format */
3724 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3725 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3726 };
3727
3728 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3729 .clock = 79500,
3730 .hdisplay = 1280,
3731 .hsync_start = 1280 + 192,
3732 .hsync_end = 1280 + 192 + 128,
3733 .htotal = 1280 + 192 + 128 + 64,
3734 .vdisplay = 768,
3735 .vsync_start = 768 + 20,
3736 .vsync_end = 768 + 20 + 7,
3737 .vtotal = 768 + 20 + 7 + 3,
3738 };
3739
3740 static const struct panel_desc toshiba_lt089ac29000 = {
3741 .modes = &toshiba_lt089ac29000_mode,
3742 .num_modes = 1,
3743 .size = {
3744 .width = 194,
3745 .height = 116,
3746 },
3747 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3748 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3749 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3750 };
3751
3752 static const struct drm_display_mode tpk_f07a_0102_mode = {
3753 .clock = 33260,
3754 .hdisplay = 800,
3755 .hsync_start = 800 + 40,
3756 .hsync_end = 800 + 40 + 128,
3757 .htotal = 800 + 40 + 128 + 88,
3758 .vdisplay = 480,
3759 .vsync_start = 480 + 10,
3760 .vsync_end = 480 + 10 + 2,
3761 .vtotal = 480 + 10 + 2 + 33,
3762 };
3763
3764 static const struct panel_desc tpk_f07a_0102 = {
3765 .modes = &tpk_f07a_0102_mode,
3766 .num_modes = 1,
3767 .size = {
3768 .width = 152,
3769 .height = 91,
3770 },
3771 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3772 };
3773
3774 static const struct drm_display_mode tpk_f10a_0102_mode = {
3775 .clock = 45000,
3776 .hdisplay = 1024,
3777 .hsync_start = 1024 + 176,
3778 .hsync_end = 1024 + 176 + 5,
3779 .htotal = 1024 + 176 + 5 + 88,
3780 .vdisplay = 600,
3781 .vsync_start = 600 + 20,
3782 .vsync_end = 600 + 20 + 5,
3783 .vtotal = 600 + 20 + 5 + 25,
3784 };
3785
3786 static const struct panel_desc tpk_f10a_0102 = {
3787 .modes = &tpk_f10a_0102_mode,
3788 .num_modes = 1,
3789 .size = {
3790 .width = 223,
3791 .height = 125,
3792 },
3793 };
3794
3795 static const struct display_timing urt_umsh_8596md_timing = {
3796 .pixelclock = { 33260000, 33260000, 33260000 },
3797 .hactive = { 800, 800, 800 },
3798 .hfront_porch = { 41, 41, 41 },
3799 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3800 .hsync_len = { 71, 128, 128 },
3801 .vactive = { 480, 480, 480 },
3802 .vfront_porch = { 10, 10, 10 },
3803 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3804 .vsync_len = { 2, 2, 2 },
3805 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3806 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3807 };
3808
3809 static const struct panel_desc urt_umsh_8596md_lvds = {
3810 .timings = &urt_umsh_8596md_timing,
3811 .num_timings = 1,
3812 .bpc = 6,
3813 .size = {
3814 .width = 152,
3815 .height = 91,
3816 },
3817 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3818 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3819 };
3820
3821 static const struct panel_desc urt_umsh_8596md_parallel = {
3822 .timings = &urt_umsh_8596md_timing,
3823 .num_timings = 1,
3824 .bpc = 6,
3825 .size = {
3826 .width = 152,
3827 .height = 91,
3828 },
3829 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3830 };
3831
3832 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3833 .clock = 33333,
3834 .hdisplay = 800,
3835 .hsync_start = 800 + 210,
3836 .hsync_end = 800 + 210 + 20,
3837 .htotal = 800 + 210 + 20 + 46,
3838 .vdisplay = 480,
3839 .vsync_start = 480 + 22,
3840 .vsync_end = 480 + 22 + 10,
3841 .vtotal = 480 + 22 + 10 + 23,
3842 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3843 };
3844
3845 static const struct panel_desc vl050_8048nt_c01 = {
3846 .modes = &vl050_8048nt_c01_mode,
3847 .num_modes = 1,
3848 .bpc = 8,
3849 .size = {
3850 .width = 120,
3851 .height = 76,
3852 },
3853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3855 };
3856
3857 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3858 .clock = 6410,
3859 .hdisplay = 320,
3860 .hsync_start = 320 + 20,
3861 .hsync_end = 320 + 20 + 30,
3862 .htotal = 320 + 20 + 30 + 38,
3863 .vdisplay = 240,
3864 .vsync_start = 240 + 4,
3865 .vsync_end = 240 + 4 + 3,
3866 .vtotal = 240 + 4 + 3 + 15,
3867 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3868 };
3869
3870 static const struct panel_desc winstar_wf35ltiacd = {
3871 .modes = &winstar_wf35ltiacd_mode,
3872 .num_modes = 1,
3873 .bpc = 8,
3874 .size = {
3875 .width = 70,
3876 .height = 53,
3877 },
3878 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3879 };
3880
3881 static const struct drm_display_mode arm_rtsm_mode[] = {
3882 {
3883 .clock = 65000,
3884 .hdisplay = 1024,
3885 .hsync_start = 1024 + 24,
3886 .hsync_end = 1024 + 24 + 136,
3887 .htotal = 1024 + 24 + 136 + 160,
3888 .vdisplay = 768,
3889 .vsync_start = 768 + 3,
3890 .vsync_end = 768 + 3 + 6,
3891 .vtotal = 768 + 3 + 6 + 29,
3892 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3893 },
3894 };
3895
3896 static const struct panel_desc arm_rtsm = {
3897 .modes = arm_rtsm_mode,
3898 .num_modes = 1,
3899 .bpc = 8,
3900 .size = {
3901 .width = 400,
3902 .height = 300,
3903 },
3904 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3905 };
3906
3907 static const struct of_device_id platform_of_match[] = {
3908 {
3909 .compatible = "ampire,am-1280800n3tzqw-t00h",
3910 .data = &ire_am_1280800n3tzqw_t00h,
3911 }, {
3912 .compatible = "ampire,am-480272h3tmqw-t01h",
3913 .data = &ire_am_480272h3tmqw_t01h,
3914 }, {
3915 .compatible = "ampire,am800480r3tmqwa1h",
3916 .data = &ire_am800480r3tmqwa1h,
3917 }, {
3918 .compatible = "arm,rtsm-display",
3919 .data = &arm_rtsm,
3920 }, {
3921 .compatible = "armadeus,st0700-adapt",
3922 .data = &armadeus_st0700_adapt,
3923 }, {
3924 .compatible = "auo,b101aw03",
3925 .data = &auo_b101aw03,
3926 }, {
3927 .compatible = "auo,b101ean01",
3928 .data = &auo_b101ean01,
3929 }, {
3930 .compatible = "auo,b101xtn01",
3931 .data = &auo_b101xtn01,
3932 }, {
3933 .compatible = "auo,b116xa01",
3934 .data = &auo_b116xak01,
3935 }, {
3936 .compatible = "auo,b116xw03",
3937 .data = &auo_b116xw03,
3938 }, {
3939 .compatible = "auo,b133htn01",
3940 .data = &auo_b133htn01,
3941 }, {
3942 .compatible = "auo,b133xtn01",
3943 .data = &auo_b133xtn01,
3944 }, {
3945 .compatible = "auo,g070vvn01",
3946 .data = &auo_g070vvn01,
3947 }, {
3948 .compatible = "auo,g101evn010",
3949 .data = &auo_g101evn010,
3950 }, {
3951 .compatible = "auo,g104sn02",
3952 .data = &auo_g104sn02,
3953 }, {
3954 .compatible = "auo,g121ean01",
3955 .data = &auo_g121ean01,
3956 }, {
3957 .compatible = "auo,g133han01",
3958 .data = &auo_g133han01,
3959 }, {
3960 .compatible = "auo,g156xtn01",
3961 .data = &auo_g156xtn01,
3962 }, {
3963 .compatible = "auo,g185han01",
3964 .data = &auo_g185han01,
3965 }, {
3966 .compatible = "auo,g190ean01",
3967 .data = &auo_g190ean01,
3968 }, {
3969 .compatible = "auo,p320hvn03",
3970 .data = &auo_p320hvn03,
3971 }, {
3972 .compatible = "auo,t215hvn01",
3973 .data = &auo_t215hvn01,
3974 }, {
3975 .compatible = "avic,tm070ddh03",
3976 .data = &avic_tm070ddh03,
3977 }, {
3978 .compatible = "bananapi,s070wv20-ct16",
3979 .data = &bananapi_s070wv20_ct16,
3980 }, {
3981 .compatible = "boe,hv070wsa-100",
3982 .data = &boe_hv070wsa
3983 }, {
3984 .compatible = "boe,nv101wxmn51",
3985 .data = &boe_nv101wxmn51,
3986 }, {
3987 .compatible = "boe,nv133fhm-n61",
3988 .data = &boe_nv133fhm_n61,
3989 }, {
3990 .compatible = "boe,nv133fhm-n62",
3991 .data = &boe_nv133fhm_n61,
3992 }, {
3993 .compatible = "boe,nv140fhmn49",
3994 .data = &boe_nv140fhmn49,
3995 }, {
3996 .compatible = "cdtech,s043wq26h-ct7",
3997 .data = &cdtech_s043wq26h_ct7,
3998 }, {
3999 .compatible = "cdtech,s070pws19hp-fc21",
4000 .data = &cdtech_s070pws19hp_fc21,
4001 }, {
4002 .compatible = "cdtech,s070swv29hg-dc44",
4003 .data = &cdtech_s070swv29hg_dc44,
4004 }, {
4005 .compatible = "cdtech,s070wv95-ct16",
4006 .data = &cdtech_s070wv95_ct16,
4007 }, {
4008 .compatible = "chefree,ch101olhlwh-002",
4009 .data = &chefree_ch101olhlwh_002,
4010 }, {
4011 .compatible = "chunghwa,claa070wp03xg",
4012 .data = &chunghwa_claa070wp03xg,
4013 }, {
4014 .compatible = "chunghwa,claa101wa01a",
4015 .data = &chunghwa_claa101wa01a
4016 }, {
4017 .compatible = "chunghwa,claa101wb01",
4018 .data = &chunghwa_claa101wb01
4019 }, {
4020 .compatible = "dataimage,scf0700c48ggu18",
4021 .data = &dataimage_scf0700c48ggu18,
4022 }, {
4023 .compatible = "dlc,dlc0700yzg-1",
4024 .data = &dlc_dlc0700yzg_1,
4025 }, {
4026 .compatible = "dlc,dlc1010gig",
4027 .data = &dlc_dlc1010gig,
4028 }, {
4029 .compatible = "edt,et035012dm6",
4030 .data = &edt_et035012dm6,
4031 }, {
4032 .compatible = "edt,etm043080dh6gp",
4033 .data = &edt_etm043080dh6gp,
4034 }, {
4035 .compatible = "edt,etm0430g0dh6",
4036 .data = &edt_etm0430g0dh6,
4037 }, {
4038 .compatible = "edt,et057090dhu",
4039 .data = &edt_et057090dhu,
4040 }, {
4041 .compatible = "edt,et070080dh6",
4042 .data = &edt_etm0700g0dh6,
4043 }, {
4044 .compatible = "edt,etm0700g0dh6",
4045 .data = &edt_etm0700g0dh6,
4046 }, {
4047 .compatible = "edt,etm0700g0bdh6",
4048 .data = &edt_etm0700g0bdh6,
4049 }, {
4050 .compatible = "edt,etm0700g0edh6",
4051 .data = &edt_etm0700g0bdh6,
4052 }, {
4053 .compatible = "evervision,vgg804821",
4054 .data = &evervision_vgg804821,
4055 }, {
4056 .compatible = "foxlink,fl500wvr00-a0t",
4057 .data = &foxlink_fl500wvr00_a0t,
4058 }, {
4059 .compatible = "frida,frd350h54004",
4060 .data = &frida_frd350h54004,
4061 }, {
4062 .compatible = "friendlyarm,hd702e",
4063 .data = &friendlyarm_hd702e,
4064 }, {
4065 .compatible = "giantplus,gpg482739qs5",
4066 .data = &giantplus_gpg482739qs5
4067 }, {
4068 .compatible = "giantplus,gpm940b0",
4069 .data = &giantplus_gpm940b0,
4070 }, {
4071 .compatible = "hannstar,hsd070pww1",
4072 .data = &hannstar_hsd070pww1,
4073 }, {
4074 .compatible = "hannstar,hsd100pxn1",
4075 .data = &hannstar_hsd100pxn1,
4076 }, {
4077 .compatible = "hit,tx23d38vm0caa",
4078 .data = &hitachi_tx23d38vm0caa
4079 }, {
4080 .compatible = "innolux,at043tn24",
4081 .data = &innolux_at043tn24,
4082 }, {
4083 .compatible = "innolux,at070tn92",
4084 .data = &innolux_at070tn92,
4085 }, {
4086 .compatible = "innolux,g070y2-l01",
4087 .data = &innolux_g070y2_l01,
4088 }, {
4089 .compatible = "innolux,g101ice-l01",
4090 .data = &innolux_g101ice_l01
4091 }, {
4092 .compatible = "innolux,g121i1-l01",
4093 .data = &innolux_g121i1_l01
4094 }, {
4095 .compatible = "innolux,g121x1-l03",
4096 .data = &innolux_g121x1_l03,
4097 }, {
4098 .compatible = "innolux,n116bge",
4099 .data = &innolux_n116bge,
4100 }, {
4101 .compatible = "innolux,n156bge-l21",
4102 .data = &innolux_n156bge_l21,
4103 }, {
4104 .compatible = "innolux,p120zdg-bf1",
4105 .data = &innolux_p120zdg_bf1,
4106 }, {
4107 .compatible = "innolux,zj070na-01p",
4108 .data = &innolux_zj070na_01p,
4109 }, {
4110 .compatible = "ivo,m133nwf4-r0",
4111 .data = &ivo_m133nwf4_r0,
4112 }, {
4113 .compatible = "kingdisplay,kd116n21-30nv-a010",
4114 .data = &kingdisplay_kd116n21_30nv_a010,
4115 }, {
4116 .compatible = "koe,tx14d24vm1bpa",
4117 .data = &koe_tx14d24vm1bpa,
4118 }, {
4119 .compatible = "koe,tx26d202vm0bwa",
4120 .data = &koe_tx26d202vm0bwa,
4121 }, {
4122 .compatible = "koe,tx31d200vm0baa",
4123 .data = &koe_tx31d200vm0baa,
4124 }, {
4125 .compatible = "kyo,tcg121xglp",
4126 .data = &kyo_tcg121xglp,
4127 }, {
4128 .compatible = "lemaker,bl035-rgb-002",
4129 .data = &lemaker_bl035_rgb_002,
4130 }, {
4131 .compatible = "lg,lb070wv8",
4132 .data = &lg_lb070wv8,
4133 }, {
4134 .compatible = "lg,lp079qx1-sp0v",
4135 .data = &lg_lp079qx1_sp0v,
4136 }, {
4137 .compatible = "lg,lp097qx1-spa1",
4138 .data = &lg_lp097qx1_spa1,
4139 }, {
4140 .compatible = "lg,lp120up1",
4141 .data = &lg_lp120up1,
4142 }, {
4143 .compatible = "lg,lp129qe",
4144 .data = &lg_lp129qe,
4145 }, {
4146 .compatible = "logicpd,type28",
4147 .data = &logicpd_type_28,
4148 }, {
4149 .compatible = "logictechno,lt161010-2nhc",
4150 .data = &logictechno_lt161010_2nh,
4151 }, {
4152 .compatible = "logictechno,lt161010-2nhr",
4153 .data = &logictechno_lt161010_2nh,
4154 }, {
4155 .compatible = "logictechno,lt170410-2whc",
4156 .data = &logictechno_lt170410_2whc,
4157 }, {
4158 .compatible = "mitsubishi,aa070mc01-ca1",
4159 .data = &mitsubishi_aa070mc01,
4160 }, {
4161 .compatible = "nec,nl12880bc20-05",
4162 .data = &nec_nl12880bc20_05,
4163 }, {
4164 .compatible = "nec,nl4827hc19-05b",
4165 .data = &nec_nl4827hc19_05b,
4166 }, {
4167 .compatible = "netron-dy,e231732",
4168 .data = &netron_dy_e231732,
4169 }, {
4170 .compatible = "neweast,wjfh116008a",
4171 .data = &neweast_wjfh116008a,
4172 }, {
4173 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4174 .data = &newhaven_nhd_43_480272ef_atxl,
4175 }, {
4176 .compatible = "nlt,nl192108ac18-02d",
4177 .data = &nlt_nl192108ac18_02d,
4178 }, {
4179 .compatible = "nvd,9128",
4180 .data = &nvd_9128,
4181 }, {
4182 .compatible = "okaya,rs800480t-7x0gp",
4183 .data = &okaya_rs800480t_7x0gp,
4184 }, {
4185 .compatible = "olimex,lcd-olinuxino-43-ts",
4186 .data = &olimex_lcd_olinuxino_43ts,
4187 }, {
4188 .compatible = "ontat,yx700wv03",
4189 .data = &ontat_yx700wv03,
4190 }, {
4191 .compatible = "ortustech,com37h3m05dtc",
4192 .data = &ortustech_com37h3m,
4193 }, {
4194 .compatible = "ortustech,com37h3m99dtc",
4195 .data = &ortustech_com37h3m,
4196 }, {
4197 .compatible = "ortustech,com43h4m85ulc",
4198 .data = &ortustech_com43h4m85ulc,
4199 }, {
4200 .compatible = "osddisplays,osd070t1718-19ts",
4201 .data = &osddisplays_osd070t1718_19ts,
4202 }, {
4203 .compatible = "pda,91-00156-a0",
4204 .data = &pda_91_00156_a0,
4205 }, {
4206 .compatible = "powertip,ph800480t013-idf02",
4207 .data = &powertip_ph800480t013_idf02,
4208 }, {
4209 .compatible = "qiaodian,qd43003c0-40",
4210 .data = &qd43003c0_40,
4211 }, {
4212 .compatible = "rocktech,rk070er9427",
4213 .data = &rocktech_rk070er9427,
4214 }, {
4215 .compatible = "rocktech,rk101ii01d-ct",
4216 .data = &rocktech_rk101ii01d_ct,
4217 }, {
4218 .compatible = "samsung,lsn122dl01-c01",
4219 .data = &samsung_lsn122dl01_c01,
4220 }, {
4221 .compatible = "samsung,ltn101nt05",
4222 .data = &samsung_ltn101nt05,
4223 }, {
4224 .compatible = "samsung,ltn140at29-301",
4225 .data = &samsung_ltn140at29_301,
4226 }, {
4227 .compatible = "satoz,sat050at40h12r2",
4228 .data = &satoz_sat050at40h12r2,
4229 }, {
4230 .compatible = "sharp,ld-d5116z01b",
4231 .data = &sharp_ld_d5116z01b,
4232 }, {
4233 .compatible = "sharp,lq035q7db03",
4234 .data = &sharp_lq035q7db03,
4235 }, {
4236 .compatible = "sharp,lq070y3dg3b",
4237 .data = &sharp_lq070y3dg3b,
4238 }, {
4239 .compatible = "sharp,lq101k1ly04",
4240 .data = &sharp_lq101k1ly04,
4241 }, {
4242 .compatible = "sharp,lq123p1jx31",
4243 .data = &sharp_lq123p1jx31,
4244 }, {
4245 .compatible = "sharp,ls020b1dd01d",
4246 .data = &sharp_ls020b1dd01d,
4247 }, {
4248 .compatible = "shelly,sca07010-bfn-lnn",
4249 .data = &shelly_sca07010_bfn_lnn,
4250 }, {
4251 .compatible = "starry,kr070pe2t",
4252 .data = &starry_kr070pe2t,
4253 }, {
4254 .compatible = "starry,kr122ea0sra",
4255 .data = &starry_kr122ea0sra,
4256 }, {
4257 .compatible = "tfc,s9700rtwv43tr-01b",
4258 .data = &tfc_s9700rtwv43tr_01b,
4259 }, {
4260 .compatible = "tianma,tm070jdhg30",
4261 .data = &tianma_tm070jdhg30,
4262 }, {
4263 .compatible = "tianma,tm070jvhg33",
4264 .data = &tianma_tm070jvhg33,
4265 }, {
4266 .compatible = "tianma,tm070rvhg71",
4267 .data = &tianma_tm070rvhg71,
4268 }, {
4269 .compatible = "ti,nspire-cx-lcd-panel",
4270 .data = &ti_nspire_cx_lcd_panel,
4271 }, {
4272 .compatible = "ti,nspire-classic-lcd-panel",
4273 .data = &ti_nspire_classic_lcd_panel,
4274 }, {
4275 .compatible = "toshiba,lt089ac29000",
4276 .data = &toshiba_lt089ac29000,
4277 }, {
4278 .compatible = "tpk,f07a-0102",
4279 .data = &tpk_f07a_0102,
4280 }, {
4281 .compatible = "tpk,f10a-0102",
4282 .data = &tpk_f10a_0102,
4283 }, {
4284 .compatible = "urt,umsh-8596md-t",
4285 .data = &urt_umsh_8596md_parallel,
4286 }, {
4287 .compatible = "urt,umsh-8596md-1t",
4288 .data = &urt_umsh_8596md_parallel,
4289 }, {
4290 .compatible = "urt,umsh-8596md-7t",
4291 .data = &urt_umsh_8596md_parallel,
4292 }, {
4293 .compatible = "urt,umsh-8596md-11t",
4294 .data = &urt_umsh_8596md_lvds,
4295 }, {
4296 .compatible = "urt,umsh-8596md-19t",
4297 .data = &urt_umsh_8596md_lvds,
4298 }, {
4299 .compatible = "urt,umsh-8596md-20t",
4300 .data = &urt_umsh_8596md_parallel,
4301 }, {
4302 .compatible = "vxt,vl050-8048nt-c01",
4303 .data = &vl050_8048nt_c01,
4304 }, {
4305 .compatible = "winstar,wf35ltiacd",
4306 .data = &winstar_wf35ltiacd,
4307 }, {
4308 /* Must be the last entry */
4309 .compatible = "panel-dpi",
4310 .data = &panel_dpi,
4311 }, {
4312 /* sentinel */
4313 }
4314 };
4315 MODULE_DEVICE_TABLE(of, platform_of_match);
4316
panel_simple_platform_probe(struct platform_device * pdev)4317 static int panel_simple_platform_probe(struct platform_device *pdev)
4318 {
4319 const struct of_device_id *id;
4320
4321 id = of_match_node(platform_of_match, pdev->dev.of_node);
4322 if (!id)
4323 return -ENODEV;
4324
4325 return panel_simple_probe(&pdev->dev, id->data);
4326 }
4327
panel_simple_platform_remove(struct platform_device * pdev)4328 static int panel_simple_platform_remove(struct platform_device *pdev)
4329 {
4330 return panel_simple_remove(&pdev->dev);
4331 }
4332
panel_simple_platform_shutdown(struct platform_device * pdev)4333 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4334 {
4335 panel_simple_shutdown(&pdev->dev);
4336 }
4337
4338 static struct platform_driver panel_simple_platform_driver = {
4339 .driver = {
4340 .name = "panel-simple",
4341 .of_match_table = platform_of_match,
4342 },
4343 .probe = panel_simple_platform_probe,
4344 .remove = panel_simple_platform_remove,
4345 .shutdown = panel_simple_platform_shutdown,
4346 };
4347
4348 struct panel_desc_dsi {
4349 struct panel_desc desc;
4350
4351 unsigned long flags;
4352 enum mipi_dsi_pixel_format format;
4353 unsigned int lanes;
4354 };
4355
4356 static const struct drm_display_mode auo_b080uan01_mode = {
4357 .clock = 154500,
4358 .hdisplay = 1200,
4359 .hsync_start = 1200 + 62,
4360 .hsync_end = 1200 + 62 + 4,
4361 .htotal = 1200 + 62 + 4 + 62,
4362 .vdisplay = 1920,
4363 .vsync_start = 1920 + 9,
4364 .vsync_end = 1920 + 9 + 2,
4365 .vtotal = 1920 + 9 + 2 + 8,
4366 };
4367
4368 static const struct panel_desc_dsi auo_b080uan01 = {
4369 .desc = {
4370 .modes = &auo_b080uan01_mode,
4371 .num_modes = 1,
4372 .bpc = 8,
4373 .size = {
4374 .width = 108,
4375 .height = 272,
4376 },
4377 .connector_type = DRM_MODE_CONNECTOR_DSI,
4378 },
4379 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4380 .format = MIPI_DSI_FMT_RGB888,
4381 .lanes = 4,
4382 };
4383
4384 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4385 .clock = 160000,
4386 .hdisplay = 1200,
4387 .hsync_start = 1200 + 120,
4388 .hsync_end = 1200 + 120 + 20,
4389 .htotal = 1200 + 120 + 20 + 21,
4390 .vdisplay = 1920,
4391 .vsync_start = 1920 + 21,
4392 .vsync_end = 1920 + 21 + 3,
4393 .vtotal = 1920 + 21 + 3 + 18,
4394 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4395 };
4396
4397 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4398 .desc = {
4399 .modes = &boe_tv080wum_nl0_mode,
4400 .num_modes = 1,
4401 .size = {
4402 .width = 107,
4403 .height = 172,
4404 },
4405 .connector_type = DRM_MODE_CONNECTOR_DSI,
4406 },
4407 .flags = MIPI_DSI_MODE_VIDEO |
4408 MIPI_DSI_MODE_VIDEO_BURST |
4409 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4410 .format = MIPI_DSI_FMT_RGB888,
4411 .lanes = 4,
4412 };
4413
4414 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4415 .clock = 71000,
4416 .hdisplay = 800,
4417 .hsync_start = 800 + 32,
4418 .hsync_end = 800 + 32 + 1,
4419 .htotal = 800 + 32 + 1 + 57,
4420 .vdisplay = 1280,
4421 .vsync_start = 1280 + 28,
4422 .vsync_end = 1280 + 28 + 1,
4423 .vtotal = 1280 + 28 + 1 + 14,
4424 };
4425
4426 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4427 .desc = {
4428 .modes = &lg_ld070wx3_sl01_mode,
4429 .num_modes = 1,
4430 .bpc = 8,
4431 .size = {
4432 .width = 94,
4433 .height = 151,
4434 },
4435 .connector_type = DRM_MODE_CONNECTOR_DSI,
4436 },
4437 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4438 .format = MIPI_DSI_FMT_RGB888,
4439 .lanes = 4,
4440 };
4441
4442 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4443 .clock = 67000,
4444 .hdisplay = 720,
4445 .hsync_start = 720 + 12,
4446 .hsync_end = 720 + 12 + 4,
4447 .htotal = 720 + 12 + 4 + 112,
4448 .vdisplay = 1280,
4449 .vsync_start = 1280 + 8,
4450 .vsync_end = 1280 + 8 + 4,
4451 .vtotal = 1280 + 8 + 4 + 12,
4452 };
4453
4454 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4455 .desc = {
4456 .modes = &lg_lh500wx1_sd03_mode,
4457 .num_modes = 1,
4458 .bpc = 8,
4459 .size = {
4460 .width = 62,
4461 .height = 110,
4462 },
4463 .connector_type = DRM_MODE_CONNECTOR_DSI,
4464 },
4465 .flags = MIPI_DSI_MODE_VIDEO,
4466 .format = MIPI_DSI_FMT_RGB888,
4467 .lanes = 4,
4468 };
4469
4470 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4471 .clock = 157200,
4472 .hdisplay = 1920,
4473 .hsync_start = 1920 + 154,
4474 .hsync_end = 1920 + 154 + 16,
4475 .htotal = 1920 + 154 + 16 + 32,
4476 .vdisplay = 1200,
4477 .vsync_start = 1200 + 17,
4478 .vsync_end = 1200 + 17 + 2,
4479 .vtotal = 1200 + 17 + 2 + 16,
4480 };
4481
4482 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4483 .desc = {
4484 .modes = &panasonic_vvx10f004b00_mode,
4485 .num_modes = 1,
4486 .bpc = 8,
4487 .size = {
4488 .width = 217,
4489 .height = 136,
4490 },
4491 .connector_type = DRM_MODE_CONNECTOR_DSI,
4492 },
4493 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4494 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4495 .format = MIPI_DSI_FMT_RGB888,
4496 .lanes = 4,
4497 };
4498
4499 static const struct drm_display_mode lg_acx467akm_7_mode = {
4500 .clock = 150000,
4501 .hdisplay = 1080,
4502 .hsync_start = 1080 + 2,
4503 .hsync_end = 1080 + 2 + 2,
4504 .htotal = 1080 + 2 + 2 + 2,
4505 .vdisplay = 1920,
4506 .vsync_start = 1920 + 2,
4507 .vsync_end = 1920 + 2 + 2,
4508 .vtotal = 1920 + 2 + 2 + 2,
4509 };
4510
4511 static const struct panel_desc_dsi lg_acx467akm_7 = {
4512 .desc = {
4513 .modes = &lg_acx467akm_7_mode,
4514 .num_modes = 1,
4515 .bpc = 8,
4516 .size = {
4517 .width = 62,
4518 .height = 110,
4519 },
4520 .connector_type = DRM_MODE_CONNECTOR_DSI,
4521 },
4522 .flags = 0,
4523 .format = MIPI_DSI_FMT_RGB888,
4524 .lanes = 4,
4525 };
4526
4527 static const struct drm_display_mode osd101t2045_53ts_mode = {
4528 .clock = 154500,
4529 .hdisplay = 1920,
4530 .hsync_start = 1920 + 112,
4531 .hsync_end = 1920 + 112 + 16,
4532 .htotal = 1920 + 112 + 16 + 32,
4533 .vdisplay = 1200,
4534 .vsync_start = 1200 + 16,
4535 .vsync_end = 1200 + 16 + 2,
4536 .vtotal = 1200 + 16 + 2 + 16,
4537 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4538 };
4539
4540 static const struct panel_desc_dsi osd101t2045_53ts = {
4541 .desc = {
4542 .modes = &osd101t2045_53ts_mode,
4543 .num_modes = 1,
4544 .bpc = 8,
4545 .size = {
4546 .width = 217,
4547 .height = 136,
4548 },
4549 .connector_type = DRM_MODE_CONNECTOR_DSI,
4550 },
4551 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4552 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4553 MIPI_DSI_MODE_EOT_PACKET,
4554 .format = MIPI_DSI_FMT_RGB888,
4555 .lanes = 4,
4556 };
4557
4558 static const struct of_device_id dsi_of_match[] = {
4559 {
4560 .compatible = "auo,b080uan01",
4561 .data = &auo_b080uan01
4562 }, {
4563 .compatible = "boe,tv080wum-nl0",
4564 .data = &boe_tv080wum_nl0
4565 }, {
4566 .compatible = "lg,ld070wx3-sl01",
4567 .data = &lg_ld070wx3_sl01
4568 }, {
4569 .compatible = "lg,lh500wx1-sd03",
4570 .data = &lg_lh500wx1_sd03
4571 }, {
4572 .compatible = "panasonic,vvx10f004b00",
4573 .data = &panasonic_vvx10f004b00
4574 }, {
4575 .compatible = "lg,acx467akm-7",
4576 .data = &lg_acx467akm_7
4577 }, {
4578 .compatible = "osddisplays,osd101t2045-53ts",
4579 .data = &osd101t2045_53ts
4580 }, {
4581 /* sentinel */
4582 }
4583 };
4584 MODULE_DEVICE_TABLE(of, dsi_of_match);
4585
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)4586 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4587 {
4588 const struct panel_desc_dsi *desc;
4589 const struct of_device_id *id;
4590 int err;
4591
4592 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4593 if (!id)
4594 return -ENODEV;
4595
4596 desc = id->data;
4597
4598 err = panel_simple_probe(&dsi->dev, &desc->desc);
4599 if (err < 0)
4600 return err;
4601
4602 dsi->mode_flags = desc->flags;
4603 dsi->format = desc->format;
4604 dsi->lanes = desc->lanes;
4605
4606 err = mipi_dsi_attach(dsi);
4607 if (err) {
4608 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4609
4610 drm_panel_remove(&panel->base);
4611 }
4612
4613 return err;
4614 }
4615
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)4616 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4617 {
4618 int err;
4619
4620 err = mipi_dsi_detach(dsi);
4621 if (err < 0)
4622 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4623
4624 return panel_simple_remove(&dsi->dev);
4625 }
4626
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)4627 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4628 {
4629 panel_simple_shutdown(&dsi->dev);
4630 }
4631
4632 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4633 .driver = {
4634 .name = "panel-simple-dsi",
4635 .of_match_table = dsi_of_match,
4636 },
4637 .probe = panel_simple_dsi_probe,
4638 .remove = panel_simple_dsi_remove,
4639 .shutdown = panel_simple_dsi_shutdown,
4640 };
4641
panel_simple_init(void)4642 static int __init panel_simple_init(void)
4643 {
4644 int err;
4645
4646 err = platform_driver_register(&panel_simple_platform_driver);
4647 if (err < 0)
4648 return err;
4649
4650 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4651 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4652 if (err < 0)
4653 return err;
4654 }
4655
4656 return 0;
4657 }
4658 module_init(panel_simple_init);
4659
panel_simple_exit(void)4660 static void __exit panel_simple_exit(void)
4661 {
4662 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4663 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4664
4665 platform_driver_unregister(&panel_simple_platform_driver);
4666 }
4667 module_exit(panel_simple_exit);
4668
4669 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4670 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4671 MODULE_LICENSE("GPL and additional rights");
4672