1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2017
4 *
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 * Fabien Dessenne <fabien.dessenne@st.com>
8 * Mickael Reulier <mickael.reulier@st.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/component.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_graph.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/reset.h>
22
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_device.h>
27 #include <drm/drm_fb_cma_helper.h>
28 #include <drm/drm_fourcc.h>
29 #include <drm/drm_gem_cma_helper.h>
30 #include <drm/drm_gem_framebuffer_helper.h>
31 #include <drm/drm_of.h>
32 #include <drm/drm_plane_helper.h>
33 #include <drm/drm_probe_helper.h>
34 #include <drm/drm_vblank.h>
35
36 #include <video/videomode.h>
37
38 #include "ltdc.h"
39
40 #define NB_CRTC 1
41 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
42
43 #define MAX_IRQ 4
44
45 #define HWVER_10200 0x010200
46 #define HWVER_10300 0x010300
47 #define HWVER_20101 0x020101
48
49 /*
50 * The address of some registers depends on the HW version: such registers have
51 * an extra offset specified with reg_ofs.
52 */
53 #define REG_OFS_NONE 0
54 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */
55 #define REG_OFS (ldev->caps.reg_ofs)
56 #define LAY_OFS 0x80 /* Register Offset between 2 layers */
57
58 /* Global register offsets */
59 #define LTDC_IDR 0x0000 /* IDentification */
60 #define LTDC_LCR 0x0004 /* Layer Count */
61 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
62 #define LTDC_BPCR 0x000C /* Back Porch Configuration */
63 #define LTDC_AWCR 0x0010 /* Active Width Configuration */
64 #define LTDC_TWCR 0x0014 /* Total Width Configuration */
65 #define LTDC_GCR 0x0018 /* Global Control */
66 #define LTDC_GC1R 0x001C /* Global Configuration 1 */
67 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */
68 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
69 #define LTDC_GACR 0x0028 /* GAmma Correction */
70 #define LTDC_BCCR 0x002C /* Background Color Configuration */
71 #define LTDC_IER 0x0034 /* Interrupt Enable */
72 #define LTDC_ISR 0x0038 /* Interrupt Status */
73 #define LTDC_ICR 0x003C /* Interrupt Clear */
74 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */
75 #define LTDC_CPSR 0x0044 /* Current Position Status */
76 #define LTDC_CDSR 0x0048 /* Current Display Status */
77
78 /* Layer register offsets */
79 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */
80 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */
81 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */
82 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */
83 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */
84 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */
85 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */
86 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */
87 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */
88 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */
89 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */
90 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */
91 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */
92 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */
93 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */
94 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */
95 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */
96 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */
97 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */
98 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */
99 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */
100
101 /* Bit definitions */
102 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
103 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
104
105 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
106 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
107
108 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
109 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
110
111 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
112 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
113
114 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
115 #define GCR_DEN BIT(16) /* Dither ENable */
116 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
117 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
118 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
119 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
120
121 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
122 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
123 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
124 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */
125 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
126 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
127 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
128 #define GC1R_BCP BIT(22) /* Background Colour Programmable */
129 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
130 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
131 #define GC1R_TP BIT(25) /* Timing Programmable */
132 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
133 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
134 #define GC1R_DWP BIT(28) /* Dither Width Programmable */
135 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */
136 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
137
138 #define GC2R_EDCA BIT(0) /* External Display Control Ability */
139 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
140 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
141 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
142 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
143 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
144
145 #define SRCR_IMR BIT(0) /* IMmediate Reload */
146 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
147
148 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */
149 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
150 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
151 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
152 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
153
154 #define IER_LIE BIT(0) /* Line Interrupt Enable */
155 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
156 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
157 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
158
159 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */
160
161 #define ISR_LIF BIT(0) /* Line Interrupt Flag */
162 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
163 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
164 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
165
166 #define LXCR_LEN BIT(0) /* Layer ENable */
167 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */
168 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
169
170 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
171 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
172
173 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
174 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
175
176 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
177
178 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
179
180 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
181 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
182
183 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
184 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
185
186 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
187
188 #define CLUT_SIZE 256
189
190 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
191 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
192 #define BF1_CA 0x400 /* Constant Alpha */
193 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
194 #define BF2_1CA 0x005 /* 1 - Constant Alpha */
195
196 #define NB_PF 8 /* Max nb of HW pixel format */
197
198 enum ltdc_pix_fmt {
199 PF_NONE,
200 /* RGB formats */
201 PF_ARGB8888, /* ARGB [32 bits] */
202 PF_RGBA8888, /* RGBA [32 bits] */
203 PF_RGB888, /* RGB [24 bits] */
204 PF_RGB565, /* RGB [16 bits] */
205 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
206 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
207 /* Indexed formats */
208 PF_L8, /* Indexed 8 bits [8 bits] */
209 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
210 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
211 };
212
213 /* The index gives the encoding of the pixel format for an HW version */
214 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
215 PF_ARGB8888, /* 0x00 */
216 PF_RGB888, /* 0x01 */
217 PF_RGB565, /* 0x02 */
218 PF_ARGB1555, /* 0x03 */
219 PF_ARGB4444, /* 0x04 */
220 PF_L8, /* 0x05 */
221 PF_AL44, /* 0x06 */
222 PF_AL88 /* 0x07 */
223 };
224
225 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
226 PF_ARGB8888, /* 0x00 */
227 PF_RGB888, /* 0x01 */
228 PF_RGB565, /* 0x02 */
229 PF_RGBA8888, /* 0x03 */
230 PF_AL44, /* 0x04 */
231 PF_L8, /* 0x05 */
232 PF_ARGB1555, /* 0x06 */
233 PF_ARGB4444 /* 0x07 */
234 };
235
236 static const u64 ltdc_format_modifiers[] = {
237 DRM_FORMAT_MOD_LINEAR,
238 DRM_FORMAT_MOD_INVALID
239 };
240
reg_read(void __iomem * base,u32 reg)241 static inline u32 reg_read(void __iomem *base, u32 reg)
242 {
243 return readl_relaxed(base + reg);
244 }
245
reg_write(void __iomem * base,u32 reg,u32 val)246 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
247 {
248 writel_relaxed(val, base + reg);
249 }
250
reg_set(void __iomem * base,u32 reg,u32 mask)251 static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
252 {
253 reg_write(base, reg, reg_read(base, reg) | mask);
254 }
255
reg_clear(void __iomem * base,u32 reg,u32 mask)256 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
257 {
258 reg_write(base, reg, reg_read(base, reg) & ~mask);
259 }
260
reg_update_bits(void __iomem * base,u32 reg,u32 mask,u32 val)261 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
262 u32 val)
263 {
264 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
265 }
266
crtc_to_ltdc(struct drm_crtc * crtc)267 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
268 {
269 return (struct ltdc_device *)crtc->dev->dev_private;
270 }
271
plane_to_ltdc(struct drm_plane * plane)272 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
273 {
274 return (struct ltdc_device *)plane->dev->dev_private;
275 }
276
encoder_to_ltdc(struct drm_encoder * enc)277 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
278 {
279 return (struct ltdc_device *)enc->dev->dev_private;
280 }
281
to_ltdc_pixelformat(u32 drm_fmt)282 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
283 {
284 enum ltdc_pix_fmt pf;
285
286 switch (drm_fmt) {
287 case DRM_FORMAT_ARGB8888:
288 case DRM_FORMAT_XRGB8888:
289 pf = PF_ARGB8888;
290 break;
291 case DRM_FORMAT_RGBA8888:
292 case DRM_FORMAT_RGBX8888:
293 pf = PF_RGBA8888;
294 break;
295 case DRM_FORMAT_RGB888:
296 pf = PF_RGB888;
297 break;
298 case DRM_FORMAT_RGB565:
299 pf = PF_RGB565;
300 break;
301 case DRM_FORMAT_ARGB1555:
302 case DRM_FORMAT_XRGB1555:
303 pf = PF_ARGB1555;
304 break;
305 case DRM_FORMAT_ARGB4444:
306 case DRM_FORMAT_XRGB4444:
307 pf = PF_ARGB4444;
308 break;
309 case DRM_FORMAT_C8:
310 pf = PF_L8;
311 break;
312 default:
313 pf = PF_NONE;
314 break;
315 /* Note: There are no DRM_FORMAT for AL44 and AL88 */
316 }
317
318 return pf;
319 }
320
to_drm_pixelformat(enum ltdc_pix_fmt pf)321 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
322 {
323 switch (pf) {
324 case PF_ARGB8888:
325 return DRM_FORMAT_ARGB8888;
326 case PF_RGBA8888:
327 return DRM_FORMAT_RGBA8888;
328 case PF_RGB888:
329 return DRM_FORMAT_RGB888;
330 case PF_RGB565:
331 return DRM_FORMAT_RGB565;
332 case PF_ARGB1555:
333 return DRM_FORMAT_ARGB1555;
334 case PF_ARGB4444:
335 return DRM_FORMAT_ARGB4444;
336 case PF_L8:
337 return DRM_FORMAT_C8;
338 case PF_AL44: /* No DRM support */
339 case PF_AL88: /* No DRM support */
340 case PF_NONE:
341 default:
342 return 0;
343 }
344 }
345
get_pixelformat_without_alpha(u32 drm)346 static inline u32 get_pixelformat_without_alpha(u32 drm)
347 {
348 switch (drm) {
349 case DRM_FORMAT_ARGB4444:
350 return DRM_FORMAT_XRGB4444;
351 case DRM_FORMAT_RGBA4444:
352 return DRM_FORMAT_RGBX4444;
353 case DRM_FORMAT_ARGB1555:
354 return DRM_FORMAT_XRGB1555;
355 case DRM_FORMAT_RGBA5551:
356 return DRM_FORMAT_RGBX5551;
357 case DRM_FORMAT_ARGB8888:
358 return DRM_FORMAT_XRGB8888;
359 case DRM_FORMAT_RGBA8888:
360 return DRM_FORMAT_RGBX8888;
361 default:
362 return 0;
363 }
364 }
365
ltdc_irq_thread(int irq,void * arg)366 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
367 {
368 struct drm_device *ddev = arg;
369 struct ltdc_device *ldev = ddev->dev_private;
370 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
371
372 /* Line IRQ : trigger the vblank event */
373 if (ldev->irq_status & ISR_LIF)
374 drm_crtc_handle_vblank(crtc);
375
376 /* Save FIFO Underrun & Transfer Error status */
377 mutex_lock(&ldev->err_lock);
378 if (ldev->irq_status & ISR_FUIF)
379 ldev->error_status |= ISR_FUIF;
380 if (ldev->irq_status & ISR_TERRIF)
381 ldev->error_status |= ISR_TERRIF;
382 mutex_unlock(&ldev->err_lock);
383
384 return IRQ_HANDLED;
385 }
386
ltdc_irq(int irq,void * arg)387 static irqreturn_t ltdc_irq(int irq, void *arg)
388 {
389 struct drm_device *ddev = arg;
390 struct ltdc_device *ldev = ddev->dev_private;
391
392 /* Read & Clear the interrupt status */
393 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
394 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
395
396 return IRQ_WAKE_THREAD;
397 }
398
399 /*
400 * DRM_CRTC
401 */
402
ltdc_crtc_update_clut(struct drm_crtc * crtc)403 static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
404 {
405 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
406 struct drm_color_lut *lut;
407 u32 val;
408 int i;
409
410 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
411 return;
412
413 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
414
415 for (i = 0; i < CLUT_SIZE; i++, lut++) {
416 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
417 (lut->blue >> 8) | (i << 24);
418 reg_write(ldev->regs, LTDC_L1CLUTWR, val);
419 }
420 }
421
ltdc_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)422 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
423 struct drm_crtc_state *old_state)
424 {
425 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
426 struct drm_device *ddev = crtc->dev;
427
428 DRM_DEBUG_DRIVER("\n");
429
430 pm_runtime_get_sync(ddev->dev);
431
432 /* Sets the background color value */
433 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
434
435 /* Enable IRQ */
436 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
437
438 /* Commit shadow registers = update planes at next vblank */
439 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
440
441 drm_crtc_vblank_on(crtc);
442 }
443
ltdc_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)444 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
445 struct drm_crtc_state *old_state)
446 {
447 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
448 struct drm_device *ddev = crtc->dev;
449
450 DRM_DEBUG_DRIVER("\n");
451
452 drm_crtc_vblank_off(crtc);
453
454 /* disable IRQ */
455 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
456
457 /* immediately commit disable of layers before switching off LTDC */
458 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
459
460 pm_runtime_put_sync(ddev->dev);
461 }
462
463 #define CLK_TOLERANCE_HZ 50
464
465 static enum drm_mode_status
ltdc_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)466 ltdc_crtc_mode_valid(struct drm_crtc *crtc,
467 const struct drm_display_mode *mode)
468 {
469 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
470 int target = mode->clock * 1000;
471 int target_min = target - CLK_TOLERANCE_HZ;
472 int target_max = target + CLK_TOLERANCE_HZ;
473 int result;
474
475 result = clk_round_rate(ldev->pixel_clk, target);
476
477 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
478
479 /* Filter modes according to the max frequency supported by the pads */
480 if (result > ldev->caps.pad_max_freq_hz)
481 return MODE_CLOCK_HIGH;
482
483 /*
484 * Accept all "preferred" modes:
485 * - this is important for panels because panel clock tolerances are
486 * bigger than hdmi ones and there is no reason to not accept them
487 * (the fps may vary a little but it is not a problem).
488 * - the hdmi preferred mode will be accepted too, but userland will
489 * be able to use others hdmi "valid" modes if necessary.
490 */
491 if (mode->type & DRM_MODE_TYPE_PREFERRED)
492 return MODE_OK;
493
494 /*
495 * Filter modes according to the clock value, particularly useful for
496 * hdmi modes that require precise pixel clocks.
497 */
498 if (result < target_min || result > target_max)
499 return MODE_CLOCK_RANGE;
500
501 return MODE_OK;
502 }
503
ltdc_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)504 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
505 const struct drm_display_mode *mode,
506 struct drm_display_mode *adjusted_mode)
507 {
508 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
509 int rate = mode->clock * 1000;
510
511 if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
512 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
513 return false;
514 }
515
516 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
517
518 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n",
519 mode->clock, adjusted_mode->clock);
520
521 return true;
522 }
523
ltdc_crtc_mode_set_nofb(struct drm_crtc * crtc)524 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
525 {
526 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
527 struct drm_device *ddev = crtc->dev;
528 struct drm_connector_list_iter iter;
529 struct drm_connector *connector = NULL;
530 struct drm_encoder *encoder = NULL, *en_iter;
531 struct drm_bridge *bridge = NULL, *br_iter;
532 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
533 struct videomode vm;
534 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
535 u32 total_width, total_height;
536 u32 bus_flags = 0;
537 u32 val;
538 int ret;
539
540 /* get encoder from crtc */
541 drm_for_each_encoder(en_iter, ddev)
542 if (en_iter->crtc == crtc) {
543 encoder = en_iter;
544 break;
545 }
546
547 if (encoder) {
548 /* get bridge from encoder */
549 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node)
550 if (br_iter->encoder == encoder) {
551 bridge = br_iter;
552 break;
553 }
554
555 /* Get the connector from encoder */
556 drm_connector_list_iter_begin(ddev, &iter);
557 drm_for_each_connector_iter(connector, &iter)
558 if (connector->encoder == encoder)
559 break;
560 drm_connector_list_iter_end(&iter);
561 }
562
563 if (bridge && bridge->timings)
564 bus_flags = bridge->timings->input_bus_flags;
565 else if (connector)
566 bus_flags = connector->display_info.bus_flags;
567
568 if (!pm_runtime_active(ddev->dev)) {
569 ret = pm_runtime_get_sync(ddev->dev);
570 if (ret) {
571 DRM_ERROR("Failed to set mode, cannot get sync\n");
572 return;
573 }
574 }
575
576 drm_display_mode_to_videomode(mode, &vm);
577
578 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
579 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
580 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
581 vm.hfront_porch, vm.hback_porch, vm.hsync_len,
582 vm.vfront_porch, vm.vback_porch, vm.vsync_len);
583
584 /* Convert video timings to ltdc timings */
585 hsync = vm.hsync_len - 1;
586 vsync = vm.vsync_len - 1;
587 accum_hbp = hsync + vm.hback_porch;
588 accum_vbp = vsync + vm.vback_porch;
589 accum_act_w = accum_hbp + vm.hactive;
590 accum_act_h = accum_vbp + vm.vactive;
591 total_width = accum_act_w + vm.hfront_porch;
592 total_height = accum_act_h + vm.vfront_porch;
593
594 /* Configures the HS, VS, DE and PC polarities. Default Active Low */
595 val = 0;
596
597 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
598 val |= GCR_HSPOL;
599
600 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
601 val |= GCR_VSPOL;
602
603 if (bus_flags & DRM_BUS_FLAG_DE_LOW)
604 val |= GCR_DEPOL;
605
606 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
607 val |= GCR_PCPOL;
608
609 reg_update_bits(ldev->regs, LTDC_GCR,
610 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
611
612 /* Set Synchronization size */
613 val = (hsync << 16) | vsync;
614 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
615
616 /* Set Accumulated Back porch */
617 val = (accum_hbp << 16) | accum_vbp;
618 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
619
620 /* Set Accumulated Active Width */
621 val = (accum_act_w << 16) | accum_act_h;
622 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
623
624 /* Set total width & height */
625 val = (total_width << 16) | total_height;
626 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
627
628 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
629 }
630
ltdc_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * old_crtc_state)631 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
632 struct drm_crtc_state *old_crtc_state)
633 {
634 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
635 struct drm_device *ddev = crtc->dev;
636 struct drm_pending_vblank_event *event = crtc->state->event;
637
638 DRM_DEBUG_ATOMIC("\n");
639
640 ltdc_crtc_update_clut(crtc);
641
642 /* Commit shadow registers = update planes at next vblank */
643 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
644
645 if (event) {
646 crtc->state->event = NULL;
647
648 spin_lock_irq(&ddev->event_lock);
649 if (drm_crtc_vblank_get(crtc) == 0)
650 drm_crtc_arm_vblank_event(crtc, event);
651 else
652 drm_crtc_send_vblank_event(crtc, event);
653 spin_unlock_irq(&ddev->event_lock);
654 }
655 }
656
ltdc_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)657 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
658 bool in_vblank_irq,
659 int *vpos, int *hpos,
660 ktime_t *stime, ktime_t *etime,
661 const struct drm_display_mode *mode)
662 {
663 struct drm_device *ddev = crtc->dev;
664 struct ltdc_device *ldev = ddev->dev_private;
665 int line, vactive_start, vactive_end, vtotal;
666
667 if (stime)
668 *stime = ktime_get();
669
670 /* The active area starts after vsync + front porch and ends
671 * at vsync + front porc + display size.
672 * The total height also include back porch.
673 * We have 3 possible cases to handle:
674 * - line < vactive_start: vpos = line - vactive_start and will be
675 * negative
676 * - vactive_start < line < vactive_end: vpos = line - vactive_start
677 * and will be positive
678 * - line > vactive_end: vpos = line - vtotal - vactive_start
679 * and will negative
680 *
681 * Computation for the two first cases are identical so we can
682 * simplify the code and only test if line > vactive_end
683 */
684 if (pm_runtime_active(ddev->dev)) {
685 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS;
686 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP;
687 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH;
688 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH;
689
690 if (line > vactive_end)
691 *vpos = line - vtotal - vactive_start;
692 else
693 *vpos = line - vactive_start;
694 } else {
695 *vpos = 0;
696 }
697
698 *hpos = 0;
699
700 if (etime)
701 *etime = ktime_get();
702
703 return true;
704 }
705
706 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
707 .mode_valid = ltdc_crtc_mode_valid,
708 .mode_fixup = ltdc_crtc_mode_fixup,
709 .mode_set_nofb = ltdc_crtc_mode_set_nofb,
710 .atomic_flush = ltdc_crtc_atomic_flush,
711 .atomic_enable = ltdc_crtc_atomic_enable,
712 .atomic_disable = ltdc_crtc_atomic_disable,
713 .get_scanout_position = ltdc_crtc_get_scanout_position,
714 };
715
ltdc_crtc_enable_vblank(struct drm_crtc * crtc)716 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
717 {
718 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
719 struct drm_crtc_state *state = crtc->state;
720
721 DRM_DEBUG_DRIVER("\n");
722
723 if (state->enable)
724 reg_set(ldev->regs, LTDC_IER, IER_LIE);
725 else
726 return -EPERM;
727
728 return 0;
729 }
730
ltdc_crtc_disable_vblank(struct drm_crtc * crtc)731 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
732 {
733 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
734
735 DRM_DEBUG_DRIVER("\n");
736 reg_clear(ldev->regs, LTDC_IER, IER_LIE);
737 }
738
739 static const struct drm_crtc_funcs ltdc_crtc_funcs = {
740 .destroy = drm_crtc_cleanup,
741 .set_config = drm_atomic_helper_set_config,
742 .page_flip = drm_atomic_helper_page_flip,
743 .reset = drm_atomic_helper_crtc_reset,
744 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
745 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
746 .enable_vblank = ltdc_crtc_enable_vblank,
747 .disable_vblank = ltdc_crtc_disable_vblank,
748 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
749 .gamma_set = drm_atomic_helper_legacy_gamma_set,
750 };
751
752 /*
753 * DRM_PLANE
754 */
755
ltdc_plane_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)756 static int ltdc_plane_atomic_check(struct drm_plane *plane,
757 struct drm_plane_state *state)
758 {
759 struct drm_framebuffer *fb = state->fb;
760 u32 src_w, src_h;
761
762 DRM_DEBUG_DRIVER("\n");
763
764 if (!fb)
765 return 0;
766
767 /* convert src_ from 16:16 format */
768 src_w = state->src_w >> 16;
769 src_h = state->src_h >> 16;
770
771 /* Reject scaling */
772 if (src_w != state->crtc_w || src_h != state->crtc_h) {
773 DRM_ERROR("Scaling is not supported");
774 return -EINVAL;
775 }
776
777 return 0;
778 }
779
ltdc_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * oldstate)780 static void ltdc_plane_atomic_update(struct drm_plane *plane,
781 struct drm_plane_state *oldstate)
782 {
783 struct ltdc_device *ldev = plane_to_ltdc(plane);
784 struct drm_plane_state *state = plane->state;
785 struct drm_framebuffer *fb = state->fb;
786 u32 lofs = plane->index * LAY_OFS;
787 u32 x0 = state->crtc_x;
788 u32 x1 = state->crtc_x + state->crtc_w - 1;
789 u32 y0 = state->crtc_y;
790 u32 y1 = state->crtc_y + state->crtc_h - 1;
791 u32 src_x, src_y, src_w, src_h;
792 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
793 enum ltdc_pix_fmt pf;
794
795 if (!state->crtc || !fb) {
796 DRM_DEBUG_DRIVER("fb or crtc NULL");
797 return;
798 }
799
800 /* convert src_ from 16:16 format */
801 src_x = state->src_x >> 16;
802 src_y = state->src_y >> 16;
803 src_w = state->src_w >> 16;
804 src_h = state->src_h >> 16;
805
806 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
807 plane->base.id, fb->base.id,
808 src_w, src_h, src_x, src_y,
809 state->crtc_w, state->crtc_h,
810 state->crtc_x, state->crtc_y);
811
812 bpcr = reg_read(ldev->regs, LTDC_BPCR);
813 ahbp = (bpcr & BPCR_AHBP) >> 16;
814 avbp = bpcr & BPCR_AVBP;
815
816 /* Configures the horizontal start and stop position */
817 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
818 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
819 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
820
821 /* Configures the vertical start and stop position */
822 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
823 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
824 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
825
826 /* Specifies the pixel format */
827 pf = to_ltdc_pixelformat(fb->format->format);
828 for (val = 0; val < NB_PF; val++)
829 if (ldev->caps.pix_fmt_hw[val] == pf)
830 break;
831
832 if (val == NB_PF) {
833 DRM_ERROR("Pixel format %.4s not supported\n",
834 (char *)&fb->format->format);
835 val = 0; /* set by default ARGB 32 bits */
836 }
837 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
838
839 /* Configures the color frame buffer pitch in bytes & line length */
840 pitch_in_bytes = fb->pitches[0];
841 line_length = fb->format->cpp[0] *
842 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
843 val = ((pitch_in_bytes << 16) | line_length);
844 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
845 LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
846
847 /* Specifies the constant alpha value */
848 val = CONSTA_MAX;
849 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
850
851 /* Specifies the blending factors */
852 val = BF1_PAXCA | BF2_1PAXCA;
853 if (!fb->format->has_alpha)
854 val = BF1_CA | BF2_1CA;
855
856 /* Manage hw-specific capabilities */
857 if (ldev->caps.non_alpha_only_l1 &&
858 plane->type != DRM_PLANE_TYPE_PRIMARY)
859 val = BF1_PAXCA | BF2_1PAXCA;
860
861 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
862 LXBFCR_BF2 | LXBFCR_BF1, val);
863
864 /* Configures the frame buffer line number */
865 val = y1 - y0 + 1;
866 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);
867
868 /* Sets the FB address */
869 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
870
871 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
872 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
873
874 /* Enable layer and CLUT if needed */
875 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
876 val |= LXCR_LEN;
877 reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
878 LXCR_LEN | LXCR_CLUTEN, val);
879
880 ldev->plane_fpsi[plane->index].counter++;
881
882 mutex_lock(&ldev->err_lock);
883 if (ldev->error_status & ISR_FUIF) {
884 DRM_WARN("ltdc fifo underrun: please verify display mode\n");
885 ldev->error_status &= ~ISR_FUIF;
886 }
887 if (ldev->error_status & ISR_TERRIF) {
888 DRM_WARN("ltdc transfer error\n");
889 ldev->error_status &= ~ISR_TERRIF;
890 }
891 mutex_unlock(&ldev->err_lock);
892 }
893
ltdc_plane_atomic_disable(struct drm_plane * plane,struct drm_plane_state * oldstate)894 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
895 struct drm_plane_state *oldstate)
896 {
897 struct ltdc_device *ldev = plane_to_ltdc(plane);
898 u32 lofs = plane->index * LAY_OFS;
899
900 /* disable layer */
901 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
902
903 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
904 oldstate->crtc->base.id, plane->base.id);
905 }
906
ltdc_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)907 static void ltdc_plane_atomic_print_state(struct drm_printer *p,
908 const struct drm_plane_state *state)
909 {
910 struct drm_plane *plane = state->plane;
911 struct ltdc_device *ldev = plane_to_ltdc(plane);
912 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
913 int ms_since_last;
914 ktime_t now;
915
916 now = ktime_get();
917 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp));
918
919 drm_printf(p, "\tuser_updates=%dfps\n",
920 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last));
921
922 fpsi->last_timestamp = now;
923 fpsi->counter = 0;
924 }
925
ltdc_plane_format_mod_supported(struct drm_plane * plane,u32 format,u64 modifier)926 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane,
927 u32 format,
928 u64 modifier)
929 {
930 if (modifier == DRM_FORMAT_MOD_LINEAR)
931 return true;
932
933 return false;
934 }
935
936 static const struct drm_plane_funcs ltdc_plane_funcs = {
937 .update_plane = drm_atomic_helper_update_plane,
938 .disable_plane = drm_atomic_helper_disable_plane,
939 .destroy = drm_plane_cleanup,
940 .reset = drm_atomic_helper_plane_reset,
941 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
942 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
943 .atomic_print_state = ltdc_plane_atomic_print_state,
944 .format_mod_supported = ltdc_plane_format_mod_supported,
945 };
946
947 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
948 .prepare_fb = drm_gem_fb_prepare_fb,
949 .atomic_check = ltdc_plane_atomic_check,
950 .atomic_update = ltdc_plane_atomic_update,
951 .atomic_disable = ltdc_plane_atomic_disable,
952 };
953
ltdc_plane_create(struct drm_device * ddev,enum drm_plane_type type)954 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
955 enum drm_plane_type type)
956 {
957 unsigned long possible_crtcs = CRTC_MASK;
958 struct ltdc_device *ldev = ddev->dev_private;
959 struct device *dev = ddev->dev;
960 struct drm_plane *plane;
961 unsigned int i, nb_fmt = 0;
962 u32 formats[NB_PF * 2];
963 u32 drm_fmt, drm_fmt_no_alpha;
964 const u64 *modifiers = ltdc_format_modifiers;
965 int ret;
966
967 /* Get supported pixel formats */
968 for (i = 0; i < NB_PF; i++) {
969 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
970 if (!drm_fmt)
971 continue;
972 formats[nb_fmt++] = drm_fmt;
973
974 /* Add the no-alpha related format if any & supported */
975 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt);
976 if (!drm_fmt_no_alpha)
977 continue;
978
979 /* Manage hw-specific capabilities */
980 if (ldev->caps.non_alpha_only_l1 &&
981 type != DRM_PLANE_TYPE_PRIMARY)
982 continue;
983
984 formats[nb_fmt++] = drm_fmt_no_alpha;
985 }
986
987 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
988 if (!plane)
989 return NULL;
990
991 ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
992 <dc_plane_funcs, formats, nb_fmt,
993 modifiers, type, NULL);
994 if (ret < 0)
995 return NULL;
996
997 drm_plane_helper_add(plane, <dc_plane_helper_funcs);
998
999 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
1000
1001 return plane;
1002 }
1003
ltdc_plane_destroy_all(struct drm_device * ddev)1004 static void ltdc_plane_destroy_all(struct drm_device *ddev)
1005 {
1006 struct drm_plane *plane, *plane_temp;
1007
1008 list_for_each_entry_safe(plane, plane_temp,
1009 &ddev->mode_config.plane_list, head)
1010 drm_plane_cleanup(plane);
1011 }
1012
ltdc_crtc_init(struct drm_device * ddev,struct drm_crtc * crtc)1013 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
1014 {
1015 struct ltdc_device *ldev = ddev->dev_private;
1016 struct drm_plane *primary, *overlay;
1017 unsigned int i;
1018 int ret;
1019
1020 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
1021 if (!primary) {
1022 DRM_ERROR("Can not create primary plane\n");
1023 return -EINVAL;
1024 }
1025
1026 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1027 <dc_crtc_funcs, NULL);
1028 if (ret) {
1029 DRM_ERROR("Can not initialize CRTC\n");
1030 goto cleanup;
1031 }
1032
1033 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs);
1034
1035 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
1036 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
1037
1038 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
1039
1040 /* Add planes. Note : the first layer is used by primary plane */
1041 for (i = 1; i < ldev->caps.nb_layers; i++) {
1042 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
1043 if (!overlay) {
1044 ret = -ENOMEM;
1045 DRM_ERROR("Can not create overlay plane %d\n", i);
1046 goto cleanup;
1047 }
1048 }
1049
1050 return 0;
1051
1052 cleanup:
1053 ltdc_plane_destroy_all(ddev);
1054 return ret;
1055 }
1056
1057 /*
1058 * DRM_ENCODER
1059 */
1060
1061 static const struct drm_encoder_funcs ltdc_encoder_funcs = {
1062 .destroy = drm_encoder_cleanup,
1063 };
1064
ltdc_encoder_disable(struct drm_encoder * encoder)1065 static void ltdc_encoder_disable(struct drm_encoder *encoder)
1066 {
1067 struct drm_device *ddev = encoder->dev;
1068 struct ltdc_device *ldev = ddev->dev_private;
1069
1070 DRM_DEBUG_DRIVER("\n");
1071
1072 /* Disable LTDC */
1073 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
1074
1075 /* Set to sleep state the pinctrl whatever type of encoder */
1076 pinctrl_pm_select_sleep_state(ddev->dev);
1077 }
1078
ltdc_encoder_enable(struct drm_encoder * encoder)1079 static void ltdc_encoder_enable(struct drm_encoder *encoder)
1080 {
1081 struct drm_device *ddev = encoder->dev;
1082 struct ltdc_device *ldev = ddev->dev_private;
1083
1084 DRM_DEBUG_DRIVER("\n");
1085
1086 /* Enable LTDC */
1087 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
1088 }
1089
ltdc_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1090 static void ltdc_encoder_mode_set(struct drm_encoder *encoder,
1091 struct drm_display_mode *mode,
1092 struct drm_display_mode *adjusted_mode)
1093 {
1094 struct drm_device *ddev = encoder->dev;
1095
1096 DRM_DEBUG_DRIVER("\n");
1097
1098 /*
1099 * Set to default state the pinctrl only with DPI type.
1100 * Others types like DSI, don't need pinctrl due to
1101 * internal bridge (the signals do not come out of the chipset).
1102 */
1103 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI)
1104 pinctrl_pm_select_default_state(ddev->dev);
1105 }
1106
1107 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = {
1108 .disable = ltdc_encoder_disable,
1109 .enable = ltdc_encoder_enable,
1110 .mode_set = ltdc_encoder_mode_set,
1111 };
1112
ltdc_encoder_init(struct drm_device * ddev,struct drm_bridge * bridge)1113 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
1114 {
1115 struct drm_encoder *encoder;
1116 int ret;
1117
1118 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
1119 if (!encoder)
1120 return -ENOMEM;
1121
1122 encoder->possible_crtcs = CRTC_MASK;
1123 encoder->possible_clones = 0; /* No cloning support */
1124
1125 drm_encoder_init(ddev, encoder, <dc_encoder_funcs,
1126 DRM_MODE_ENCODER_DPI, NULL);
1127
1128 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs);
1129
1130 ret = drm_bridge_attach(encoder, bridge, NULL, 0);
1131 if (ret) {
1132 drm_encoder_cleanup(encoder);
1133 return -EINVAL;
1134 }
1135
1136 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
1137
1138 return 0;
1139 }
1140
ltdc_get_caps(struct drm_device * ddev)1141 static int ltdc_get_caps(struct drm_device *ddev)
1142 {
1143 struct ltdc_device *ldev = ddev->dev_private;
1144 u32 bus_width_log2, lcr, gc2r;
1145
1146 /*
1147 * at least 1 layer must be managed & the number of layers
1148 * must not exceed LTDC_MAX_LAYER
1149 */
1150 lcr = reg_read(ldev->regs, LTDC_LCR);
1151
1152 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
1153
1154 /* set data bus width */
1155 gc2r = reg_read(ldev->regs, LTDC_GC2R);
1156 bus_width_log2 = (gc2r & GC2R_BW) >> 4;
1157 ldev->caps.bus_width = 8 << bus_width_log2;
1158 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
1159
1160 switch (ldev->caps.hw_version) {
1161 case HWVER_10200:
1162 case HWVER_10300:
1163 ldev->caps.reg_ofs = REG_OFS_NONE;
1164 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
1165 /*
1166 * Hw older versions support non-alpha color formats derived
1167 * from native alpha color formats only on the primary layer.
1168 * For instance, RG16 native format without alpha works fine
1169 * on 2nd layer but XR24 (derived color format from AR24)
1170 * does not work on 2nd layer.
1171 */
1172 ldev->caps.non_alpha_only_l1 = true;
1173 ldev->caps.pad_max_freq_hz = 90000000;
1174 if (ldev->caps.hw_version == HWVER_10200)
1175 ldev->caps.pad_max_freq_hz = 65000000;
1176 ldev->caps.nb_irq = 2;
1177 break;
1178 case HWVER_20101:
1179 ldev->caps.reg_ofs = REG_OFS_4;
1180 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1181 ldev->caps.non_alpha_only_l1 = false;
1182 ldev->caps.pad_max_freq_hz = 150000000;
1183 ldev->caps.nb_irq = 4;
1184 break;
1185 default:
1186 return -ENODEV;
1187 }
1188
1189 return 0;
1190 }
1191
ltdc_suspend(struct drm_device * ddev)1192 void ltdc_suspend(struct drm_device *ddev)
1193 {
1194 struct ltdc_device *ldev = ddev->dev_private;
1195
1196 DRM_DEBUG_DRIVER("\n");
1197 clk_disable_unprepare(ldev->pixel_clk);
1198 }
1199
ltdc_resume(struct drm_device * ddev)1200 int ltdc_resume(struct drm_device *ddev)
1201 {
1202 struct ltdc_device *ldev = ddev->dev_private;
1203 int ret;
1204
1205 DRM_DEBUG_DRIVER("\n");
1206
1207 ret = clk_prepare_enable(ldev->pixel_clk);
1208 if (ret) {
1209 DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
1210 return ret;
1211 }
1212
1213 return 0;
1214 }
1215
ltdc_load(struct drm_device * ddev)1216 int ltdc_load(struct drm_device *ddev)
1217 {
1218 struct platform_device *pdev = to_platform_device(ddev->dev);
1219 struct ltdc_device *ldev = ddev->dev_private;
1220 struct device *dev = ddev->dev;
1221 struct device_node *np = dev->of_node;
1222 struct drm_bridge *bridge;
1223 struct drm_panel *panel;
1224 struct drm_crtc *crtc;
1225 struct reset_control *rstc;
1226 struct resource *res;
1227 int irq, i, nb_endpoints;
1228 int ret = -ENODEV;
1229
1230 DRM_DEBUG_DRIVER("\n");
1231
1232 /* Get number of endpoints */
1233 nb_endpoints = of_graph_get_endpoint_count(np);
1234 if (!nb_endpoints)
1235 return -ENODEV;
1236
1237 ldev->pixel_clk = devm_clk_get(dev, "lcd");
1238 if (IS_ERR(ldev->pixel_clk)) {
1239 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
1240 DRM_ERROR("Unable to get lcd clock\n");
1241 return PTR_ERR(ldev->pixel_clk);
1242 }
1243
1244 if (clk_prepare_enable(ldev->pixel_clk)) {
1245 DRM_ERROR("Unable to prepare pixel clock\n");
1246 return -ENODEV;
1247 }
1248
1249 /* Get endpoints if any */
1250 for (i = 0; i < nb_endpoints; i++) {
1251 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
1252
1253 /*
1254 * If at least one endpoint is -ENODEV, continue probing,
1255 * else if at least one endpoint returned an error
1256 * (ie -EPROBE_DEFER) then stop probing.
1257 */
1258 if (ret == -ENODEV)
1259 continue;
1260 else if (ret)
1261 goto err;
1262
1263 if (panel) {
1264 bridge = drm_panel_bridge_add_typed(panel,
1265 DRM_MODE_CONNECTOR_DPI);
1266 if (IS_ERR(bridge)) {
1267 DRM_ERROR("panel-bridge endpoint %d\n", i);
1268 ret = PTR_ERR(bridge);
1269 goto err;
1270 }
1271 }
1272
1273 if (bridge) {
1274 ret = ltdc_encoder_init(ddev, bridge);
1275 if (ret) {
1276 DRM_ERROR("init encoder endpoint %d\n", i);
1277 goto err;
1278 }
1279 }
1280 }
1281
1282 rstc = devm_reset_control_get_exclusive(dev, NULL);
1283
1284 mutex_init(&ldev->err_lock);
1285
1286 if (!IS_ERR(rstc)) {
1287 reset_control_assert(rstc);
1288 usleep_range(10, 20);
1289 reset_control_deassert(rstc);
1290 }
1291
1292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293 ldev->regs = devm_ioremap_resource(dev, res);
1294 if (IS_ERR(ldev->regs)) {
1295 DRM_ERROR("Unable to get ltdc registers\n");
1296 ret = PTR_ERR(ldev->regs);
1297 goto err;
1298 }
1299
1300 /* Disable interrupts */
1301 reg_clear(ldev->regs, LTDC_IER,
1302 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
1303
1304 ret = ltdc_get_caps(ddev);
1305 if (ret) {
1306 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
1307 ldev->caps.hw_version);
1308 goto err;
1309 }
1310
1311 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
1312
1313 for (i = 0; i < ldev->caps.nb_irq; i++) {
1314 irq = platform_get_irq(pdev, i);
1315 if (irq < 0) {
1316 ret = irq;
1317 goto err;
1318 }
1319
1320 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
1321 ltdc_irq_thread, IRQF_ONESHOT,
1322 dev_name(dev), ddev);
1323 if (ret) {
1324 DRM_ERROR("Failed to register LTDC interrupt\n");
1325 goto err;
1326 }
1327
1328 }
1329
1330 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
1331 if (!crtc) {
1332 DRM_ERROR("Failed to allocate crtc\n");
1333 ret = -ENOMEM;
1334 goto err;
1335 }
1336
1337 ddev->mode_config.allow_fb_modifiers = true;
1338
1339 ret = ltdc_crtc_init(ddev, crtc);
1340 if (ret) {
1341 DRM_ERROR("Failed to init crtc\n");
1342 goto err;
1343 }
1344
1345 ret = drm_vblank_init(ddev, NB_CRTC);
1346 if (ret) {
1347 DRM_ERROR("Failed calling drm_vblank_init()\n");
1348 goto err;
1349 }
1350
1351 /* Allow usage of vblank without having to call drm_irq_install */
1352 ddev->irq_enabled = 1;
1353
1354 clk_disable_unprepare(ldev->pixel_clk);
1355
1356 pinctrl_pm_select_sleep_state(ddev->dev);
1357
1358 pm_runtime_enable(ddev->dev);
1359
1360 return 0;
1361 err:
1362 for (i = 0; i < nb_endpoints; i++)
1363 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
1364
1365 clk_disable_unprepare(ldev->pixel_clk);
1366
1367 return ret;
1368 }
1369
ltdc_unload(struct drm_device * ddev)1370 void ltdc_unload(struct drm_device *ddev)
1371 {
1372 struct device *dev = ddev->dev;
1373 int nb_endpoints, i;
1374
1375 DRM_DEBUG_DRIVER("\n");
1376
1377 nb_endpoints = of_graph_get_endpoint_count(dev->of_node);
1378
1379 for (i = 0; i < nb_endpoints; i++)
1380 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
1381
1382 pm_runtime_disable(ddev->dev);
1383 }
1384
1385 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1386 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1387 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
1388 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
1389 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
1390 MODULE_LICENSE("GPL v2");
1391