1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * I2C bus driver for the Cadence I2C controller.
4 *
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/of.h>
16 #include <linux/pm_runtime.h>
17
18 /* Register offsets for the I2C device. */
19 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
20 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */
21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
23 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
24 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
25 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
26 #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */
27 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
28 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
29
30 /* Control Register Bit mask definitions */
31 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */
32 #define CDNS_I2C_CR_ACK_EN BIT(3)
33 #define CDNS_I2C_CR_NEA BIT(2)
34 #define CDNS_I2C_CR_MS BIT(1)
35 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
36 #define CDNS_I2C_CR_RW BIT(0)
37 /* 1 = Auto init FIFO to zeroes */
38 #define CDNS_I2C_CR_CLR_FIFO BIT(6)
39 #define CDNS_I2C_CR_DIVA_SHIFT 14
40 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
41 #define CDNS_I2C_CR_DIVB_SHIFT 8
42 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
43
44 #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \
45 CDNS_I2C_CR_ACK_EN | \
46 CDNS_I2C_CR_MS)
47
48 #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK
49
50 /* Status Register Bit mask definitions */
51 #define CDNS_I2C_SR_BA BIT(8)
52 #define CDNS_I2C_SR_TXDV BIT(6)
53 #define CDNS_I2C_SR_RXDV BIT(5)
54 #define CDNS_I2C_SR_RXRW BIT(3)
55
56 /*
57 * I2C Address Register Bit mask definitions
58 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
59 * bits. A write access to this register always initiates a transfer if the I2C
60 * is in master mode.
61 */
62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
63
64 /*
65 * I2C Interrupt Registers Bit mask definitions
66 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
67 * bit definitions.
68 */
69 #define CDNS_I2C_IXR_ARB_LOST BIT(9)
70 #define CDNS_I2C_IXR_RX_UNF BIT(7)
71 #define CDNS_I2C_IXR_TX_OVF BIT(6)
72 #define CDNS_I2C_IXR_RX_OVF BIT(5)
73 #define CDNS_I2C_IXR_SLV_RDY BIT(4)
74 #define CDNS_I2C_IXR_TO BIT(3)
75 #define CDNS_I2C_IXR_NACK BIT(2)
76 #define CDNS_I2C_IXR_DATA BIT(1)
77 #define CDNS_I2C_IXR_COMP BIT(0)
78
79 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
80 CDNS_I2C_IXR_RX_UNF | \
81 CDNS_I2C_IXR_TX_OVF | \
82 CDNS_I2C_IXR_RX_OVF | \
83 CDNS_I2C_IXR_SLV_RDY | \
84 CDNS_I2C_IXR_TO | \
85 CDNS_I2C_IXR_NACK | \
86 CDNS_I2C_IXR_DATA | \
87 CDNS_I2C_IXR_COMP)
88
89 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
90 CDNS_I2C_IXR_RX_UNF | \
91 CDNS_I2C_IXR_TX_OVF | \
92 CDNS_I2C_IXR_RX_OVF | \
93 CDNS_I2C_IXR_NACK)
94
95 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
96 CDNS_I2C_IXR_RX_UNF | \
97 CDNS_I2C_IXR_TX_OVF | \
98 CDNS_I2C_IXR_RX_OVF | \
99 CDNS_I2C_IXR_NACK | \
100 CDNS_I2C_IXR_DATA | \
101 CDNS_I2C_IXR_COMP)
102
103 #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \
104 CDNS_I2C_IXR_TX_OVF | \
105 CDNS_I2C_IXR_RX_OVF | \
106 CDNS_I2C_IXR_TO | \
107 CDNS_I2C_IXR_NACK | \
108 CDNS_I2C_IXR_DATA | \
109 CDNS_I2C_IXR_COMP)
110
111 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
112 /* timeout for pm runtime autosuspend */
113 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
114
115 #define CDNS_I2C_FIFO_DEPTH 16
116 /* FIFO depth at which the DATA interrupt occurs */
117 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
118 #define CDNS_I2C_MAX_TRANSFER_SIZE 255
119 /* Transfer size in multiples of data interrupt depth */
120 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
121
122 #define DRIVER_NAME "cdns-i2c"
123
124 #define CDNS_I2C_DIVA_MAX 4
125 #define CDNS_I2C_DIVB_MAX 64
126
127 #define CDNS_I2C_TIMEOUT_MAX 0xFF
128
129 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
130
131 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
132 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
133
134 #if IS_ENABLED(CONFIG_I2C_SLAVE)
135 /**
136 * enum cdns_i2c_mode - I2C Controller current operating mode
137 *
138 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode
139 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode
140 */
141 enum cdns_i2c_mode {
142 CDNS_I2C_MODE_SLAVE,
143 CDNS_I2C_MODE_MASTER,
144 };
145
146 /**
147 * enum cdns_i2c_slave_mode - Slave state when I2C is operating in slave mode
148 *
149 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
150 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
151 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
152 */
153 enum cdns_i2c_slave_state {
154 CDNS_I2C_SLAVE_STATE_IDLE,
155 CDNS_I2C_SLAVE_STATE_SEND,
156 CDNS_I2C_SLAVE_STATE_RECV,
157 };
158 #endif
159
160 /**
161 * struct cdns_i2c - I2C device private data structure
162 *
163 * @dev: Pointer to device structure
164 * @membase: Base address of the I2C device
165 * @adap: I2C adapter instance
166 * @p_msg: Message pointer
167 * @err_status: Error status in Interrupt Status Register
168 * @xfer_done: Transfer complete status
169 * @p_send_buf: Pointer to transmit buffer
170 * @p_recv_buf: Pointer to receive buffer
171 * @send_count: Number of bytes still expected to send
172 * @recv_count: Number of bytes still expected to receive
173 * @curr_recv_count: Number of bytes to be received in current transfer
174 * @irq: IRQ number
175 * @input_clk: Input clock to I2C controller
176 * @i2c_clk: Maximum I2C clock speed
177 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
178 * @clk: Pointer to struct clk
179 * @clk_rate_change_nb: Notifier block for clock rate changes
180 * @quirks: flag for broken hold bit usage in r1p10
181 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
182 * @slave: Registered slave instance.
183 * @dev_mode: I2C operating role(master/slave).
184 * @slave_state: I2C Slave state(idle/read/write).
185 */
186 struct cdns_i2c {
187 struct device *dev;
188 void __iomem *membase;
189 struct i2c_adapter adap;
190 struct i2c_msg *p_msg;
191 int err_status;
192 struct completion xfer_done;
193 unsigned char *p_send_buf;
194 unsigned char *p_recv_buf;
195 unsigned int send_count;
196 unsigned int recv_count;
197 unsigned int curr_recv_count;
198 int irq;
199 unsigned long input_clk;
200 unsigned int i2c_clk;
201 unsigned int bus_hold_flag;
202 struct clk *clk;
203 struct notifier_block clk_rate_change_nb;
204 u32 quirks;
205 #if IS_ENABLED(CONFIG_I2C_SLAVE)
206 u16 ctrl_reg_diva_divb;
207 struct i2c_client *slave;
208 enum cdns_i2c_mode dev_mode;
209 enum cdns_i2c_slave_state slave_state;
210 #endif
211 };
212
213 struct cdns_platform_data {
214 u32 quirks;
215 };
216
217 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
218 clk_rate_change_nb)
219
220 /**
221 * cdns_i2c_clear_bus_hold - Clear bus hold bit
222 * @id: Pointer to driver data struct
223 *
224 * Helper to clear the controller's bus hold bit.
225 */
cdns_i2c_clear_bus_hold(struct cdns_i2c * id)226 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
227 {
228 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
229 if (reg & CDNS_I2C_CR_HOLD)
230 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
231 }
232
cdns_is_holdquirk(struct cdns_i2c * id,bool hold_wrkaround)233 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
234 {
235 return (hold_wrkaround &&
236 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
237 }
238
239 #if IS_ENABLED(CONFIG_I2C_SLAVE)
cdns_i2c_set_mode(enum cdns_i2c_mode mode,struct cdns_i2c * id)240 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
241 {
242 /* Disable all interrupts */
243 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
244
245 /* Clear FIFO and transfer size */
246 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
247
248 /* Update device mode and state */
249 id->dev_mode = mode;
250 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
251
252 switch (mode) {
253 case CDNS_I2C_MODE_MASTER:
254 /* Enable i2c master */
255 cdns_i2c_writereg(id->ctrl_reg_diva_divb |
256 CDNS_I2C_CR_MASTER_EN_MASK,
257 CDNS_I2C_CR_OFFSET);
258 /*
259 * This delay is needed to give the IP some time to switch to
260 * the master mode. With lower values(like 110 us) i2cdetect
261 * will not detect any slave and without this delay, the IP will
262 * trigger a timeout interrupt.
263 */
264 usleep_range(115, 125);
265 break;
266 case CDNS_I2C_MODE_SLAVE:
267 /* Enable i2c slave */
268 cdns_i2c_writereg(id->ctrl_reg_diva_divb &
269 CDNS_I2C_CR_SLAVE_EN_MASK,
270 CDNS_I2C_CR_OFFSET);
271
272 /* Setting slave address */
273 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
274 CDNS_I2C_ADDR_OFFSET);
275
276 /* Enable slave send/receive interrupts */
277 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
278 CDNS_I2C_IER_OFFSET);
279 break;
280 }
281 }
282
cdns_i2c_slave_rcv_data(struct cdns_i2c * id)283 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
284 {
285 u8 bytes;
286 unsigned char data;
287
288 /* Prepare backend for data reception */
289 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
290 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
291 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
292 }
293
294 /* Fetch number of bytes to receive */
295 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
296
297 /* Read data and send to backend */
298 while (bytes--) {
299 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
300 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
301 }
302 }
303
cdns_i2c_slave_send_data(struct cdns_i2c * id)304 static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
305 {
306 u8 data;
307
308 /* Prepare backend for data transmission */
309 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
310 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
311 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
312 } else {
313 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
314 }
315
316 /* Send data over bus */
317 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
318 }
319
320 /**
321 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
322 * @ptr: Pointer to I2C device private data
323 *
324 * This function handles the data interrupt and transfer complete interrupt of
325 * the I2C device in slave role.
326 *
327 * Return: IRQ_HANDLED always
328 */
cdns_i2c_slave_isr(void * ptr)329 static irqreturn_t cdns_i2c_slave_isr(void *ptr)
330 {
331 struct cdns_i2c *id = ptr;
332 unsigned int isr_status, i2c_status;
333
334 /* Fetch the interrupt status */
335 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
336 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
337
338 /* Ignore masked interrupts */
339 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
340
341 /* Fetch transfer mode (send/receive) */
342 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
343
344 /* Handle data send/receive */
345 if (i2c_status & CDNS_I2C_SR_RXRW) {
346 /* Send data to master */
347 if (isr_status & CDNS_I2C_IXR_DATA)
348 cdns_i2c_slave_send_data(id);
349
350 if (isr_status & CDNS_I2C_IXR_COMP) {
351 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
352 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
353 }
354 } else {
355 /* Receive data from master */
356 if (isr_status & CDNS_I2C_IXR_DATA)
357 cdns_i2c_slave_rcv_data(id);
358
359 if (isr_status & CDNS_I2C_IXR_COMP) {
360 cdns_i2c_slave_rcv_data(id);
361 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
362 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
363 }
364 }
365
366 /* Master indicated xfer stop or fifo underflow/overflow */
367 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
368 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
369 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
370 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
371 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
372 }
373
374 return IRQ_HANDLED;
375 }
376 #endif
377
378 /**
379 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
380 * @ptr: Pointer to I2C device private data
381 *
382 * This function handles the data interrupt, transfer complete interrupt and
383 * the error interrupts of the I2C device in master role.
384 *
385 * Return: IRQ_HANDLED always
386 */
cdns_i2c_master_isr(void * ptr)387 static irqreturn_t cdns_i2c_master_isr(void *ptr)
388 {
389 unsigned int isr_status, avail_bytes;
390 unsigned int bytes_to_send;
391 bool updatetx;
392 struct cdns_i2c *id = ptr;
393 /* Signal completion only after everything is updated */
394 int done_flag = 0;
395 irqreturn_t status = IRQ_NONE;
396
397 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
398 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
399 id->err_status = 0;
400
401 /* Handling nack and arbitration lost interrupt */
402 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
403 done_flag = 1;
404 status = IRQ_HANDLED;
405 }
406
407 /*
408 * Check if transfer size register needs to be updated again for a
409 * large data receive operation.
410 */
411 updatetx = id->recv_count > id->curr_recv_count;
412
413 /* When receiving, handle data interrupt and completion interrupt */
414 if (id->p_recv_buf &&
415 ((isr_status & CDNS_I2C_IXR_COMP) ||
416 (isr_status & CDNS_I2C_IXR_DATA))) {
417 /* Read data if receive data valid is set */
418 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
419 CDNS_I2C_SR_RXDV) {
420 if (id->recv_count > 0) {
421 *(id->p_recv_buf)++ =
422 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
423 id->recv_count--;
424 id->curr_recv_count--;
425
426 /*
427 * Clear hold bit that was set for FIFO control
428 * if RX data left is less than or equal to
429 * FIFO DEPTH unless repeated start is selected
430 */
431 if (id->recv_count <= CDNS_I2C_FIFO_DEPTH &&
432 !id->bus_hold_flag)
433 cdns_i2c_clear_bus_hold(id);
434
435 } else {
436 dev_err(id->adap.dev.parent,
437 "xfer_size reg rollover. xfer aborted!\n");
438 id->err_status |= CDNS_I2C_IXR_TO;
439 break;
440 }
441
442 if (cdns_is_holdquirk(id, updatetx))
443 break;
444 }
445
446 /*
447 * The controller sends NACK to the slave when transfer size
448 * register reaches zero without considering the HOLD bit.
449 * This workaround is implemented for large data transfers to
450 * maintain transfer size non-zero while performing a large
451 * receive operation.
452 */
453 if (cdns_is_holdquirk(id, updatetx)) {
454 /* wait while fifo is full */
455 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
456 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
457 ;
458
459 /*
460 * Check number of bytes to be received against maximum
461 * transfer size and update register accordingly.
462 */
463 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
464 CDNS_I2C_TRANSFER_SIZE) {
465 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
466 CDNS_I2C_XFER_SIZE_OFFSET);
467 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
468 CDNS_I2C_FIFO_DEPTH;
469 } else {
470 cdns_i2c_writereg(id->recv_count -
471 CDNS_I2C_FIFO_DEPTH,
472 CDNS_I2C_XFER_SIZE_OFFSET);
473 id->curr_recv_count = id->recv_count;
474 }
475 }
476
477 /* Clear hold (if not repeated start) and signal completion */
478 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
479 if (!id->bus_hold_flag)
480 cdns_i2c_clear_bus_hold(id);
481 done_flag = 1;
482 }
483
484 status = IRQ_HANDLED;
485 }
486
487 /* When sending, handle transfer complete interrupt */
488 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
489 /*
490 * If there is more data to be sent, calculate the
491 * space available in FIFO and fill with that many bytes.
492 */
493 if (id->send_count) {
494 avail_bytes = CDNS_I2C_FIFO_DEPTH -
495 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
496 if (id->send_count > avail_bytes)
497 bytes_to_send = avail_bytes;
498 else
499 bytes_to_send = id->send_count;
500
501 while (bytes_to_send--) {
502 cdns_i2c_writereg(
503 (*(id->p_send_buf)++),
504 CDNS_I2C_DATA_OFFSET);
505 id->send_count--;
506 }
507 } else {
508 /*
509 * Signal the completion of transaction and
510 * clear the hold bus bit if there are no
511 * further messages to be processed.
512 */
513 done_flag = 1;
514 }
515 if (!id->send_count && !id->bus_hold_flag)
516 cdns_i2c_clear_bus_hold(id);
517
518 status = IRQ_HANDLED;
519 }
520
521 /* Update the status for errors */
522 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
523 if (id->err_status)
524 status = IRQ_HANDLED;
525
526 if (done_flag)
527 complete(&id->xfer_done);
528
529 return status;
530 }
531
532 /**
533 * cdns_i2c_isr - Interrupt handler for the I2C device
534 * @irq: irq number for the I2C device
535 * @ptr: void pointer to cdns_i2c structure
536 *
537 * This function passes the control to slave/master based on current role of
538 * i2c controller.
539 *
540 * Return: IRQ_HANDLED always
541 */
cdns_i2c_isr(int irq,void * ptr)542 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
543 {
544 #if IS_ENABLED(CONFIG_I2C_SLAVE)
545 struct cdns_i2c *id = ptr;
546
547 if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
548 return cdns_i2c_slave_isr(ptr);
549 #endif
550 return cdns_i2c_master_isr(ptr);
551 }
552
553 /**
554 * cdns_i2c_mrecv - Prepare and start a master receive operation
555 * @id: pointer to the i2c device structure
556 */
cdns_i2c_mrecv(struct cdns_i2c * id)557 static void cdns_i2c_mrecv(struct cdns_i2c *id)
558 {
559 unsigned int ctrl_reg;
560 unsigned int isr_status;
561
562 id->p_recv_buf = id->p_msg->buf;
563 id->recv_count = id->p_msg->len;
564
565 /* Put the controller in master receive mode and clear the FIFO */
566 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
567 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
568
569 /*
570 * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length
571 * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if
572 * PEC is enabled, otherwise 1.
573 */
574 if (id->p_msg->flags & I2C_M_RECV_LEN)
575 id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len;
576
577 id->curr_recv_count = id->recv_count;
578
579 /*
580 * Check for the message size against FIFO depth and set the
581 * 'hold bus' bit if it is greater than FIFO depth.
582 */
583 if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
584 ctrl_reg |= CDNS_I2C_CR_HOLD;
585
586 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
587
588 /* Clear the interrupts in interrupt status register */
589 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
590 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
591
592 /*
593 * The no. of bytes to receive is checked against the limit of
594 * max transfer size. Set transfer size register with no of bytes
595 * receive if it is less than transfer size and transfer size if
596 * it is more. Enable the interrupts.
597 */
598 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
599 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
600 CDNS_I2C_XFER_SIZE_OFFSET);
601 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
602 } else {
603 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
604 }
605
606 /* Set the slave address in address register - triggers operation */
607 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
608 CDNS_I2C_ADDR_OFFSET);
609 /* Clear the bus hold flag if bytes to receive is less than FIFO size */
610 if (!id->bus_hold_flag &&
611 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
612 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
613 cdns_i2c_clear_bus_hold(id);
614 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
615 }
616
617 /**
618 * cdns_i2c_msend - Prepare and start a master send operation
619 * @id: pointer to the i2c device
620 */
cdns_i2c_msend(struct cdns_i2c * id)621 static void cdns_i2c_msend(struct cdns_i2c *id)
622 {
623 unsigned int avail_bytes;
624 unsigned int bytes_to_send;
625 unsigned int ctrl_reg;
626 unsigned int isr_status;
627
628 id->p_recv_buf = NULL;
629 id->p_send_buf = id->p_msg->buf;
630 id->send_count = id->p_msg->len;
631
632 /* Set the controller in Master transmit mode and clear the FIFO. */
633 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
634 ctrl_reg &= ~CDNS_I2C_CR_RW;
635 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
636
637 /*
638 * Check for the message size against FIFO depth and set the
639 * 'hold bus' bit if it is greater than FIFO depth.
640 */
641 if (id->send_count > CDNS_I2C_FIFO_DEPTH)
642 ctrl_reg |= CDNS_I2C_CR_HOLD;
643 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
644
645 /* Clear the interrupts in interrupt status register. */
646 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
647 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
648
649 /*
650 * Calculate the space available in FIFO. Check the message length
651 * against the space available, and fill the FIFO accordingly.
652 * Enable the interrupts.
653 */
654 avail_bytes = CDNS_I2C_FIFO_DEPTH -
655 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
656
657 if (id->send_count > avail_bytes)
658 bytes_to_send = avail_bytes;
659 else
660 bytes_to_send = id->send_count;
661
662 while (bytes_to_send--) {
663 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
664 id->send_count--;
665 }
666
667 /*
668 * Clear the bus hold flag if there is no more data
669 * and if it is the last message.
670 */
671 if (!id->bus_hold_flag && !id->send_count)
672 cdns_i2c_clear_bus_hold(id);
673 /* Set the slave address in address register - triggers operation. */
674 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
675 CDNS_I2C_ADDR_OFFSET);
676
677 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
678 }
679
680 /**
681 * cdns_i2c_master_reset - Reset the interface
682 * @adap: pointer to the i2c adapter driver instance
683 *
684 * This function cleanup the fifos, clear the hold bit and status
685 * and disable the interrupts.
686 */
cdns_i2c_master_reset(struct i2c_adapter * adap)687 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
688 {
689 struct cdns_i2c *id = adap->algo_data;
690 u32 regval;
691
692 /* Disable the interrupts */
693 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
694 /* Clear the hold bit and fifos */
695 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
696 regval &= ~CDNS_I2C_CR_HOLD;
697 regval |= CDNS_I2C_CR_CLR_FIFO;
698 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
699 /* Update the transfercount register to zero */
700 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
701 /* Clear the interrupt status register */
702 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
703 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
704 /* Clear the status register */
705 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
706 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
707 }
708
cdns_i2c_process_msg(struct cdns_i2c * id,struct i2c_msg * msg,struct i2c_adapter * adap)709 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
710 struct i2c_adapter *adap)
711 {
712 unsigned long time_left, msg_timeout;
713 u32 reg;
714
715 id->p_msg = msg;
716 id->err_status = 0;
717 reinit_completion(&id->xfer_done);
718
719 /* Check for the TEN Bit mode on each msg */
720 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
721 if (msg->flags & I2C_M_TEN) {
722 if (reg & CDNS_I2C_CR_NEA)
723 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
724 CDNS_I2C_CR_OFFSET);
725 } else {
726 if (!(reg & CDNS_I2C_CR_NEA))
727 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
728 CDNS_I2C_CR_OFFSET);
729 }
730
731 /* Check for the R/W flag on each msg */
732 if (msg->flags & I2C_M_RD)
733 cdns_i2c_mrecv(id);
734 else
735 cdns_i2c_msend(id);
736
737 /* Minimal time to execute this message */
738 msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk);
739 /* Plus some wiggle room */
740 msg_timeout += msecs_to_jiffies(500);
741
742 if (msg_timeout < adap->timeout)
743 msg_timeout = adap->timeout;
744
745 /* Wait for the signal of completion */
746 time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout);
747 if (time_left == 0) {
748 cdns_i2c_master_reset(adap);
749 dev_err(id->adap.dev.parent,
750 "timeout waiting on completion\n");
751 return -ETIMEDOUT;
752 }
753
754 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
755 CDNS_I2C_IDR_OFFSET);
756
757 /* If it is bus arbitration error, try again */
758 if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
759 return -EAGAIN;
760
761 if (msg->flags & I2C_M_RECV_LEN)
762 msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
763
764 return 0;
765 }
766
767 /**
768 * cdns_i2c_master_xfer - The main i2c transfer function
769 * @adap: pointer to the i2c adapter driver instance
770 * @msgs: pointer to the i2c message structure
771 * @num: the number of messages to transfer
772 *
773 * Initiates the send/recv activity based on the transfer message received.
774 *
775 * Return: number of msgs processed on success, negative error otherwise
776 */
cdns_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)777 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
778 int num)
779 {
780 int ret, count;
781 u32 reg;
782 struct cdns_i2c *id = adap->algo_data;
783 bool hold_quirk;
784 #if IS_ENABLED(CONFIG_I2C_SLAVE)
785 bool change_role = false;
786 #endif
787
788 ret = pm_runtime_resume_and_get(id->dev);
789 if (ret < 0)
790 return ret;
791
792 #if IS_ENABLED(CONFIG_I2C_SLAVE)
793 /* Check i2c operating mode and switch if possible */
794 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
795 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE)
796 return -EAGAIN;
797
798 /* Set mode to master */
799 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
800
801 /* Mark flag to change role once xfer is completed */
802 change_role = true;
803 }
804 #endif
805
806 /* Check if the bus is free */
807 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) {
808 ret = -EAGAIN;
809 goto out;
810 }
811
812 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
813 /*
814 * Set the flag to one when multiple messages are to be
815 * processed with a repeated start.
816 */
817 if (num > 1) {
818 /*
819 * This controller does not give completion interrupt after a
820 * master receive message if HOLD bit is set (repeated start),
821 * resulting in SW timeout. Hence, if a receive message is
822 * followed by any other message, an error is returned
823 * indicating that this sequence is not supported.
824 */
825 for (count = 0; (count < num - 1 && hold_quirk); count++) {
826 if (msgs[count].flags & I2C_M_RD) {
827 dev_warn(adap->dev.parent,
828 "Can't do repeated start after a receive message\n");
829 ret = -EOPNOTSUPP;
830 goto out;
831 }
832 }
833 id->bus_hold_flag = 1;
834 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
835 reg |= CDNS_I2C_CR_HOLD;
836 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
837 } else {
838 id->bus_hold_flag = 0;
839 }
840
841 /* Process the msg one by one */
842 for (count = 0; count < num; count++, msgs++) {
843 if (count == (num - 1))
844 id->bus_hold_flag = 0;
845
846 ret = cdns_i2c_process_msg(id, msgs, adap);
847 if (ret)
848 goto out;
849
850 /* Report the other error interrupts to application */
851 if (id->err_status) {
852 cdns_i2c_master_reset(adap);
853
854 if (id->err_status & CDNS_I2C_IXR_NACK) {
855 ret = -ENXIO;
856 goto out;
857 }
858 ret = -EIO;
859 goto out;
860 }
861 }
862
863 ret = num;
864
865 out:
866
867 #if IS_ENABLED(CONFIG_I2C_SLAVE)
868 /* Switch i2c mode to slave */
869 if (change_role)
870 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
871 #endif
872
873 pm_runtime_mark_last_busy(id->dev);
874 pm_runtime_put_autosuspend(id->dev);
875 return ret;
876 }
877
878 /**
879 * cdns_i2c_func - Returns the supported features of the I2C driver
880 * @adap: pointer to the i2c adapter structure
881 *
882 * Return: 32 bit value, each bit corresponding to a feature
883 */
cdns_i2c_func(struct i2c_adapter * adap)884 static u32 cdns_i2c_func(struct i2c_adapter *adap)
885 {
886 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
887 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
888 I2C_FUNC_SMBUS_BLOCK_DATA;
889
890 #if IS_ENABLED(CONFIG_I2C_SLAVE)
891 func |= I2C_FUNC_SLAVE;
892 #endif
893
894 return func;
895 }
896
897 #if IS_ENABLED(CONFIG_I2C_SLAVE)
cdns_reg_slave(struct i2c_client * slave)898 static int cdns_reg_slave(struct i2c_client *slave)
899 {
900 int ret;
901 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
902 adap);
903
904 if (id->slave)
905 return -EBUSY;
906
907 if (slave->flags & I2C_CLIENT_TEN)
908 return -EAFNOSUPPORT;
909
910 ret = pm_runtime_resume_and_get(id->dev);
911 if (ret < 0)
912 return ret;
913
914 /* Store slave information */
915 id->slave = slave;
916
917 /* Enable I2C slave */
918 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
919
920 return 0;
921 }
922
cdns_unreg_slave(struct i2c_client * slave)923 static int cdns_unreg_slave(struct i2c_client *slave)
924 {
925 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
926 adap);
927
928 pm_runtime_put(id->dev);
929
930 /* Remove slave information */
931 id->slave = NULL;
932
933 /* Enable I2C master */
934 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
935
936 return 0;
937 }
938 #endif
939
940 static const struct i2c_algorithm cdns_i2c_algo = {
941 .master_xfer = cdns_i2c_master_xfer,
942 .functionality = cdns_i2c_func,
943 #if IS_ENABLED(CONFIG_I2C_SLAVE)
944 .reg_slave = cdns_reg_slave,
945 .unreg_slave = cdns_unreg_slave,
946 #endif
947 };
948
949 /**
950 * cdns_i2c_calc_divs - Calculate clock dividers
951 * @f: I2C clock frequency
952 * @input_clk: Input clock frequency
953 * @a: First divider (return value)
954 * @b: Second divider (return value)
955 *
956 * f is used as input and output variable. As input it is used as target I2C
957 * frequency. On function exit f holds the actually resulting I2C frequency.
958 *
959 * Return: 0 on success, negative errno otherwise.
960 */
cdns_i2c_calc_divs(unsigned long * f,unsigned long input_clk,unsigned int * a,unsigned int * b)961 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
962 unsigned int *a, unsigned int *b)
963 {
964 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
965 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
966 unsigned int last_error, current_error;
967
968 /* calculate (divisor_a+1) x (divisor_b+1) */
969 temp = input_clk / (22 * fscl);
970
971 /*
972 * If the calculated value is negative or 0, the fscl input is out of
973 * range. Return error.
974 */
975 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
976 return -EINVAL;
977
978 last_error = -1;
979 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
980 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
981
982 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
983 continue;
984 div_b--;
985
986 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
987
988 if (actual_fscl > fscl)
989 continue;
990
991 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
992 (fscl - actual_fscl));
993
994 if (last_error > current_error) {
995 calc_div_a = div_a;
996 calc_div_b = div_b;
997 best_fscl = actual_fscl;
998 last_error = current_error;
999 }
1000 }
1001
1002 *a = calc_div_a;
1003 *b = calc_div_b;
1004 *f = best_fscl;
1005
1006 return 0;
1007 }
1008
1009 /**
1010 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
1011 * @clk_in: I2C clock input frequency in Hz
1012 * @id: Pointer to the I2C device structure
1013 *
1014 * The device must be idle rather than busy transferring data before setting
1015 * these device options.
1016 * The data rate is set by values in the control register.
1017 * The formula for determining the correct register values is
1018 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
1019 * See the hardware data sheet for a full explanation of setting the serial
1020 * clock rate. The clock can not be faster than the input clock divide by 22.
1021 * The two most common clock rates are 100KHz and 400KHz.
1022 *
1023 * Return: 0 on success, negative error otherwise
1024 */
cdns_i2c_setclk(unsigned long clk_in,struct cdns_i2c * id)1025 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
1026 {
1027 unsigned int div_a, div_b;
1028 unsigned int ctrl_reg;
1029 int ret = 0;
1030 unsigned long fscl = id->i2c_clk;
1031
1032 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
1033 if (ret)
1034 return ret;
1035
1036 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
1037 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
1038 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
1039 (div_b << CDNS_I2C_CR_DIVB_SHIFT));
1040 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1041 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1042 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
1043 CDNS_I2C_CR_DIVB_MASK);
1044 #endif
1045 return 0;
1046 }
1047
1048 /**
1049 * cdns_i2c_clk_notifier_cb - Clock rate change callback
1050 * @nb: Pointer to notifier block
1051 * @event: Notification reason
1052 * @data: Pointer to notification data object
1053 *
1054 * This function is called when the cdns_i2c input clock frequency changes.
1055 * The callback checks whether a valid bus frequency can be generated after the
1056 * change. If so, the change is acknowledged, otherwise the change is aborted.
1057 * New dividers are written to the HW in the pre- or post change notification
1058 * depending on the scaling direction.
1059 *
1060 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
1061 * to acknowledge the change, NOTIFY_DONE if the notification is
1062 * considered irrelevant.
1063 */
cdns_i2c_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)1064 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
1065 event, void *data)
1066 {
1067 struct clk_notifier_data *ndata = data;
1068 struct cdns_i2c *id = to_cdns_i2c(nb);
1069
1070 if (pm_runtime_suspended(id->dev))
1071 return NOTIFY_OK;
1072
1073 switch (event) {
1074 case PRE_RATE_CHANGE:
1075 {
1076 unsigned long input_clk = ndata->new_rate;
1077 unsigned long fscl = id->i2c_clk;
1078 unsigned int div_a, div_b;
1079 int ret;
1080
1081 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
1082 if (ret) {
1083 dev_warn(id->adap.dev.parent,
1084 "clock rate change rejected\n");
1085 return NOTIFY_STOP;
1086 }
1087
1088 /* scale up */
1089 if (ndata->new_rate > ndata->old_rate)
1090 cdns_i2c_setclk(ndata->new_rate, id);
1091
1092 return NOTIFY_OK;
1093 }
1094 case POST_RATE_CHANGE:
1095 id->input_clk = ndata->new_rate;
1096 /* scale down */
1097 if (ndata->new_rate < ndata->old_rate)
1098 cdns_i2c_setclk(ndata->new_rate, id);
1099 return NOTIFY_OK;
1100 case ABORT_RATE_CHANGE:
1101 /* scale up */
1102 if (ndata->new_rate > ndata->old_rate)
1103 cdns_i2c_setclk(ndata->old_rate, id);
1104 return NOTIFY_OK;
1105 default:
1106 return NOTIFY_DONE;
1107 }
1108 }
1109
1110 /**
1111 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver
1112 * @dev: Address of the platform_device structure
1113 *
1114 * Put the driver into low power mode.
1115 *
1116 * Return: 0 always
1117 */
cdns_i2c_runtime_suspend(struct device * dev)1118 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
1119 {
1120 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1121
1122 clk_disable(xi2c->clk);
1123
1124 return 0;
1125 }
1126
1127 /**
1128 * cdns_i2c_runtime_resume - Runtime resume
1129 * @dev: Address of the platform_device structure
1130 *
1131 * Runtime resume callback.
1132 *
1133 * Return: 0 on success and error value on error
1134 */
cdns_i2c_runtime_resume(struct device * dev)1135 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
1136 {
1137 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1138 int ret;
1139
1140 ret = clk_enable(xi2c->clk);
1141 if (ret) {
1142 dev_err(dev, "Cannot enable clock.\n");
1143 return ret;
1144 }
1145
1146 return 0;
1147 }
1148
1149 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
1150 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
1151 cdns_i2c_runtime_resume, NULL)
1152 };
1153
1154 static const struct cdns_platform_data r1p10_i2c_def = {
1155 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
1156 };
1157
1158 static const struct of_device_id cdns_i2c_of_match[] = {
1159 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
1160 { .compatible = "cdns,i2c-r1p14",},
1161 { /* end of table */ }
1162 };
1163 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
1164
1165 /**
1166 * cdns_i2c_probe - Platform registration call
1167 * @pdev: Handle to the platform device structure
1168 *
1169 * This function does all the memory allocation and registration for the i2c
1170 * device. User can modify the address mode to 10 bit address mode using the
1171 * ioctl call with option I2C_TENBIT.
1172 *
1173 * Return: 0 on success, negative error otherwise
1174 */
cdns_i2c_probe(struct platform_device * pdev)1175 static int cdns_i2c_probe(struct platform_device *pdev)
1176 {
1177 struct resource *r_mem;
1178 struct cdns_i2c *id;
1179 int ret;
1180 const struct of_device_id *match;
1181
1182 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
1183 if (!id)
1184 return -ENOMEM;
1185
1186 id->dev = &pdev->dev;
1187 platform_set_drvdata(pdev, id);
1188
1189 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
1190 if (match && match->data) {
1191 const struct cdns_platform_data *data = match->data;
1192 id->quirks = data->quirks;
1193 }
1194
1195 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
1196 if (IS_ERR(id->membase))
1197 return PTR_ERR(id->membase);
1198
1199 ret = platform_get_irq(pdev, 0);
1200 if (ret < 0)
1201 return ret;
1202 id->irq = ret;
1203
1204 id->adap.owner = THIS_MODULE;
1205 id->adap.dev.of_node = pdev->dev.of_node;
1206 id->adap.algo = &cdns_i2c_algo;
1207 id->adap.timeout = CDNS_I2C_TIMEOUT;
1208 id->adap.retries = 3; /* Default retry value. */
1209 id->adap.algo_data = id;
1210 id->adap.dev.parent = &pdev->dev;
1211 init_completion(&id->xfer_done);
1212 snprintf(id->adap.name, sizeof(id->adap.name),
1213 "Cadence I2C at %08lx", (unsigned long)r_mem->start);
1214
1215 id->clk = devm_clk_get(&pdev->dev, NULL);
1216 if (IS_ERR(id->clk)) {
1217 if (PTR_ERR(id->clk) != -EPROBE_DEFER)
1218 dev_err(&pdev->dev, "input clock not found.\n");
1219 return PTR_ERR(id->clk);
1220 }
1221 ret = clk_prepare_enable(id->clk);
1222 if (ret)
1223 dev_err(&pdev->dev, "Unable to enable clock.\n");
1224
1225 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
1226 pm_runtime_use_autosuspend(id->dev);
1227 pm_runtime_set_active(id->dev);
1228 pm_runtime_enable(id->dev);
1229
1230 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
1231 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
1232 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1233 id->input_clk = clk_get_rate(id->clk);
1234
1235 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1236 &id->i2c_clk);
1237 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
1238 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
1239
1240 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1241 /* Set initial mode to master */
1242 id->dev_mode = CDNS_I2C_MODE_MASTER;
1243 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
1244 #endif
1245 cdns_i2c_writereg(CDNS_I2C_CR_MASTER_EN_MASK, CDNS_I2C_CR_OFFSET);
1246
1247 ret = cdns_i2c_setclk(id->input_clk, id);
1248 if (ret) {
1249 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
1250 ret = -EINVAL;
1251 goto err_clk_dis;
1252 }
1253
1254 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
1255 DRIVER_NAME, id);
1256 if (ret) {
1257 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
1258 goto err_clk_dis;
1259 }
1260
1261 /*
1262 * Cadence I2C controller has a bug wherein it generates
1263 * invalid read transaction after HW timeout in master receiver mode.
1264 * HW timeout is not used by this driver and the interrupt is disabled.
1265 * But the feature itself cannot be disabled. Hence maximum value
1266 * is written to this register to reduce the chances of error.
1267 */
1268 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
1269
1270 ret = i2c_add_adapter(&id->adap);
1271 if (ret < 0)
1272 goto err_clk_dis;
1273
1274 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
1275 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
1276
1277 return 0;
1278
1279 err_clk_dis:
1280 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1281 clk_disable_unprepare(id->clk);
1282 pm_runtime_disable(&pdev->dev);
1283 pm_runtime_set_suspended(&pdev->dev);
1284 return ret;
1285 }
1286
1287 /**
1288 * cdns_i2c_remove - Unregister the device after releasing the resources
1289 * @pdev: Handle to the platform device structure
1290 *
1291 * This function frees all the resources allocated to the device.
1292 *
1293 * Return: 0 always
1294 */
cdns_i2c_remove(struct platform_device * pdev)1295 static int cdns_i2c_remove(struct platform_device *pdev)
1296 {
1297 struct cdns_i2c *id = platform_get_drvdata(pdev);
1298
1299 pm_runtime_disable(&pdev->dev);
1300 pm_runtime_set_suspended(&pdev->dev);
1301 pm_runtime_dont_use_autosuspend(&pdev->dev);
1302
1303 i2c_del_adapter(&id->adap);
1304 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1305 clk_disable_unprepare(id->clk);
1306
1307 return 0;
1308 }
1309
1310 static struct platform_driver cdns_i2c_drv = {
1311 .driver = {
1312 .name = DRIVER_NAME,
1313 .of_match_table = cdns_i2c_of_match,
1314 .pm = &cdns_i2c_dev_pm_ops,
1315 },
1316 .probe = cdns_i2c_probe,
1317 .remove = cdns_i2c_remove,
1318 };
1319
1320 module_platform_driver(cdns_i2c_drv);
1321
1322 MODULE_AUTHOR("Xilinx Inc.");
1323 MODULE_DESCRIPTION("Cadence I2C bus driver");
1324 MODULE_LICENSE("GPL");
1325