1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #define pr_fmt(fmt) "GICv3: " fmt
8
9 #include <linux/acpi.h>
10 #include <linux/cpu.h>
11 #include <linux/cpu_pm.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqdomain.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/percpu.h>
19 #include <linux/refcount.h>
20 #include <linux/slab.h>
21
22 #include <linux/irqchip.h>
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
26
27 #include <asm/cputype.h>
28 #include <asm/exception.h>
29 #include <asm/smp_plat.h>
30 #include <asm/virt.h>
31
32 #include "irq-gic-common.h"
33
34 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
35
36 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
37 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
38
39 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
40
41 struct redist_region {
42 void __iomem *redist_base;
43 phys_addr_t phys_base;
44 bool single_redist;
45 };
46
47 struct gic_chip_data {
48 struct fwnode_handle *fwnode;
49 void __iomem *dist_base;
50 struct redist_region *redist_regions;
51 struct rdists rdists;
52 struct irq_domain *domain;
53 u64 redist_stride;
54 u32 nr_redist_regions;
55 u64 flags;
56 bool has_rss;
57 unsigned int ppi_nr;
58 struct partition_desc **ppi_descs;
59 };
60
61 static struct gic_chip_data gic_data __read_mostly;
62 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
63
64 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
65 #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
66 #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
67
68 /*
69 * The behaviours of RPR and PMR registers differ depending on the value of
70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
71 * distributor and redistributors depends on whether security is enabled in the
72 * GIC.
73 *
74 * When security is enabled, non-secure priority values from the (re)distributor
75 * are presented to the GIC CPUIF as follow:
76 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
77 *
78 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
79 * EL1 are subject to a similar operation thus matching the priorities presented
80 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
81 * these values are unchanched by the GIC.
82 *
83 * see GICv3/GICv4 Architecture Specification (IHI0069D):
84 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
85 * priorities.
86 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
87 * interrupt.
88 */
89 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
90
91 /*
92 * Global static key controlling whether an update to PMR allowing more
93 * interrupts requires to be propagated to the redistributor (DSB SY).
94 * And this needs to be exported for modules to be able to enable
95 * interrupts...
96 */
97 DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
98 EXPORT_SYMBOL(gic_pmr_sync);
99
100 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
101 EXPORT_SYMBOL(gic_nonsecure_priorities);
102
103 /*
104 * When the Non-secure world has access to group 0 interrupts (as a
105 * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
106 * return the Distributor's view of the interrupt priority.
107 *
108 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
109 * written by software is moved to the Non-secure range by the Distributor.
110 *
111 * If both are true (which is when gic_nonsecure_priorities gets enabled),
112 * we need to shift down the priority programmed by software to match it
113 * against the value returned by ICC_RPR_EL1.
114 */
115 #define GICD_INT_RPR_PRI(priority) \
116 ({ \
117 u32 __priority = (priority); \
118 if (static_branch_unlikely(&gic_nonsecure_priorities)) \
119 __priority = 0x80 | (__priority >> 1); \
120 \
121 __priority; \
122 })
123
124 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
125 static refcount_t *ppi_nmi_refs;
126
127 static struct gic_kvm_info gic_v3_kvm_info;
128 static DEFINE_PER_CPU(bool, has_rss);
129
130 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
131 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
132 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
133 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
134
135 /* Our default, arbitrary priority value. Linux only uses one anyway. */
136 #define DEFAULT_PMR_VALUE 0xf0
137
138 enum gic_intid_range {
139 SGI_RANGE,
140 PPI_RANGE,
141 SPI_RANGE,
142 EPPI_RANGE,
143 ESPI_RANGE,
144 LPI_RANGE,
145 __INVALID_RANGE__
146 };
147
__get_intid_range(irq_hw_number_t hwirq)148 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
149 {
150 switch (hwirq) {
151 case 0 ... 15:
152 return SGI_RANGE;
153 case 16 ... 31:
154 return PPI_RANGE;
155 case 32 ... 1019:
156 return SPI_RANGE;
157 case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
158 return EPPI_RANGE;
159 case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
160 return ESPI_RANGE;
161 case 8192 ... GENMASK(23, 0):
162 return LPI_RANGE;
163 default:
164 return __INVALID_RANGE__;
165 }
166 }
167
get_intid_range(struct irq_data * d)168 static enum gic_intid_range get_intid_range(struct irq_data *d)
169 {
170 return __get_intid_range(d->hwirq);
171 }
172
gic_irq(struct irq_data * d)173 static inline unsigned int gic_irq(struct irq_data *d)
174 {
175 return d->hwirq;
176 }
177
gic_irq_in_rdist(struct irq_data * d)178 static inline bool gic_irq_in_rdist(struct irq_data *d)
179 {
180 switch (get_intid_range(d)) {
181 case SGI_RANGE:
182 case PPI_RANGE:
183 case EPPI_RANGE:
184 return true;
185 default:
186 return false;
187 }
188 }
189
gic_dist_base(struct irq_data * d)190 static inline void __iomem *gic_dist_base(struct irq_data *d)
191 {
192 switch (get_intid_range(d)) {
193 case SGI_RANGE:
194 case PPI_RANGE:
195 case EPPI_RANGE:
196 /* SGI+PPI -> SGI_base for this CPU */
197 return gic_data_rdist_sgi_base();
198
199 case SPI_RANGE:
200 case ESPI_RANGE:
201 /* SPI -> dist_base */
202 return gic_data.dist_base;
203
204 default:
205 return NULL;
206 }
207 }
208
gic_do_wait_for_rwp(void __iomem * base,u32 bit)209 static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
210 {
211 u32 count = 1000000; /* 1s! */
212
213 while (readl_relaxed(base + GICD_CTLR) & bit) {
214 count--;
215 if (!count) {
216 pr_err_ratelimited("RWP timeout, gone fishing\n");
217 return;
218 }
219 cpu_relax();
220 udelay(1);
221 }
222 }
223
224 /* Wait for completion of a distributor change */
gic_dist_wait_for_rwp(void)225 static void gic_dist_wait_for_rwp(void)
226 {
227 gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
228 }
229
230 /* Wait for completion of a redistributor change */
gic_redist_wait_for_rwp(void)231 static void gic_redist_wait_for_rwp(void)
232 {
233 gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
234 }
235
236 #ifdef CONFIG_ARM64
237
gic_read_iar(void)238 static u64 __maybe_unused gic_read_iar(void)
239 {
240 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
241 return gic_read_iar_cavium_thunderx();
242 else
243 return gic_read_iar_common();
244 }
245 #endif
246
gic_enable_redist(bool enable)247 static void gic_enable_redist(bool enable)
248 {
249 void __iomem *rbase;
250 u32 count = 1000000; /* 1s! */
251 u32 val;
252
253 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
254 return;
255
256 rbase = gic_data_rdist_rd_base();
257
258 val = readl_relaxed(rbase + GICR_WAKER);
259 if (enable)
260 /* Wake up this CPU redistributor */
261 val &= ~GICR_WAKER_ProcessorSleep;
262 else
263 val |= GICR_WAKER_ProcessorSleep;
264 writel_relaxed(val, rbase + GICR_WAKER);
265
266 if (!enable) { /* Check that GICR_WAKER is writeable */
267 val = readl_relaxed(rbase + GICR_WAKER);
268 if (!(val & GICR_WAKER_ProcessorSleep))
269 return; /* No PM support in this redistributor */
270 }
271
272 while (--count) {
273 val = readl_relaxed(rbase + GICR_WAKER);
274 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
275 break;
276 cpu_relax();
277 udelay(1);
278 }
279 if (!count)
280 pr_err_ratelimited("redistributor failed to %s...\n",
281 enable ? "wakeup" : "sleep");
282 }
283
284 /*
285 * Routines to disable, enable, EOI and route interrupts
286 */
convert_offset_index(struct irq_data * d,u32 offset,u32 * index)287 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
288 {
289 switch (get_intid_range(d)) {
290 case SGI_RANGE:
291 case PPI_RANGE:
292 case SPI_RANGE:
293 *index = d->hwirq;
294 return offset;
295 case EPPI_RANGE:
296 /*
297 * Contrary to the ESPI range, the EPPI range is contiguous
298 * to the PPI range in the registers, so let's adjust the
299 * displacement accordingly. Consistency is overrated.
300 */
301 *index = d->hwirq - EPPI_BASE_INTID + 32;
302 return offset;
303 case ESPI_RANGE:
304 *index = d->hwirq - ESPI_BASE_INTID;
305 switch (offset) {
306 case GICD_ISENABLER:
307 return GICD_ISENABLERnE;
308 case GICD_ICENABLER:
309 return GICD_ICENABLERnE;
310 case GICD_ISPENDR:
311 return GICD_ISPENDRnE;
312 case GICD_ICPENDR:
313 return GICD_ICPENDRnE;
314 case GICD_ISACTIVER:
315 return GICD_ISACTIVERnE;
316 case GICD_ICACTIVER:
317 return GICD_ICACTIVERnE;
318 case GICD_IPRIORITYR:
319 return GICD_IPRIORITYRnE;
320 case GICD_ICFGR:
321 return GICD_ICFGRnE;
322 case GICD_IROUTER:
323 return GICD_IROUTERnE;
324 default:
325 break;
326 }
327 break;
328 default:
329 break;
330 }
331
332 WARN_ON(1);
333 *index = d->hwirq;
334 return offset;
335 }
336
gic_peek_irq(struct irq_data * d,u32 offset)337 static int gic_peek_irq(struct irq_data *d, u32 offset)
338 {
339 void __iomem *base;
340 u32 index, mask;
341
342 offset = convert_offset_index(d, offset, &index);
343 mask = 1 << (index % 32);
344
345 if (gic_irq_in_rdist(d))
346 base = gic_data_rdist_sgi_base();
347 else
348 base = gic_data.dist_base;
349
350 return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
351 }
352
gic_poke_irq(struct irq_data * d,u32 offset)353 static void gic_poke_irq(struct irq_data *d, u32 offset)
354 {
355 void (*rwp_wait)(void);
356 void __iomem *base;
357 u32 index, mask;
358
359 offset = convert_offset_index(d, offset, &index);
360 mask = 1 << (index % 32);
361
362 if (gic_irq_in_rdist(d)) {
363 base = gic_data_rdist_sgi_base();
364 rwp_wait = gic_redist_wait_for_rwp;
365 } else {
366 base = gic_data.dist_base;
367 rwp_wait = gic_dist_wait_for_rwp;
368 }
369
370 writel_relaxed(mask, base + offset + (index / 32) * 4);
371 rwp_wait();
372 }
373
gic_mask_irq(struct irq_data * d)374 static void gic_mask_irq(struct irq_data *d)
375 {
376 gic_poke_irq(d, GICD_ICENABLER);
377 }
378
gic_eoimode1_mask_irq(struct irq_data * d)379 static void gic_eoimode1_mask_irq(struct irq_data *d)
380 {
381 gic_mask_irq(d);
382 /*
383 * When masking a forwarded interrupt, make sure it is
384 * deactivated as well.
385 *
386 * This ensures that an interrupt that is getting
387 * disabled/masked will not get "stuck", because there is
388 * noone to deactivate it (guest is being terminated).
389 */
390 if (irqd_is_forwarded_to_vcpu(d))
391 gic_poke_irq(d, GICD_ICACTIVER);
392 }
393
gic_unmask_irq(struct irq_data * d)394 static void gic_unmask_irq(struct irq_data *d)
395 {
396 gic_poke_irq(d, GICD_ISENABLER);
397 }
398
gic_supports_nmi(void)399 static inline bool gic_supports_nmi(void)
400 {
401 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
402 static_branch_likely(&supports_pseudo_nmis);
403 }
404
gic_irq_set_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool val)405 static int gic_irq_set_irqchip_state(struct irq_data *d,
406 enum irqchip_irq_state which, bool val)
407 {
408 u32 reg;
409
410 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */
411 return -EINVAL;
412
413 switch (which) {
414 case IRQCHIP_STATE_PENDING:
415 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
416 break;
417
418 case IRQCHIP_STATE_ACTIVE:
419 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
420 break;
421
422 case IRQCHIP_STATE_MASKED:
423 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
424 break;
425
426 default:
427 return -EINVAL;
428 }
429
430 gic_poke_irq(d, reg);
431 return 0;
432 }
433
gic_irq_get_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool * val)434 static int gic_irq_get_irqchip_state(struct irq_data *d,
435 enum irqchip_irq_state which, bool *val)
436 {
437 if (d->hwirq >= 8192) /* PPI/SPI only */
438 return -EINVAL;
439
440 switch (which) {
441 case IRQCHIP_STATE_PENDING:
442 *val = gic_peek_irq(d, GICD_ISPENDR);
443 break;
444
445 case IRQCHIP_STATE_ACTIVE:
446 *val = gic_peek_irq(d, GICD_ISACTIVER);
447 break;
448
449 case IRQCHIP_STATE_MASKED:
450 *val = !gic_peek_irq(d, GICD_ISENABLER);
451 break;
452
453 default:
454 return -EINVAL;
455 }
456
457 return 0;
458 }
459
gic_irq_set_prio(struct irq_data * d,u8 prio)460 static void gic_irq_set_prio(struct irq_data *d, u8 prio)
461 {
462 void __iomem *base = gic_dist_base(d);
463 u32 offset, index;
464
465 offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
466
467 writeb_relaxed(prio, base + offset + index);
468 }
469
gic_get_ppi_index(struct irq_data * d)470 static u32 gic_get_ppi_index(struct irq_data *d)
471 {
472 switch (get_intid_range(d)) {
473 case PPI_RANGE:
474 return d->hwirq - 16;
475 case EPPI_RANGE:
476 return d->hwirq - EPPI_BASE_INTID + 16;
477 default:
478 unreachable();
479 }
480 }
481
gic_irq_nmi_setup(struct irq_data * d)482 static int gic_irq_nmi_setup(struct irq_data *d)
483 {
484 struct irq_desc *desc = irq_to_desc(d->irq);
485
486 if (!gic_supports_nmi())
487 return -EINVAL;
488
489 if (gic_peek_irq(d, GICD_ISENABLER)) {
490 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
491 return -EINVAL;
492 }
493
494 /*
495 * A secondary irq_chip should be in charge of LPI request,
496 * it should not be possible to get there
497 */
498 if (WARN_ON(gic_irq(d) >= 8192))
499 return -EINVAL;
500
501 /* desc lock should already be held */
502 if (gic_irq_in_rdist(d)) {
503 u32 idx = gic_get_ppi_index(d);
504
505 /* Setting up PPI as NMI, only switch handler for first NMI */
506 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
507 refcount_set(&ppi_nmi_refs[idx], 1);
508 desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
509 }
510 } else {
511 desc->handle_irq = handle_fasteoi_nmi;
512 }
513
514 gic_irq_set_prio(d, GICD_INT_NMI_PRI);
515
516 return 0;
517 }
518
gic_irq_nmi_teardown(struct irq_data * d)519 static void gic_irq_nmi_teardown(struct irq_data *d)
520 {
521 struct irq_desc *desc = irq_to_desc(d->irq);
522
523 if (WARN_ON(!gic_supports_nmi()))
524 return;
525
526 if (gic_peek_irq(d, GICD_ISENABLER)) {
527 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
528 return;
529 }
530
531 /*
532 * A secondary irq_chip should be in charge of LPI request,
533 * it should not be possible to get there
534 */
535 if (WARN_ON(gic_irq(d) >= 8192))
536 return;
537
538 /* desc lock should already be held */
539 if (gic_irq_in_rdist(d)) {
540 u32 idx = gic_get_ppi_index(d);
541
542 /* Tearing down NMI, only switch handler for last NMI */
543 if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
544 desc->handle_irq = handle_percpu_devid_irq;
545 } else {
546 desc->handle_irq = handle_fasteoi_irq;
547 }
548
549 gic_irq_set_prio(d, GICD_INT_DEF_PRI);
550 }
551
gic_eoi_irq(struct irq_data * d)552 static void gic_eoi_irq(struct irq_data *d)
553 {
554 gic_write_eoir(gic_irq(d));
555 }
556
gic_eoimode1_eoi_irq(struct irq_data * d)557 static void gic_eoimode1_eoi_irq(struct irq_data *d)
558 {
559 /*
560 * No need to deactivate an LPI, or an interrupt that
561 * is is getting forwarded to a vcpu.
562 */
563 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
564 return;
565 gic_write_dir(gic_irq(d));
566 }
567
gic_set_type(struct irq_data * d,unsigned int type)568 static int gic_set_type(struct irq_data *d, unsigned int type)
569 {
570 enum gic_intid_range range;
571 unsigned int irq = gic_irq(d);
572 void (*rwp_wait)(void);
573 void __iomem *base;
574 u32 offset, index;
575 int ret;
576
577 range = get_intid_range(d);
578
579 /* Interrupt configuration for SGIs can't be changed */
580 if (range == SGI_RANGE)
581 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
582
583 /* SPIs have restrictions on the supported types */
584 if ((range == SPI_RANGE || range == ESPI_RANGE) &&
585 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
586 return -EINVAL;
587
588 if (gic_irq_in_rdist(d)) {
589 base = gic_data_rdist_sgi_base();
590 rwp_wait = gic_redist_wait_for_rwp;
591 } else {
592 base = gic_data.dist_base;
593 rwp_wait = gic_dist_wait_for_rwp;
594 }
595
596 offset = convert_offset_index(d, GICD_ICFGR, &index);
597
598 ret = gic_configure_irq(index, type, base + offset, rwp_wait);
599 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
600 /* Misconfigured PPIs are usually not fatal */
601 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
602 ret = 0;
603 }
604
605 return ret;
606 }
607
gic_irq_set_vcpu_affinity(struct irq_data * d,void * vcpu)608 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
609 {
610 if (get_intid_range(d) == SGI_RANGE)
611 return -EINVAL;
612
613 if (vcpu)
614 irqd_set_forwarded_to_vcpu(d);
615 else
616 irqd_clr_forwarded_to_vcpu(d);
617 return 0;
618 }
619
gic_mpidr_to_affinity(unsigned long mpidr)620 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
621 {
622 u64 aff;
623
624 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
625 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
626 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
627 MPIDR_AFFINITY_LEVEL(mpidr, 0));
628
629 return aff;
630 }
631
gic_deactivate_unhandled(u32 irqnr)632 static void gic_deactivate_unhandled(u32 irqnr)
633 {
634 if (static_branch_likely(&supports_deactivate_key)) {
635 if (irqnr < 8192)
636 gic_write_dir(irqnr);
637 } else {
638 gic_write_eoir(irqnr);
639 }
640 }
641
gic_handle_nmi(u32 irqnr,struct pt_regs * regs)642 static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
643 {
644 bool irqs_enabled = interrupts_enabled(regs);
645 int err;
646
647 if (irqs_enabled)
648 nmi_enter();
649
650 if (static_branch_likely(&supports_deactivate_key))
651 gic_write_eoir(irqnr);
652 /*
653 * Leave the PSR.I bit set to prevent other NMIs to be
654 * received while handling this one.
655 * PSR.I will be restored when we ERET to the
656 * interrupted context.
657 */
658 err = handle_domain_nmi(gic_data.domain, irqnr, regs);
659 if (err)
660 gic_deactivate_unhandled(irqnr);
661
662 if (irqs_enabled)
663 nmi_exit();
664 }
665
do_read_iar(struct pt_regs * regs)666 static u32 do_read_iar(struct pt_regs *regs)
667 {
668 u32 iar;
669
670 if (gic_supports_nmi() && unlikely(!interrupts_enabled(regs))) {
671 u64 pmr;
672
673 /*
674 * We were in a context with IRQs disabled. However, the
675 * entry code has set PMR to a value that allows any
676 * interrupt to be acknowledged, and not just NMIs. This can
677 * lead to surprising effects if the NMI has been retired in
678 * the meantime, and that there is an IRQ pending. The IRQ
679 * would then be taken in NMI context, something that nobody
680 * wants to debug twice.
681 *
682 * Until we sort this, drop PMR again to a level that will
683 * actually only allow NMIs before reading IAR, and then
684 * restore it to what it was.
685 */
686 pmr = gic_read_pmr();
687 gic_pmr_mask_irqs();
688 isb();
689
690 iar = gic_read_iar();
691
692 gic_write_pmr(pmr);
693 } else {
694 iar = gic_read_iar();
695 }
696
697 return iar;
698 }
699
gic_handle_irq(struct pt_regs * regs)700 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
701 {
702 u32 irqnr;
703
704 irqnr = do_read_iar(regs);
705
706 /* Check for special IDs first */
707 if ((irqnr >= 1020 && irqnr <= 1023))
708 return;
709
710 if (gic_supports_nmi() &&
711 unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) {
712 gic_handle_nmi(irqnr, regs);
713 return;
714 }
715
716 if (gic_prio_masking_enabled()) {
717 gic_pmr_mask_irqs();
718 gic_arch_enable_irqs();
719 }
720
721 if (static_branch_likely(&supports_deactivate_key))
722 gic_write_eoir(irqnr);
723 else
724 isb();
725
726 if (handle_domain_irq(gic_data.domain, irqnr, regs)) {
727 WARN_ONCE(true, "Unexpected interrupt received!\n");
728 gic_deactivate_unhandled(irqnr);
729 }
730 }
731
gic_get_pribits(void)732 static u32 gic_get_pribits(void)
733 {
734 u32 pribits;
735
736 pribits = gic_read_ctlr();
737 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
738 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
739 pribits++;
740
741 return pribits;
742 }
743
gic_has_group0(void)744 static bool gic_has_group0(void)
745 {
746 u32 val;
747 u32 old_pmr;
748
749 old_pmr = gic_read_pmr();
750
751 /*
752 * Let's find out if Group0 is under control of EL3 or not by
753 * setting the highest possible, non-zero priority in PMR.
754 *
755 * If SCR_EL3.FIQ is set, the priority gets shifted down in
756 * order for the CPU interface to set bit 7, and keep the
757 * actual priority in the non-secure range. In the process, it
758 * looses the least significant bit and the actual priority
759 * becomes 0x80. Reading it back returns 0, indicating that
760 * we're don't have access to Group0.
761 */
762 gic_write_pmr(BIT(8 - gic_get_pribits()));
763 val = gic_read_pmr();
764
765 gic_write_pmr(old_pmr);
766
767 return val != 0;
768 }
769
gic_dist_init(void)770 static void __init gic_dist_init(void)
771 {
772 unsigned int i;
773 u64 affinity;
774 void __iomem *base = gic_data.dist_base;
775 u32 val;
776
777 /* Disable the distributor */
778 writel_relaxed(0, base + GICD_CTLR);
779 gic_dist_wait_for_rwp();
780
781 /*
782 * Configure SPIs as non-secure Group-1. This will only matter
783 * if the GIC only has a single security state. This will not
784 * do the right thing if the kernel is running in secure mode,
785 * but that's not the intended use case anyway.
786 */
787 for (i = 32; i < GIC_LINE_NR; i += 32)
788 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
789
790 /* Extended SPI range, not handled by the GICv2/GICv3 common code */
791 for (i = 0; i < GIC_ESPI_NR; i += 32) {
792 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
793 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
794 }
795
796 for (i = 0; i < GIC_ESPI_NR; i += 32)
797 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
798
799 for (i = 0; i < GIC_ESPI_NR; i += 16)
800 writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
801
802 for (i = 0; i < GIC_ESPI_NR; i += 4)
803 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
804
805 /* Now do the common stuff, and wait for the distributor to drain */
806 gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);
807
808 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
809 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
810 pr_info("Enabling SGIs without active state\n");
811 val |= GICD_CTLR_nASSGIreq;
812 }
813
814 /* Enable distributor with ARE, Group1 */
815 writel_relaxed(val, base + GICD_CTLR);
816
817 /*
818 * Set all global interrupts to the boot CPU only. ARE must be
819 * enabled.
820 */
821 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
822 for (i = 32; i < GIC_LINE_NR; i++)
823 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
824
825 for (i = 0; i < GIC_ESPI_NR; i++)
826 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
827 }
828
gic_iterate_rdists(int (* fn)(struct redist_region *,void __iomem *))829 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
830 {
831 int ret = -ENODEV;
832 int i;
833
834 for (i = 0; i < gic_data.nr_redist_regions; i++) {
835 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
836 u64 typer;
837 u32 reg;
838
839 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
840 if (reg != GIC_PIDR2_ARCH_GICv3 &&
841 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
842 pr_warn("No redistributor present @%p\n", ptr);
843 break;
844 }
845
846 do {
847 typer = gic_read_typer(ptr + GICR_TYPER);
848 ret = fn(gic_data.redist_regions + i, ptr);
849 if (!ret)
850 return 0;
851
852 if (gic_data.redist_regions[i].single_redist)
853 break;
854
855 if (gic_data.redist_stride) {
856 ptr += gic_data.redist_stride;
857 } else {
858 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
859 if (typer & GICR_TYPER_VLPIS)
860 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
861 }
862 } while (!(typer & GICR_TYPER_LAST));
863 }
864
865 return ret ? -ENODEV : 0;
866 }
867
__gic_populate_rdist(struct redist_region * region,void __iomem * ptr)868 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
869 {
870 unsigned long mpidr = cpu_logical_map(smp_processor_id());
871 u64 typer;
872 u32 aff;
873
874 /*
875 * Convert affinity to a 32bit value that can be matched to
876 * GICR_TYPER bits [63:32].
877 */
878 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
879 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
880 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
881 MPIDR_AFFINITY_LEVEL(mpidr, 0));
882
883 typer = gic_read_typer(ptr + GICR_TYPER);
884 if ((typer >> 32) == aff) {
885 u64 offset = ptr - region->redist_base;
886 raw_spin_lock_init(&gic_data_rdist()->rd_lock);
887 gic_data_rdist_rd_base() = ptr;
888 gic_data_rdist()->phys_base = region->phys_base + offset;
889
890 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
891 smp_processor_id(), mpidr,
892 (int)(region - gic_data.redist_regions),
893 &gic_data_rdist()->phys_base);
894 return 0;
895 }
896
897 /* Try next one */
898 return 1;
899 }
900
gic_populate_rdist(void)901 static int gic_populate_rdist(void)
902 {
903 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
904 return 0;
905
906 /* We couldn't even deal with ourselves... */
907 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
908 smp_processor_id(),
909 (unsigned long)cpu_logical_map(smp_processor_id()));
910 return -ENODEV;
911 }
912
__gic_update_rdist_properties(struct redist_region * region,void __iomem * ptr)913 static int __gic_update_rdist_properties(struct redist_region *region,
914 void __iomem *ptr)
915 {
916 u64 typer = gic_read_typer(ptr + GICR_TYPER);
917
918 /* Boot-time cleanip */
919 if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) {
920 u64 val;
921
922 /* Deactivate any present vPE */
923 val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER);
924 if (val & GICR_VPENDBASER_Valid)
925 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
926 ptr + SZ_128K + GICR_VPENDBASER);
927
928 /* Mark the VPE table as invalid */
929 val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER);
930 val &= ~GICR_VPROPBASER_4_1_VALID;
931 gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER);
932 }
933
934 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
935
936 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */
937 gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
938 gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
939 gic_data.rdists.has_rvpeid);
940 gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
941
942 /* Detect non-sensical configurations */
943 if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
944 gic_data.rdists.has_direct_lpi = false;
945 gic_data.rdists.has_vlpis = false;
946 gic_data.rdists.has_rvpeid = false;
947 }
948
949 gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
950
951 return 1;
952 }
953
gic_update_rdist_properties(void)954 static void gic_update_rdist_properties(void)
955 {
956 gic_data.ppi_nr = UINT_MAX;
957 gic_iterate_rdists(__gic_update_rdist_properties);
958 if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
959 gic_data.ppi_nr = 0;
960 pr_info("%d PPIs implemented\n", gic_data.ppi_nr);
961 if (gic_data.rdists.has_vlpis)
962 pr_info("GICv4 features: %s%s%s\n",
963 gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
964 gic_data.rdists.has_rvpeid ? "RVPEID " : "",
965 gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
966 }
967
968 /* Check whether it's single security state view */
gic_dist_security_disabled(void)969 static inline bool gic_dist_security_disabled(void)
970 {
971 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
972 }
973
gic_cpu_sys_reg_init(void)974 static void gic_cpu_sys_reg_init(void)
975 {
976 int i, cpu = smp_processor_id();
977 u64 mpidr = cpu_logical_map(cpu);
978 u64 need_rss = MPIDR_RS(mpidr);
979 bool group0;
980 u32 pribits;
981
982 /*
983 * Need to check that the SRE bit has actually been set. If
984 * not, it means that SRE is disabled at EL2. We're going to
985 * die painfully, and there is nothing we can do about it.
986 *
987 * Kindly inform the luser.
988 */
989 if (!gic_enable_sre())
990 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
991
992 pribits = gic_get_pribits();
993
994 group0 = gic_has_group0();
995
996 /* Set priority mask register */
997 if (!gic_prio_masking_enabled()) {
998 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
999 } else if (gic_supports_nmi()) {
1000 /*
1001 * Mismatch configuration with boot CPU, the system is likely
1002 * to die as interrupt masking will not work properly on all
1003 * CPUs
1004 *
1005 * The boot CPU calls this function before enabling NMI support,
1006 * and as a result we'll never see this warning in the boot path
1007 * for that CPU.
1008 */
1009 if (static_branch_unlikely(&gic_nonsecure_priorities))
1010 WARN_ON(!group0 || gic_dist_security_disabled());
1011 else
1012 WARN_ON(group0 && !gic_dist_security_disabled());
1013 }
1014
1015 /*
1016 * Some firmwares hand over to the kernel with the BPR changed from
1017 * its reset value (and with a value large enough to prevent
1018 * any pre-emptive interrupts from working at all). Writing a zero
1019 * to BPR restores is reset value.
1020 */
1021 gic_write_bpr1(0);
1022
1023 if (static_branch_likely(&supports_deactivate_key)) {
1024 /* EOI drops priority only (mode 1) */
1025 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
1026 } else {
1027 /* EOI deactivates interrupt too (mode 0) */
1028 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
1029 }
1030
1031 /* Always whack Group0 before Group1 */
1032 if (group0) {
1033 switch(pribits) {
1034 case 8:
1035 case 7:
1036 write_gicreg(0, ICC_AP0R3_EL1);
1037 write_gicreg(0, ICC_AP0R2_EL1);
1038 fallthrough;
1039 case 6:
1040 write_gicreg(0, ICC_AP0R1_EL1);
1041 fallthrough;
1042 case 5:
1043 case 4:
1044 write_gicreg(0, ICC_AP0R0_EL1);
1045 }
1046
1047 isb();
1048 }
1049
1050 switch(pribits) {
1051 case 8:
1052 case 7:
1053 write_gicreg(0, ICC_AP1R3_EL1);
1054 write_gicreg(0, ICC_AP1R2_EL1);
1055 fallthrough;
1056 case 6:
1057 write_gicreg(0, ICC_AP1R1_EL1);
1058 fallthrough;
1059 case 5:
1060 case 4:
1061 write_gicreg(0, ICC_AP1R0_EL1);
1062 }
1063
1064 isb();
1065
1066 /* ... and let's hit the road... */
1067 gic_write_grpen1(1);
1068
1069 /* Keep the RSS capability status in per_cpu variable */
1070 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
1071
1072 /* Check all the CPUs have capable of sending SGIs to other CPUs */
1073 for_each_online_cpu(i) {
1074 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
1075
1076 need_rss |= MPIDR_RS(cpu_logical_map(i));
1077 if (need_rss && (!have_rss))
1078 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
1079 cpu, (unsigned long)mpidr,
1080 i, (unsigned long)cpu_logical_map(i));
1081 }
1082
1083 /**
1084 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
1085 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
1086 * UNPREDICTABLE choice of :
1087 * - The write is ignored.
1088 * - The RS field is treated as 0.
1089 */
1090 if (need_rss && (!gic_data.has_rss))
1091 pr_crit_once("RSS is required but GICD doesn't support it\n");
1092 }
1093
1094 static bool gicv3_nolpi;
1095
gicv3_nolpi_cfg(char * buf)1096 static int __init gicv3_nolpi_cfg(char *buf)
1097 {
1098 return strtobool(buf, &gicv3_nolpi);
1099 }
1100 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
1101
gic_dist_supports_lpis(void)1102 static int gic_dist_supports_lpis(void)
1103 {
1104 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
1105 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
1106 !gicv3_nolpi);
1107 }
1108
gic_cpu_init(void)1109 static void gic_cpu_init(void)
1110 {
1111 void __iomem *rbase;
1112 int i;
1113
1114 /* Register ourselves with the rest of the world */
1115 if (gic_populate_rdist())
1116 return;
1117
1118 gic_enable_redist(true);
1119
1120 WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
1121 !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
1122 "Distributor has extended ranges, but CPU%d doesn't\n",
1123 smp_processor_id());
1124
1125 rbase = gic_data_rdist_sgi_base();
1126
1127 /* Configure SGIs/PPIs as non-secure Group-1 */
1128 for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
1129 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
1130
1131 gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
1132
1133 /* initialise system registers */
1134 gic_cpu_sys_reg_init();
1135 }
1136
1137 #ifdef CONFIG_SMP
1138
1139 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
1140 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
1141
gic_starting_cpu(unsigned int cpu)1142 static int gic_starting_cpu(unsigned int cpu)
1143 {
1144 gic_cpu_init();
1145
1146 if (gic_dist_supports_lpis())
1147 its_cpu_init();
1148
1149 return 0;
1150 }
1151
gic_compute_target_list(int * base_cpu,const struct cpumask * mask,unsigned long cluster_id)1152 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
1153 unsigned long cluster_id)
1154 {
1155 int next_cpu, cpu = *base_cpu;
1156 unsigned long mpidr = cpu_logical_map(cpu);
1157 u16 tlist = 0;
1158
1159 while (cpu < nr_cpu_ids) {
1160 tlist |= 1 << (mpidr & 0xf);
1161
1162 next_cpu = cpumask_next(cpu, mask);
1163 if (next_cpu >= nr_cpu_ids)
1164 goto out;
1165 cpu = next_cpu;
1166
1167 mpidr = cpu_logical_map(cpu);
1168
1169 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
1170 cpu--;
1171 goto out;
1172 }
1173 }
1174 out:
1175 *base_cpu = cpu;
1176 return tlist;
1177 }
1178
1179 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
1180 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
1181 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
1182
gic_send_sgi(u64 cluster_id,u16 tlist,unsigned int irq)1183 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
1184 {
1185 u64 val;
1186
1187 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
1188 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
1189 irq << ICC_SGI1R_SGI_ID_SHIFT |
1190 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
1191 MPIDR_TO_SGI_RS(cluster_id) |
1192 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
1193
1194 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
1195 gic_write_sgi1r(val);
1196 }
1197
gic_ipi_send_mask(struct irq_data * d,const struct cpumask * mask)1198 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
1199 {
1200 int cpu;
1201
1202 if (WARN_ON(d->hwirq >= 16))
1203 return;
1204
1205 /*
1206 * Ensure that stores to Normal memory are visible to the
1207 * other CPUs before issuing the IPI.
1208 */
1209 wmb();
1210
1211 for_each_cpu(cpu, mask) {
1212 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
1213 u16 tlist;
1214
1215 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1216 gic_send_sgi(cluster_id, tlist, d->hwirq);
1217 }
1218
1219 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
1220 isb();
1221 }
1222
gic_smp_init(void)1223 static void __init gic_smp_init(void)
1224 {
1225 struct irq_fwspec sgi_fwspec = {
1226 .fwnode = gic_data.fwnode,
1227 .param_count = 1,
1228 };
1229 int base_sgi;
1230
1231 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1232 "irqchip/arm/gicv3:starting",
1233 gic_starting_cpu, NULL);
1234
1235 /* Register all 8 non-secure SGIs */
1236 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8,
1237 NUMA_NO_NODE, &sgi_fwspec,
1238 false, NULL);
1239 if (WARN_ON(base_sgi <= 0))
1240 return;
1241
1242 set_smp_ipi_range(base_sgi, 8);
1243 }
1244
gic_set_affinity(struct irq_data * d,const struct cpumask * mask_val,bool force)1245 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1246 bool force)
1247 {
1248 unsigned int cpu;
1249 u32 offset, index;
1250 void __iomem *reg;
1251 int enabled;
1252 u64 val;
1253
1254 if (force)
1255 cpu = cpumask_first(mask_val);
1256 else
1257 cpu = cpumask_any_and(mask_val, cpu_online_mask);
1258
1259 if (cpu >= nr_cpu_ids)
1260 return -EINVAL;
1261
1262 if (gic_irq_in_rdist(d))
1263 return -EINVAL;
1264
1265 /* If interrupt was enabled, disable it first */
1266 enabled = gic_peek_irq(d, GICD_ISENABLER);
1267 if (enabled)
1268 gic_mask_irq(d);
1269
1270 offset = convert_offset_index(d, GICD_IROUTER, &index);
1271 reg = gic_dist_base(d) + offset + (index * 8);
1272 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
1273
1274 gic_write_irouter(val, reg);
1275
1276 /*
1277 * If the interrupt was enabled, enabled it again. Otherwise,
1278 * just wait for the distributor to have digested our changes.
1279 */
1280 if (enabled)
1281 gic_unmask_irq(d);
1282 else
1283 gic_dist_wait_for_rwp();
1284
1285 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1286
1287 return IRQ_SET_MASK_OK_DONE;
1288 }
1289 #else
1290 #define gic_set_affinity NULL
1291 #define gic_ipi_send_mask NULL
1292 #define gic_smp_init() do { } while(0)
1293 #endif
1294
gic_retrigger(struct irq_data * data)1295 static int gic_retrigger(struct irq_data *data)
1296 {
1297 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
1298 }
1299
1300 #ifdef CONFIG_CPU_PM
gic_cpu_pm_notifier(struct notifier_block * self,unsigned long cmd,void * v)1301 static int gic_cpu_pm_notifier(struct notifier_block *self,
1302 unsigned long cmd, void *v)
1303 {
1304 if (cmd == CPU_PM_EXIT) {
1305 if (gic_dist_security_disabled())
1306 gic_enable_redist(true);
1307 gic_cpu_sys_reg_init();
1308 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
1309 gic_write_grpen1(0);
1310 gic_enable_redist(false);
1311 }
1312 return NOTIFY_OK;
1313 }
1314
1315 static struct notifier_block gic_cpu_pm_notifier_block = {
1316 .notifier_call = gic_cpu_pm_notifier,
1317 };
1318
gic_cpu_pm_init(void)1319 static void gic_cpu_pm_init(void)
1320 {
1321 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1322 }
1323
1324 #else
gic_cpu_pm_init(void)1325 static inline void gic_cpu_pm_init(void) { }
1326 #endif /* CONFIG_CPU_PM */
1327
1328 static struct irq_chip gic_chip = {
1329 .name = "GICv3",
1330 .irq_mask = gic_mask_irq,
1331 .irq_unmask = gic_unmask_irq,
1332 .irq_eoi = gic_eoi_irq,
1333 .irq_set_type = gic_set_type,
1334 .irq_set_affinity = gic_set_affinity,
1335 .irq_retrigger = gic_retrigger,
1336 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1337 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1338 .irq_nmi_setup = gic_irq_nmi_setup,
1339 .irq_nmi_teardown = gic_irq_nmi_teardown,
1340 .ipi_send_mask = gic_ipi_send_mask,
1341 .flags = IRQCHIP_SET_TYPE_MASKED |
1342 IRQCHIP_SKIP_SET_WAKE |
1343 IRQCHIP_MASK_ON_SUSPEND,
1344 };
1345
1346 static struct irq_chip gic_eoimode1_chip = {
1347 .name = "GICv3",
1348 .irq_mask = gic_eoimode1_mask_irq,
1349 .irq_unmask = gic_unmask_irq,
1350 .irq_eoi = gic_eoimode1_eoi_irq,
1351 .irq_set_type = gic_set_type,
1352 .irq_set_affinity = gic_set_affinity,
1353 .irq_retrigger = gic_retrigger,
1354 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1355 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1356 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
1357 .irq_nmi_setup = gic_irq_nmi_setup,
1358 .irq_nmi_teardown = gic_irq_nmi_teardown,
1359 .ipi_send_mask = gic_ipi_send_mask,
1360 .flags = IRQCHIP_SET_TYPE_MASKED |
1361 IRQCHIP_SKIP_SET_WAKE |
1362 IRQCHIP_MASK_ON_SUSPEND,
1363 };
1364
gic_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)1365 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1366 irq_hw_number_t hw)
1367 {
1368 struct irq_chip *chip = &gic_chip;
1369 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1370
1371 if (static_branch_likely(&supports_deactivate_key))
1372 chip = &gic_eoimode1_chip;
1373
1374 switch (__get_intid_range(hw)) {
1375 case SGI_RANGE:
1376 irq_set_percpu_devid(irq);
1377 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1378 handle_percpu_devid_fasteoi_ipi,
1379 NULL, NULL);
1380 break;
1381
1382 case PPI_RANGE:
1383 case EPPI_RANGE:
1384 irq_set_percpu_devid(irq);
1385 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1386 handle_percpu_devid_irq, NULL, NULL);
1387 break;
1388
1389 case SPI_RANGE:
1390 case ESPI_RANGE:
1391 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1392 handle_fasteoi_irq, NULL, NULL);
1393 irq_set_probe(irq);
1394 irqd_set_single_target(irqd);
1395 break;
1396
1397 case LPI_RANGE:
1398 if (!gic_dist_supports_lpis())
1399 return -EPERM;
1400 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1401 handle_fasteoi_irq, NULL, NULL);
1402 break;
1403
1404 default:
1405 return -EPERM;
1406 }
1407
1408 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1409 irqd_set_handle_enforce_irqctx(irqd);
1410 return 0;
1411 }
1412
gic_irq_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1413 static int gic_irq_domain_translate(struct irq_domain *d,
1414 struct irq_fwspec *fwspec,
1415 unsigned long *hwirq,
1416 unsigned int *type)
1417 {
1418 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1419 *hwirq = fwspec->param[0];
1420 *type = IRQ_TYPE_EDGE_RISING;
1421 return 0;
1422 }
1423
1424 if (is_of_node(fwspec->fwnode)) {
1425 if (fwspec->param_count < 3)
1426 return -EINVAL;
1427
1428 switch (fwspec->param[0]) {
1429 case 0: /* SPI */
1430 *hwirq = fwspec->param[1] + 32;
1431 break;
1432 case 1: /* PPI */
1433 *hwirq = fwspec->param[1] + 16;
1434 break;
1435 case 2: /* ESPI */
1436 *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
1437 break;
1438 case 3: /* EPPI */
1439 *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
1440 break;
1441 case GIC_IRQ_TYPE_LPI: /* LPI */
1442 *hwirq = fwspec->param[1];
1443 break;
1444 case GIC_IRQ_TYPE_PARTITION:
1445 *hwirq = fwspec->param[1];
1446 if (fwspec->param[1] >= 16)
1447 *hwirq += EPPI_BASE_INTID - 16;
1448 else
1449 *hwirq += 16;
1450 break;
1451 default:
1452 return -EINVAL;
1453 }
1454
1455 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1456
1457 /*
1458 * Make it clear that broken DTs are... broken.
1459 * Partitionned PPIs are an unfortunate exception.
1460 */
1461 WARN_ON(*type == IRQ_TYPE_NONE &&
1462 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1463 return 0;
1464 }
1465
1466 if (is_fwnode_irqchip(fwspec->fwnode)) {
1467 if(fwspec->param_count != 2)
1468 return -EINVAL;
1469
1470 if (fwspec->param[0] < 16) {
1471 pr_err(FW_BUG "Illegal GSI%d translation request\n",
1472 fwspec->param[0]);
1473 return -EINVAL;
1474 }
1475
1476 *hwirq = fwspec->param[0];
1477 *type = fwspec->param[1];
1478
1479 WARN_ON(*type == IRQ_TYPE_NONE);
1480 return 0;
1481 }
1482
1483 return -EINVAL;
1484 }
1485
gic_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)1486 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1487 unsigned int nr_irqs, void *arg)
1488 {
1489 int i, ret;
1490 irq_hw_number_t hwirq;
1491 unsigned int type = IRQ_TYPE_NONE;
1492 struct irq_fwspec *fwspec = arg;
1493
1494 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1495 if (ret)
1496 return ret;
1497
1498 for (i = 0; i < nr_irqs; i++) {
1499 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1500 if (ret)
1501 return ret;
1502 }
1503
1504 return 0;
1505 }
1506
gic_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)1507 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1508 unsigned int nr_irqs)
1509 {
1510 int i;
1511
1512 for (i = 0; i < nr_irqs; i++) {
1513 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1514 irq_set_handler(virq + i, NULL);
1515 irq_domain_reset_irq_data(d);
1516 }
1517 }
1518
gic_irq_domain_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)1519 static int gic_irq_domain_select(struct irq_domain *d,
1520 struct irq_fwspec *fwspec,
1521 enum irq_domain_bus_token bus_token)
1522 {
1523 /* Not for us */
1524 if (fwspec->fwnode != d->fwnode)
1525 return 0;
1526
1527 /* If this is not DT, then we have a single domain */
1528 if (!is_of_node(fwspec->fwnode))
1529 return 1;
1530
1531 /*
1532 * If this is a PPI and we have a 4th (non-null) parameter,
1533 * then we need to match the partition domain.
1534 */
1535 if (fwspec->param_count >= 4 &&
1536 fwspec->param[0] == 1 && fwspec->param[3] != 0 &&
1537 gic_data.ppi_descs)
1538 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1539
1540 return d == gic_data.domain;
1541 }
1542
1543 static const struct irq_domain_ops gic_irq_domain_ops = {
1544 .translate = gic_irq_domain_translate,
1545 .alloc = gic_irq_domain_alloc,
1546 .free = gic_irq_domain_free,
1547 .select = gic_irq_domain_select,
1548 };
1549
partition_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1550 static int partition_domain_translate(struct irq_domain *d,
1551 struct irq_fwspec *fwspec,
1552 unsigned long *hwirq,
1553 unsigned int *type)
1554 {
1555 struct device_node *np;
1556 int ret;
1557
1558 if (!gic_data.ppi_descs)
1559 return -ENOMEM;
1560
1561 np = of_find_node_by_phandle(fwspec->param[3]);
1562 if (WARN_ON(!np))
1563 return -EINVAL;
1564
1565 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1566 of_node_to_fwnode(np));
1567 if (ret < 0)
1568 return ret;
1569
1570 *hwirq = ret;
1571 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1572
1573 return 0;
1574 }
1575
1576 static const struct irq_domain_ops partition_domain_ops = {
1577 .translate = partition_domain_translate,
1578 .select = gic_irq_domain_select,
1579 };
1580
gic_enable_quirk_msm8996(void * data)1581 static bool gic_enable_quirk_msm8996(void *data)
1582 {
1583 struct gic_chip_data *d = data;
1584
1585 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1586
1587 return true;
1588 }
1589
gic_enable_quirk_cavium_38539(void * data)1590 static bool gic_enable_quirk_cavium_38539(void *data)
1591 {
1592 struct gic_chip_data *d = data;
1593
1594 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1595
1596 return true;
1597 }
1598
gic_enable_quirk_hip06_07(void * data)1599 static bool gic_enable_quirk_hip06_07(void *data)
1600 {
1601 struct gic_chip_data *d = data;
1602
1603 /*
1604 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
1605 * not being an actual ARM implementation). The saving grace is
1606 * that GIC-600 doesn't have ESPI, so nothing to do in that case.
1607 * HIP07 doesn't even have a proper IIDR, and still pretends to
1608 * have ESPI. In both cases, put them right.
1609 */
1610 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
1611 /* Zero both ESPI and the RES0 field next to it... */
1612 d->rdists.gicd_typer &= ~GENMASK(9, 8);
1613 return true;
1614 }
1615
1616 return false;
1617 }
1618
1619 static const struct gic_quirk gic_quirks[] = {
1620 {
1621 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1622 .compatible = "qcom,msm8996-gic-v3",
1623 .init = gic_enable_quirk_msm8996,
1624 },
1625 {
1626 .desc = "GICv3: HIP06 erratum 161010803",
1627 .iidr = 0x0204043b,
1628 .mask = 0xffffffff,
1629 .init = gic_enable_quirk_hip06_07,
1630 },
1631 {
1632 .desc = "GICv3: HIP07 erratum 161010803",
1633 .iidr = 0x00000000,
1634 .mask = 0xffffffff,
1635 .init = gic_enable_quirk_hip06_07,
1636 },
1637 {
1638 /*
1639 * Reserved register accesses generate a Synchronous
1640 * External Abort. This erratum applies to:
1641 * - ThunderX: CN88xx
1642 * - OCTEON TX: CN83xx, CN81xx
1643 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1644 */
1645 .desc = "GICv3: Cavium erratum 38539",
1646 .iidr = 0xa000034c,
1647 .mask = 0xe8f00fff,
1648 .init = gic_enable_quirk_cavium_38539,
1649 },
1650 {
1651 }
1652 };
1653
gic_enable_nmi_support(void)1654 static void gic_enable_nmi_support(void)
1655 {
1656 int i;
1657
1658 if (!gic_prio_masking_enabled())
1659 return;
1660
1661 ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
1662 if (!ppi_nmi_refs)
1663 return;
1664
1665 for (i = 0; i < gic_data.ppi_nr; i++)
1666 refcount_set(&ppi_nmi_refs[i], 0);
1667
1668 /*
1669 * Linux itself doesn't use 1:N distribution, so has no need to
1670 * set PMHE. The only reason to have it set is if EL3 requires it
1671 * (and we can't change it).
1672 */
1673 if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
1674 static_branch_enable(&gic_pmr_sync);
1675
1676 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
1677 static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed");
1678
1679 /*
1680 * How priority values are used by the GIC depends on two things:
1681 * the security state of the GIC (controlled by the GICD_CTRL.DS bit)
1682 * and if Group 0 interrupts can be delivered to Linux in the non-secure
1683 * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
1684 * the ICC_PMR_EL1 register and the priority that software assigns to
1685 * interrupts:
1686 *
1687 * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority
1688 * -----------------------------------------------------------
1689 * 1 | - | unchanged | unchanged
1690 * -----------------------------------------------------------
1691 * 0 | 1 | non-secure | non-secure
1692 * -----------------------------------------------------------
1693 * 0 | 0 | unchanged | non-secure
1694 *
1695 * where non-secure means that the value is right-shifted by one and the
1696 * MSB bit set, to make it fit in the non-secure priority range.
1697 *
1698 * In the first two cases, where ICC_PMR_EL1 and the interrupt priority
1699 * are both either modified or unchanged, we can use the same set of
1700 * priorities.
1701 *
1702 * In the last case, where only the interrupt priorities are modified to
1703 * be in the non-secure range, we use a different PMR value to mask IRQs
1704 * and the rest of the values that we use remain unchanged.
1705 */
1706 if (gic_has_group0() && !gic_dist_security_disabled())
1707 static_branch_enable(&gic_nonsecure_priorities);
1708
1709 static_branch_enable(&supports_pseudo_nmis);
1710
1711 if (static_branch_likely(&supports_deactivate_key))
1712 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1713 else
1714 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1715 }
1716
gic_init_bases(void __iomem * dist_base,struct redist_region * rdist_regs,u32 nr_redist_regions,u64 redist_stride,struct fwnode_handle * handle)1717 static int __init gic_init_bases(void __iomem *dist_base,
1718 struct redist_region *rdist_regs,
1719 u32 nr_redist_regions,
1720 u64 redist_stride,
1721 struct fwnode_handle *handle)
1722 {
1723 u32 typer;
1724 int err;
1725
1726 if (!is_hyp_mode_available())
1727 static_branch_disable(&supports_deactivate_key);
1728
1729 if (static_branch_likely(&supports_deactivate_key))
1730 pr_info("GIC: Using split EOI/Deactivate mode\n");
1731
1732 gic_data.fwnode = handle;
1733 gic_data.dist_base = dist_base;
1734 gic_data.redist_regions = rdist_regs;
1735 gic_data.nr_redist_regions = nr_redist_regions;
1736 gic_data.redist_stride = redist_stride;
1737
1738 /*
1739 * Find out how many interrupts are supported.
1740 */
1741 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1742 gic_data.rdists.gicd_typer = typer;
1743
1744 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
1745 gic_quirks, &gic_data);
1746
1747 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1748 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1749
1750 /*
1751 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1752 * architecture spec (which says that reserved registers are RES0).
1753 */
1754 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1755 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1756
1757 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1758 &gic_data);
1759 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1760 gic_data.rdists.has_rvpeid = true;
1761 gic_data.rdists.has_vlpis = true;
1762 gic_data.rdists.has_direct_lpi = true;
1763 gic_data.rdists.has_vpend_valid_dirty = true;
1764
1765 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1766 err = -ENOMEM;
1767 goto out_free;
1768 }
1769
1770 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1771
1772 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1773 pr_info("Distributor has %sRange Selector support\n",
1774 gic_data.has_rss ? "" : "no ");
1775
1776 if (typer & GICD_TYPER_MBIS) {
1777 err = mbi_init(handle, gic_data.domain);
1778 if (err)
1779 pr_err("Failed to initialize MBIs\n");
1780 }
1781
1782 set_handle_irq(gic_handle_irq);
1783
1784 gic_update_rdist_properties();
1785
1786 gic_dist_init();
1787 gic_cpu_init();
1788 gic_smp_init();
1789 gic_cpu_pm_init();
1790
1791 if (gic_dist_supports_lpis()) {
1792 its_init(handle, &gic_data.rdists, gic_data.domain);
1793 its_cpu_init();
1794 } else {
1795 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1796 gicv2m_init(handle, gic_data.domain);
1797 }
1798
1799 gic_enable_nmi_support();
1800
1801 return 0;
1802
1803 out_free:
1804 if (gic_data.domain)
1805 irq_domain_remove(gic_data.domain);
1806 free_percpu(gic_data.rdists.rdist);
1807 return err;
1808 }
1809
gic_validate_dist_version(void __iomem * dist_base)1810 static int __init gic_validate_dist_version(void __iomem *dist_base)
1811 {
1812 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1813
1814 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1815 return -ENODEV;
1816
1817 return 0;
1818 }
1819
1820 /* Create all possible partitions at boot time */
gic_populate_ppi_partitions(struct device_node * gic_node)1821 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1822 {
1823 struct device_node *parts_node, *child_part;
1824 int part_idx = 0, i;
1825 int nr_parts;
1826 struct partition_affinity *parts;
1827
1828 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1829 if (!parts_node)
1830 return;
1831
1832 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
1833 if (!gic_data.ppi_descs)
1834 goto out_put_node;
1835
1836 nr_parts = of_get_child_count(parts_node);
1837
1838 if (!nr_parts)
1839 goto out_put_node;
1840
1841 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1842 if (WARN_ON(!parts))
1843 goto out_put_node;
1844
1845 for_each_child_of_node(parts_node, child_part) {
1846 struct partition_affinity *part;
1847 int n;
1848
1849 part = &parts[part_idx];
1850
1851 part->partition_id = of_node_to_fwnode(child_part);
1852
1853 pr_info("GIC: PPI partition %pOFn[%d] { ",
1854 child_part, part_idx);
1855
1856 n = of_property_count_elems_of_size(child_part, "affinity",
1857 sizeof(u32));
1858 WARN_ON(n <= 0);
1859
1860 for (i = 0; i < n; i++) {
1861 int err, cpu;
1862 u32 cpu_phandle;
1863 struct device_node *cpu_node;
1864
1865 err = of_property_read_u32_index(child_part, "affinity",
1866 i, &cpu_phandle);
1867 if (WARN_ON(err))
1868 continue;
1869
1870 cpu_node = of_find_node_by_phandle(cpu_phandle);
1871 if (WARN_ON(!cpu_node))
1872 continue;
1873
1874 cpu = of_cpu_node_to_id(cpu_node);
1875 if (WARN_ON(cpu < 0)) {
1876 of_node_put(cpu_node);
1877 continue;
1878 }
1879
1880 pr_cont("%pOF[%d] ", cpu_node, cpu);
1881
1882 cpumask_set_cpu(cpu, &part->mask);
1883 of_node_put(cpu_node);
1884 }
1885
1886 pr_cont("}\n");
1887 part_idx++;
1888 }
1889
1890 for (i = 0; i < gic_data.ppi_nr; i++) {
1891 unsigned int irq;
1892 struct partition_desc *desc;
1893 struct irq_fwspec ppi_fwspec = {
1894 .fwnode = gic_data.fwnode,
1895 .param_count = 3,
1896 .param = {
1897 [0] = GIC_IRQ_TYPE_PARTITION,
1898 [1] = i,
1899 [2] = IRQ_TYPE_NONE,
1900 },
1901 };
1902
1903 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1904 if (WARN_ON(!irq))
1905 continue;
1906 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1907 irq, &partition_domain_ops);
1908 if (WARN_ON(!desc))
1909 continue;
1910
1911 gic_data.ppi_descs[i] = desc;
1912 }
1913
1914 out_put_node:
1915 of_node_put(parts_node);
1916 }
1917
gic_of_setup_kvm_info(struct device_node * node)1918 static void __init gic_of_setup_kvm_info(struct device_node *node)
1919 {
1920 int ret;
1921 struct resource r;
1922 u32 gicv_idx;
1923
1924 gic_v3_kvm_info.type = GIC_V3;
1925
1926 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1927 if (!gic_v3_kvm_info.maint_irq)
1928 return;
1929
1930 if (of_property_read_u32(node, "#redistributor-regions",
1931 &gicv_idx))
1932 gicv_idx = 1;
1933
1934 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
1935 ret = of_address_to_resource(node, gicv_idx, &r);
1936 if (!ret)
1937 gic_v3_kvm_info.vcpu = r;
1938
1939 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1940 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
1941 gic_set_kvm_info(&gic_v3_kvm_info);
1942 }
1943
gic_of_init(struct device_node * node,struct device_node * parent)1944 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1945 {
1946 void __iomem *dist_base;
1947 struct redist_region *rdist_regs;
1948 u64 redist_stride;
1949 u32 nr_redist_regions;
1950 int err, i;
1951
1952 dist_base = of_iomap(node, 0);
1953 if (!dist_base) {
1954 pr_err("%pOF: unable to map gic dist registers\n", node);
1955 return -ENXIO;
1956 }
1957
1958 err = gic_validate_dist_version(dist_base);
1959 if (err) {
1960 pr_err("%pOF: no distributor detected, giving up\n", node);
1961 goto out_unmap_dist;
1962 }
1963
1964 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1965 nr_redist_regions = 1;
1966
1967 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
1968 GFP_KERNEL);
1969 if (!rdist_regs) {
1970 err = -ENOMEM;
1971 goto out_unmap_dist;
1972 }
1973
1974 for (i = 0; i < nr_redist_regions; i++) {
1975 struct resource res;
1976 int ret;
1977
1978 ret = of_address_to_resource(node, 1 + i, &res);
1979 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1980 if (ret || !rdist_regs[i].redist_base) {
1981 pr_err("%pOF: couldn't map region %d\n", node, i);
1982 err = -ENODEV;
1983 goto out_unmap_rdist;
1984 }
1985 rdist_regs[i].phys_base = res.start;
1986 }
1987
1988 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1989 redist_stride = 0;
1990
1991 gic_enable_of_quirks(node, gic_quirks, &gic_data);
1992
1993 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1994 redist_stride, &node->fwnode);
1995 if (err)
1996 goto out_unmap_rdist;
1997
1998 gic_populate_ppi_partitions(node);
1999
2000 if (static_branch_likely(&supports_deactivate_key))
2001 gic_of_setup_kvm_info(node);
2002 return 0;
2003
2004 out_unmap_rdist:
2005 for (i = 0; i < nr_redist_regions; i++)
2006 if (rdist_regs[i].redist_base)
2007 iounmap(rdist_regs[i].redist_base);
2008 kfree(rdist_regs);
2009 out_unmap_dist:
2010 iounmap(dist_base);
2011 return err;
2012 }
2013
2014 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2015
2016 #ifdef CONFIG_ACPI
2017 static struct
2018 {
2019 void __iomem *dist_base;
2020 struct redist_region *redist_regs;
2021 u32 nr_redist_regions;
2022 bool single_redist;
2023 int enabled_rdists;
2024 u32 maint_irq;
2025 int maint_irq_mode;
2026 phys_addr_t vcpu_base;
2027 } acpi_data __initdata;
2028
2029 static void __init
gic_acpi_register_redist(phys_addr_t phys_base,void __iomem * redist_base)2030 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
2031 {
2032 static int count = 0;
2033
2034 acpi_data.redist_regs[count].phys_base = phys_base;
2035 acpi_data.redist_regs[count].redist_base = redist_base;
2036 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
2037 count++;
2038 }
2039
2040 static int __init
gic_acpi_parse_madt_redist(union acpi_subtable_headers * header,const unsigned long end)2041 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
2042 const unsigned long end)
2043 {
2044 struct acpi_madt_generic_redistributor *redist =
2045 (struct acpi_madt_generic_redistributor *)header;
2046 void __iomem *redist_base;
2047
2048 redist_base = ioremap(redist->base_address, redist->length);
2049 if (!redist_base) {
2050 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
2051 return -ENOMEM;
2052 }
2053
2054 gic_acpi_register_redist(redist->base_address, redist_base);
2055 return 0;
2056 }
2057
2058 static int __init
gic_acpi_parse_madt_gicc(union acpi_subtable_headers * header,const unsigned long end)2059 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
2060 const unsigned long end)
2061 {
2062 struct acpi_madt_generic_interrupt *gicc =
2063 (struct acpi_madt_generic_interrupt *)header;
2064 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
2065 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
2066 void __iomem *redist_base;
2067
2068 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
2069 if (!(gicc->flags & ACPI_MADT_ENABLED))
2070 return 0;
2071
2072 redist_base = ioremap(gicc->gicr_base_address, size);
2073 if (!redist_base)
2074 return -ENOMEM;
2075
2076 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
2077 return 0;
2078 }
2079
gic_acpi_collect_gicr_base(void)2080 static int __init gic_acpi_collect_gicr_base(void)
2081 {
2082 acpi_tbl_entry_handler redist_parser;
2083 enum acpi_madt_type type;
2084
2085 if (acpi_data.single_redist) {
2086 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
2087 redist_parser = gic_acpi_parse_madt_gicc;
2088 } else {
2089 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
2090 redist_parser = gic_acpi_parse_madt_redist;
2091 }
2092
2093 /* Collect redistributor base addresses in GICR entries */
2094 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
2095 return 0;
2096
2097 pr_info("No valid GICR entries exist\n");
2098 return -ENODEV;
2099 }
2100
gic_acpi_match_gicr(union acpi_subtable_headers * header,const unsigned long end)2101 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
2102 const unsigned long end)
2103 {
2104 /* Subtable presence means that redist exists, that's it */
2105 return 0;
2106 }
2107
gic_acpi_match_gicc(union acpi_subtable_headers * header,const unsigned long end)2108 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
2109 const unsigned long end)
2110 {
2111 struct acpi_madt_generic_interrupt *gicc =
2112 (struct acpi_madt_generic_interrupt *)header;
2113
2114 /*
2115 * If GICC is enabled and has valid gicr base address, then it means
2116 * GICR base is presented via GICC
2117 */
2118 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
2119 acpi_data.enabled_rdists++;
2120 return 0;
2121 }
2122
2123 /*
2124 * It's perfectly valid firmware can pass disabled GICC entry, driver
2125 * should not treat as errors, skip the entry instead of probe fail.
2126 */
2127 if (!(gicc->flags & ACPI_MADT_ENABLED))
2128 return 0;
2129
2130 return -ENODEV;
2131 }
2132
gic_acpi_count_gicr_regions(void)2133 static int __init gic_acpi_count_gicr_regions(void)
2134 {
2135 int count;
2136
2137 /*
2138 * Count how many redistributor regions we have. It is not allowed
2139 * to mix redistributor description, GICR and GICC subtables have to be
2140 * mutually exclusive.
2141 */
2142 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
2143 gic_acpi_match_gicr, 0);
2144 if (count > 0) {
2145 acpi_data.single_redist = false;
2146 return count;
2147 }
2148
2149 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2150 gic_acpi_match_gicc, 0);
2151 if (count > 0) {
2152 acpi_data.single_redist = true;
2153 count = acpi_data.enabled_rdists;
2154 }
2155
2156 return count;
2157 }
2158
acpi_validate_gic_table(struct acpi_subtable_header * header,struct acpi_probe_entry * ape)2159 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
2160 struct acpi_probe_entry *ape)
2161 {
2162 struct acpi_madt_generic_distributor *dist;
2163 int count;
2164
2165 dist = (struct acpi_madt_generic_distributor *)header;
2166 if (dist->version != ape->driver_data)
2167 return false;
2168
2169 /* We need to do that exercise anyway, the sooner the better */
2170 count = gic_acpi_count_gicr_regions();
2171 if (count <= 0)
2172 return false;
2173
2174 acpi_data.nr_redist_regions = count;
2175 return true;
2176 }
2177
gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers * header,const unsigned long end)2178 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
2179 const unsigned long end)
2180 {
2181 struct acpi_madt_generic_interrupt *gicc =
2182 (struct acpi_madt_generic_interrupt *)header;
2183 int maint_irq_mode;
2184 static int first_madt = true;
2185
2186 /* Skip unusable CPUs */
2187 if (!(gicc->flags & ACPI_MADT_ENABLED))
2188 return 0;
2189
2190 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
2191 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
2192
2193 if (first_madt) {
2194 first_madt = false;
2195
2196 acpi_data.maint_irq = gicc->vgic_interrupt;
2197 acpi_data.maint_irq_mode = maint_irq_mode;
2198 acpi_data.vcpu_base = gicc->gicv_base_address;
2199
2200 return 0;
2201 }
2202
2203 /*
2204 * The maintenance interrupt and GICV should be the same for every CPU
2205 */
2206 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
2207 (acpi_data.maint_irq_mode != maint_irq_mode) ||
2208 (acpi_data.vcpu_base != gicc->gicv_base_address))
2209 return -EINVAL;
2210
2211 return 0;
2212 }
2213
gic_acpi_collect_virt_info(void)2214 static bool __init gic_acpi_collect_virt_info(void)
2215 {
2216 int count;
2217
2218 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2219 gic_acpi_parse_virt_madt_gicc, 0);
2220
2221 return (count > 0);
2222 }
2223
2224 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
2225 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
2226 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
2227
gic_acpi_setup_kvm_info(void)2228 static void __init gic_acpi_setup_kvm_info(void)
2229 {
2230 int irq;
2231
2232 if (!gic_acpi_collect_virt_info()) {
2233 pr_warn("Unable to get hardware information used for virtualization\n");
2234 return;
2235 }
2236
2237 gic_v3_kvm_info.type = GIC_V3;
2238
2239 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
2240 acpi_data.maint_irq_mode,
2241 ACPI_ACTIVE_HIGH);
2242 if (irq <= 0)
2243 return;
2244
2245 gic_v3_kvm_info.maint_irq = irq;
2246
2247 if (acpi_data.vcpu_base) {
2248 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
2249
2250 vcpu->flags = IORESOURCE_MEM;
2251 vcpu->start = acpi_data.vcpu_base;
2252 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
2253 }
2254
2255 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2256 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2257 gic_set_kvm_info(&gic_v3_kvm_info);
2258 }
2259
2260 static int __init
gic_acpi_init(union acpi_subtable_headers * header,const unsigned long end)2261 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
2262 {
2263 struct acpi_madt_generic_distributor *dist;
2264 struct fwnode_handle *domain_handle;
2265 size_t size;
2266 int i, err;
2267
2268 /* Get distributor base address */
2269 dist = (struct acpi_madt_generic_distributor *)header;
2270 acpi_data.dist_base = ioremap(dist->base_address,
2271 ACPI_GICV3_DIST_MEM_SIZE);
2272 if (!acpi_data.dist_base) {
2273 pr_err("Unable to map GICD registers\n");
2274 return -ENOMEM;
2275 }
2276
2277 err = gic_validate_dist_version(acpi_data.dist_base);
2278 if (err) {
2279 pr_err("No distributor detected at @%p, giving up\n",
2280 acpi_data.dist_base);
2281 goto out_dist_unmap;
2282 }
2283
2284 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
2285 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
2286 if (!acpi_data.redist_regs) {
2287 err = -ENOMEM;
2288 goto out_dist_unmap;
2289 }
2290
2291 err = gic_acpi_collect_gicr_base();
2292 if (err)
2293 goto out_redist_unmap;
2294
2295 domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
2296 if (!domain_handle) {
2297 err = -ENOMEM;
2298 goto out_redist_unmap;
2299 }
2300
2301 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
2302 acpi_data.nr_redist_regions, 0, domain_handle);
2303 if (err)
2304 goto out_fwhandle_free;
2305
2306 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
2307
2308 if (static_branch_likely(&supports_deactivate_key))
2309 gic_acpi_setup_kvm_info();
2310
2311 return 0;
2312
2313 out_fwhandle_free:
2314 irq_domain_free_fwnode(domain_handle);
2315 out_redist_unmap:
2316 for (i = 0; i < acpi_data.nr_redist_regions; i++)
2317 if (acpi_data.redist_regs[i].redist_base)
2318 iounmap(acpi_data.redist_regs[i].redist_base);
2319 kfree(acpi_data.redist_regs);
2320 out_dist_unmap:
2321 iounmap(acpi_data.dist_base);
2322 return err;
2323 }
2324 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2325 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
2326 gic_acpi_init);
2327 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2328 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
2329 gic_acpi_init);
2330 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2331 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
2332 gic_acpi_init);
2333 #endif
2334