1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #ifndef _I40E_H_
5 #define _I40E_H_
6
7 #include <net/tcp.h>
8 #include <net/udp.h>
9 #include <linux/types.h>
10 #include <linux/errno.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/aer.h>
14 #include <linux/netdevice.h>
15 #include <linux/ioport.h>
16 #include <linux/iommu.h>
17 #include <linux/slab.h>
18 #include <linux/list.h>
19 #include <linux/hashtable.h>
20 #include <linux/string.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/sctp.h>
24 #include <linux/pkt_sched.h>
25 #include <linux/ipv6.h>
26 #include <net/checksum.h>
27 #include <net/ip6_checksum.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/if_macvlan.h>
31 #include <linux/if_bridge.h>
32 #include <linux/clocksource.h>
33 #include <linux/net_tstamp.h>
34 #include <linux/ptp_clock_kernel.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_mirred.h>
38 #include <net/udp_tunnel.h>
39 #include <net/xdp_sock.h>
40 #include <linux/bitfield.h>
41 #include "i40e_type.h"
42 #include "i40e_prototype.h"
43 #include <linux/net/intel/i40e_client.h>
44 #include <linux/avf/virtchnl.h>
45 #include "i40e_virtchnl_pf.h"
46 #include "i40e_txrx.h"
47 #include "i40e_dcb.h"
48
49 /* Useful i40e defaults */
50 #define I40E_MAX_VEB 16
51
52 #define I40E_MAX_NUM_DESCRIPTORS 4096
53 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
54 #define I40E_DEFAULT_NUM_DESCRIPTORS 512
55 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32
56 #define I40E_MIN_NUM_DESCRIPTORS 64
57 #define I40E_MIN_MSIX 2
58 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
59 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
60 /* max 16 qps */
61 #define i40e_default_queues_per_vmdq(pf) \
62 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
63 #define I40E_DEFAULT_QUEUES_PER_VF 4
64 #define I40E_MAX_VF_QUEUES 16
65 #define i40e_pf_get_max_q_per_tc(pf) \
66 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
67 #define I40E_FDIR_RING_COUNT 32
68 #define I40E_MAX_AQ_BUF_SIZE 4096
69 #define I40E_AQ_LEN 256
70 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
71 #define I40E_MAX_USER_PRIORITY 8
72 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
73 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
74 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
75
76 #define I40E_NVM_VERSION_LO_SHIFT 0
77 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
78 #define I40E_NVM_VERSION_HI_SHIFT 12
79 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
80 #define I40E_OEM_VER_BUILD_MASK 0xffff
81 #define I40E_OEM_VER_PATCH_MASK 0xff
82 #define I40E_OEM_VER_BUILD_SHIFT 8
83 #define I40E_OEM_VER_SHIFT 24
84 #define I40E_PHY_DEBUG_ALL \
85 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
86 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
87
88 #define I40E_OEM_EETRACK_ID 0xffffffff
89 #define I40E_OEM_GEN_SHIFT 24
90 #define I40E_OEM_SNAP_MASK 0x00ff0000
91 #define I40E_OEM_SNAP_SHIFT 16
92 #define I40E_OEM_RELEASE_MASK 0x0000ffff
93
94 #define I40E_RX_DESC(R, i) \
95 (&(((union i40e_rx_desc *)((R)->desc))[i]))
96 #define I40E_TX_DESC(R, i) \
97 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
98 #define I40E_TX_CTXTDESC(R, i) \
99 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
100 #define I40E_TX_FDIRDESC(R, i) \
101 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
102
103 /* BW rate limiting */
104 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
105 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
106 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
107
108 /* driver state flags */
109 enum i40e_state_t {
110 __I40E_TESTING,
111 __I40E_CONFIG_BUSY,
112 __I40E_CONFIG_DONE,
113 __I40E_DOWN,
114 __I40E_SERVICE_SCHED,
115 __I40E_ADMINQ_EVENT_PENDING,
116 __I40E_MDD_EVENT_PENDING,
117 __I40E_VFLR_EVENT_PENDING,
118 __I40E_RESET_RECOVERY_PENDING,
119 __I40E_TIMEOUT_RECOVERY_PENDING,
120 __I40E_MISC_IRQ_REQUESTED,
121 __I40E_RESET_INTR_RECEIVED,
122 __I40E_REINIT_REQUESTED,
123 __I40E_PF_RESET_REQUESTED,
124 __I40E_PF_RESET_AND_REBUILD_REQUESTED,
125 __I40E_CORE_RESET_REQUESTED,
126 __I40E_GLOBAL_RESET_REQUESTED,
127 __I40E_EMP_RESET_INTR_RECEIVED,
128 __I40E_SUSPENDED,
129 __I40E_PTP_TX_IN_PROGRESS,
130 __I40E_BAD_EEPROM,
131 __I40E_DOWN_REQUESTED,
132 __I40E_FD_FLUSH_REQUESTED,
133 __I40E_FD_ATR_AUTO_DISABLED,
134 __I40E_FD_SB_AUTO_DISABLED,
135 __I40E_RESET_FAILED,
136 __I40E_PORT_SUSPENDED,
137 __I40E_VF_DISABLE,
138 __I40E_MACVLAN_SYNC_PENDING,
139 __I40E_TEMP_LINK_POLLING,
140 __I40E_CLIENT_SERVICE_REQUESTED,
141 __I40E_CLIENT_L2_CHANGE,
142 __I40E_CLIENT_RESET,
143 __I40E_VIRTCHNL_OP_PENDING,
144 __I40E_RECOVERY_MODE,
145 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */
146 __I40E_VFS_RELEASING,
147 /* This must be last as it determines the size of the BITMAP */
148 __I40E_STATE_SIZE__,
149 };
150
151 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
152 #define I40E_PF_RESET_AND_REBUILD_FLAG \
153 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
154
155 /* VSI state flags */
156 enum i40e_vsi_state_t {
157 __I40E_VSI_DOWN,
158 __I40E_VSI_NEEDS_RESTART,
159 __I40E_VSI_SYNCING_FILTERS,
160 __I40E_VSI_OVERFLOW_PROMISC,
161 __I40E_VSI_REINIT_REQUESTED,
162 __I40E_VSI_DOWN_REQUESTED,
163 __I40E_VSI_RELEASING,
164 /* This must be last as it determines the size of the BITMAP */
165 __I40E_VSI_STATE_SIZE__,
166 };
167
168 enum i40e_interrupt_policy {
169 I40E_INTERRUPT_BEST_CASE,
170 I40E_INTERRUPT_MEDIUM,
171 I40E_INTERRUPT_LOWEST
172 };
173
174 struct i40e_lump_tracking {
175 u16 num_entries;
176 u16 list[0];
177 #define I40E_PILE_VALID_BIT 0x8000
178 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
179 };
180
181 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20
182 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
183 #define I40E_FDIR_BUFFER_FULL_MARGIN 10
184 #define I40E_FDIR_BUFFER_HEAD_ROOM 32
185 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
186
187 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
188 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
189 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
190
191 enum i40e_fd_stat_idx {
192 I40E_FD_STAT_ATR,
193 I40E_FD_STAT_SB,
194 I40E_FD_STAT_ATR_TUNNEL,
195 I40E_FD_STAT_PF_COUNT
196 };
197 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
198 #define I40E_FD_ATR_STAT_IDX(pf_id) \
199 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
200 #define I40E_FD_SB_STAT_IDX(pf_id) \
201 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
202 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
203 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
204
205 /* The following structure contains the data parsed from the user-defined
206 * field of the ethtool_rx_flow_spec structure.
207 */
208 struct i40e_rx_flow_userdef {
209 bool flex_filter;
210 u16 flex_word;
211 u16 flex_offset;
212 };
213
214 struct i40e_fdir_filter {
215 struct hlist_node fdir_node;
216 /* filter ipnut set */
217 u8 flow_type;
218 u8 ip4_proto;
219 /* TX packet view of src and dst */
220 __be32 dst_ip;
221 __be32 src_ip;
222 __be16 src_port;
223 __be16 dst_port;
224 __be32 sctp_v_tag;
225
226 /* Flexible data to match within the packet payload */
227 __be16 flex_word;
228 u16 flex_offset;
229 bool flex_filter;
230
231 /* filter control */
232 u16 q_index;
233 u8 flex_off;
234 u8 pctype;
235 u16 dest_vsi;
236 u8 dest_ctl;
237 u8 fd_status;
238 u16 cnt_index;
239 u32 fd_id;
240 };
241
242 #define I40E_CLOUD_FIELD_OMAC BIT(0)
243 #define I40E_CLOUD_FIELD_IMAC BIT(1)
244 #define I40E_CLOUD_FIELD_IVLAN BIT(2)
245 #define I40E_CLOUD_FIELD_TEN_ID BIT(3)
246 #define I40E_CLOUD_FIELD_IIP BIT(4)
247
248 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
249 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
250 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
251 I40E_CLOUD_FIELD_IVLAN)
252 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
253 I40E_CLOUD_FIELD_TEN_ID)
254 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
255 I40E_CLOUD_FIELD_IMAC | \
256 I40E_CLOUD_FIELD_TEN_ID)
257 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
258 I40E_CLOUD_FIELD_IVLAN | \
259 I40E_CLOUD_FIELD_TEN_ID)
260 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
261
262 struct i40e_cloud_filter {
263 struct hlist_node cloud_node;
264 unsigned long cookie;
265 /* cloud filter input set follows */
266 u8 dst_mac[ETH_ALEN];
267 u8 src_mac[ETH_ALEN];
268 __be16 vlan_id;
269 u16 seid; /* filter control */
270 __be16 dst_port;
271 __be16 src_port;
272 u32 tenant_id;
273 union {
274 struct {
275 struct in_addr dst_ip;
276 struct in_addr src_ip;
277 } v4;
278 struct {
279 struct in6_addr dst_ip6;
280 struct in6_addr src_ip6;
281 } v6;
282 } ip;
283 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32
284 #define src_ipv6 ip.v6.src_ip6.s6_addr32
285 #define dst_ipv4 ip.v4.dst_ip.s_addr
286 #define src_ipv4 ip.v4.src_ip.s_addr
287 u16 n_proto; /* Ethernet Protocol */
288 u8 ip_proto; /* IPPROTO value */
289 u8 flags;
290 #define I40E_CLOUD_TNL_TYPE_NONE 0xff
291 u8 tunnel_type;
292 };
293
294 /* DCB per TC information data structure */
295 struct i40e_tc_info {
296 u16 qoffset; /* Queue offset from base queue */
297 u16 qcount; /* Total Queues */
298 u8 netdev_tc; /* Netdev TC index if netdev associated */
299 };
300
301 /* TC configuration data structure */
302 struct i40e_tc_configuration {
303 u8 numtc; /* Total number of enabled TCs */
304 u8 enabled_tc; /* TC map */
305 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
306 };
307
308 #define I40E_UDP_PORT_INDEX_UNUSED 255
309 struct i40e_udp_port_config {
310 /* AdminQ command interface expects port number in Host byte order */
311 u16 port;
312 u8 type;
313 u8 filter_index;
314 };
315
316 #define I40_DDP_FLASH_REGION 100
317 #define I40E_PROFILE_INFO_SIZE 48
318 #define I40E_MAX_PROFILE_NUM 16
319 #define I40E_PROFILE_LIST_SIZE \
320 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
321 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
322 #define I40E_DDP_PROFILE_NAME_MAX 64
323
324 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
325 bool is_add);
326 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
327
328 struct i40e_ddp_profile_list {
329 u32 p_count;
330 struct i40e_profile_info p_info[];
331 };
332
333 struct i40e_ddp_old_profile_list {
334 struct list_head list;
335 size_t old_ddp_size;
336 u8 old_ddp_buf[];
337 };
338
339 /* macros related to FLX_PIT */
340 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
341 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
342 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
343 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
344 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
345 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
346 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
347 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
348 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
349 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
350 I40E_FLEX_SET_FSIZE(fsize) | \
351 I40E_FLEX_SET_SRC_WORD(src))
352
353
354 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
355
356 /* macros related to GLQF_ORT */
357 #define I40E_ORT_SET_IDX(idx) (((idx) << \
358 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
359 I40E_GLQF_ORT_PIT_INDX_MASK)
360
361 #define I40E_ORT_SET_COUNT(count) (((count) << \
362 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
363 I40E_GLQF_ORT_FIELD_CNT_MASK)
364
365 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
366 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
367 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
368
369 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
370 I40E_ORT_SET_COUNT(count) | \
371 I40E_ORT_SET_PAYLOAD(payload))
372
373 #define I40E_L3_GLQF_ORT_IDX 34
374 #define I40E_L4_GLQF_ORT_IDX 35
375
376 /* Flex PIT register index */
377 #define I40E_FLEX_PIT_IDX_START_L3 3
378 #define I40E_FLEX_PIT_IDX_START_L4 6
379
380 #define I40E_FLEX_PIT_TABLE_SIZE 3
381
382 #define I40E_FLEX_DEST_UNUSED 63
383
384 #define I40E_FLEX_INDEX_ENTRIES 8
385
386 /* Flex MASK to disable all flexible entries */
387 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
388 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
389 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
390 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
391
392 struct i40e_flex_pit {
393 struct list_head list;
394 u16 src_offset;
395 u8 pit_index;
396 };
397
398 struct i40e_fwd_adapter {
399 struct net_device *netdev;
400 int bit_no;
401 };
402
403 struct i40e_channel {
404 struct list_head list;
405 bool initialized;
406 u8 type;
407 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
408 u16 stat_counter_idx;
409 u16 base_queue;
410 u16 num_queue_pairs; /* Requested by user */
411 u16 seid;
412
413 u8 enabled_tc;
414 struct i40e_aqc_vsi_properties_data info;
415
416 u64 max_tx_rate;
417 struct i40e_fwd_adapter *fwd;
418
419 /* track this channel belongs to which VSI */
420 struct i40e_vsi *parent_vsi;
421 };
422
i40e_is_channel_macvlan(struct i40e_channel * ch)423 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
424 {
425 return !!ch->fwd;
426 }
427
i40e_channel_mac(struct i40e_channel * ch)428 static inline u8 *i40e_channel_mac(struct i40e_channel *ch)
429 {
430 if (i40e_is_channel_macvlan(ch))
431 return ch->fwd->netdev->dev_addr;
432 else
433 return NULL;
434 }
435
436 /* struct that defines the Ethernet device */
437 struct i40e_pf {
438 struct pci_dev *pdev;
439 struct i40e_hw hw;
440 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
441 struct msix_entry *msix_entries;
442 bool fc_autoneg_status;
443
444 u16 eeprom_version;
445 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
446 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
447 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
448 u16 num_req_vfs; /* num VFs requested for this PF */
449 u16 num_vf_qps; /* num queue pairs per VF */
450 u16 num_lan_qps; /* num lan queues this PF has set up */
451 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
452 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
453 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
454 int iwarp_base_vector;
455 int queues_left; /* queues left unclaimed */
456 u16 alloc_rss_size; /* allocated RSS queues */
457 u16 rss_size_max; /* HW defined max RSS queues */
458 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
459 u16 num_alloc_vsi; /* num VSIs this driver supports */
460 u8 atr_sample_rate;
461 bool wol_en;
462
463 struct hlist_head fdir_filter_list;
464 u16 fdir_pf_active_filters;
465 unsigned long fd_flush_timestamp;
466 u32 fd_flush_cnt;
467 u32 fd_add_err;
468 u32 fd_atr_cnt;
469
470 /* Book-keeping of side-band filter count per flow-type.
471 * This is used to detect and handle input set changes for
472 * respective flow-type.
473 */
474 u16 fd_tcp4_filter_cnt;
475 u16 fd_udp4_filter_cnt;
476 u16 fd_sctp4_filter_cnt;
477 u16 fd_ip4_filter_cnt;
478
479 /* Flexible filter table values that need to be programmed into
480 * hardware, which expects L3 and L4 to be programmed separately. We
481 * need to ensure that the values are in ascended order and don't have
482 * duplicates, so we track each L3 and L4 values in separate lists.
483 */
484 struct list_head l3_flex_pit_list;
485 struct list_head l4_flex_pit_list;
486
487 struct udp_tunnel_nic_shared udp_tunnel_shared;
488 struct udp_tunnel_nic_info udp_tunnel_nic;
489
490 struct hlist_head cloud_filter_list;
491 u16 num_cloud_filters;
492
493 enum i40e_interrupt_policy int_policy;
494 u16 rx_itr_default;
495 u16 tx_itr_default;
496 u32 msg_enable;
497 char int_name[I40E_INT_NAME_STR_LEN];
498 u16 adminq_work_limit; /* num of admin receive queue desc to process */
499 unsigned long service_timer_period;
500 unsigned long service_timer_previous;
501 struct timer_list service_timer;
502 struct work_struct service_task;
503
504 u32 hw_features;
505 #define I40E_HW_RSS_AQ_CAPABLE BIT(0)
506 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
507 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
508 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
509 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
510 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
511 #define I40E_HW_100M_SGMII_CAPABLE BIT(6)
512 #define I40E_HW_NO_DCB_SUPPORT BIT(7)
513 #define I40E_HW_USE_SET_LLDP_MIB BIT(8)
514 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
515 #define I40E_HW_PTP_L4_CAPABLE BIT(10)
516 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
517 #define I40E_HW_HAVE_CRT_RETIMER BIT(13)
518 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
519 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
520 #define I40E_HW_STOP_FW_LLDP BIT(16)
521 #define I40E_HW_PORT_ID_VALID BIT(17)
522 #define I40E_HW_RESTART_AUTONEG BIT(18)
523
524 u32 flags;
525 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
526 #define I40E_FLAG_MSI_ENABLED BIT(1)
527 #define I40E_FLAG_MSIX_ENABLED BIT(2)
528 #define I40E_FLAG_RSS_ENABLED BIT(3)
529 #define I40E_FLAG_VMDQ_ENABLED BIT(4)
530 #define I40E_FLAG_SRIOV_ENABLED BIT(5)
531 #define I40E_FLAG_DCB_CAPABLE BIT(6)
532 #define I40E_FLAG_DCB_ENABLED BIT(7)
533 #define I40E_FLAG_FD_SB_ENABLED BIT(8)
534 #define I40E_FLAG_FD_ATR_ENABLED BIT(9)
535 #define I40E_FLAG_MFP_ENABLED BIT(10)
536 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
537 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
538 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
539 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
540 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
541 #define I40E_FLAG_LEGACY_RX BIT(16)
542 #define I40E_FLAG_PTP BIT(17)
543 #define I40E_FLAG_IWARP_ENABLED BIT(18)
544 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
545 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
546 #define I40E_FLAG_TC_MQPRIO BIT(21)
547 #define I40E_FLAG_FD_SB_INACTIVE BIT(22)
548 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
549 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
550 #define I40E_FLAG_RS_FEC BIT(25)
551 #define I40E_FLAG_BASE_R_FEC BIT(26)
552 /* TOTAL_PORT_SHUTDOWN
553 * Allows to physically disable the link on the NIC's port.
554 * If enabled, (after link down request from the OS)
555 * no link, traffic or led activity is possible on that port.
556 *
557 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the
558 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true
559 * and cannot be disabled by system admin at that time.
560 * The functionalities are exclusive in terms of configuration, but they also
561 * have similar behavior (allowing to disable physical link of the port),
562 * with following differences:
563 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is
564 * supported by whole family of 7xx Intel Ethernet Controllers
565 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS)
566 * only if motherboard's BIOS and NIC's FW has support of it
567 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down
568 * by sending phy_type=0 to NIC's FW
569 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead
570 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK)
571 * in abilities field of i40e_aq_set_phy_config structure
572 */
573 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27)
574
575 struct i40e_client_instance *cinst;
576 bool stat_offsets_loaded;
577 struct i40e_hw_port_stats stats;
578 struct i40e_hw_port_stats stats_offsets;
579 u32 tx_timeout_count;
580 u32 tx_timeout_recovery_level;
581 unsigned long tx_timeout_last_recovery;
582 u32 tx_sluggish_count;
583 u32 hw_csum_rx_error;
584 u32 led_status;
585 u16 corer_count; /* Core reset count */
586 u16 globr_count; /* Global reset count */
587 u16 empr_count; /* EMP reset count */
588 u16 pfr_count; /* PF reset count */
589 u16 sw_int_count; /* SW interrupt count */
590
591 struct mutex switch_mutex;
592 u16 lan_vsi; /* our default LAN VSI */
593 u16 lan_veb; /* initial relay, if exists */
594 #define I40E_NO_VEB 0xffff
595 #define I40E_NO_VSI 0xffff
596 u16 next_vsi; /* Next unallocated VSI - 0-based! */
597 struct i40e_vsi **vsi;
598 struct i40e_veb *veb[I40E_MAX_VEB];
599
600 struct i40e_lump_tracking *qp_pile;
601 struct i40e_lump_tracking *irq_pile;
602
603 /* switch config info */
604 u16 pf_seid;
605 u16 main_vsi_seid;
606 u16 mac_seid;
607 struct kobject *switch_kobj;
608 #ifdef CONFIG_DEBUG_FS
609 struct dentry *i40e_dbg_pf;
610 #endif /* CONFIG_DEBUG_FS */
611 bool cur_promisc;
612
613 u16 instance; /* A unique number per i40e_pf instance in the system */
614
615 /* sr-iov config info */
616 struct i40e_vf *vf;
617 int num_alloc_vfs; /* actual number of VFs allocated */
618 u32 vf_aq_requests;
619 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
620
621 /* DCBx/DCBNL capability for PF that indicates
622 * whether DCBx is managed by firmware or host
623 * based agent (LLDPAD). Also, indicates what
624 * flavor of DCBx protocol (IEEE/CEE) is supported
625 * by the device. For now we're supporting IEEE
626 * mode only.
627 */
628 u16 dcbx_cap;
629
630 struct i40e_filter_control_settings filter_settings;
631
632 struct ptp_clock *ptp_clock;
633 struct ptp_clock_info ptp_caps;
634 struct sk_buff *ptp_tx_skb;
635 unsigned long ptp_tx_start;
636 struct hwtstamp_config tstamp_config;
637 struct timespec64 ptp_prev_hw_time;
638 ktime_t ptp_reset_start;
639 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
640 u32 ptp_adj_mult;
641 u32 tx_hwtstamp_timeouts;
642 u32 tx_hwtstamp_skipped;
643 u32 rx_hwtstamp_cleared;
644 u32 latch_event_flags;
645 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
646 unsigned long latch_events[4];
647 bool ptp_tx;
648 bool ptp_rx;
649 u16 rss_table_size; /* HW RSS table size */
650 u32 max_bw;
651 u32 min_bw;
652
653 u32 ioremap_len;
654 u32 fd_inv;
655 u16 phy_led_val;
656
657 u16 override_q_count;
658 u16 last_sw_conf_flags;
659 u16 last_sw_conf_valid_flags;
660 /* List to keep previous DDP profiles to be rolled back in the future */
661 struct list_head ddp_old_prof;
662 };
663
664 /**
665 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
666 * @macaddr: the MAC Address as the base key
667 *
668 * Simply copies the address and returns it as a u64 for hashing
669 **/
i40e_addr_to_hkey(const u8 * macaddr)670 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
671 {
672 u64 key = 0;
673
674 ether_addr_copy((u8 *)&key, macaddr);
675 return key;
676 }
677
678 enum i40e_filter_state {
679 I40E_FILTER_INVALID = 0, /* Invalid state */
680 I40E_FILTER_NEW, /* New, not sent to FW yet */
681 I40E_FILTER_ACTIVE, /* Added to switch by FW */
682 I40E_FILTER_FAILED, /* Rejected by FW */
683 I40E_FILTER_REMOVE, /* To be removed */
684 /* There is no 'removed' state; the filter struct is freed */
685 };
686 struct i40e_mac_filter {
687 struct hlist_node hlist;
688 u8 macaddr[ETH_ALEN];
689 #define I40E_VLAN_ANY -1
690 s16 vlan;
691 enum i40e_filter_state state;
692 };
693
694 /* Wrapper structure to keep track of filters while we are preparing to send
695 * firmware commands. We cannot send firmware commands while holding a
696 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
697 * a separate structure, which will track the state change and update the real
698 * filter while under lock. We can't simply hold the filters in a separate
699 * list, as this opens a window for a race condition when adding new MAC
700 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
701 */
702 struct i40e_new_mac_filter {
703 struct hlist_node hlist;
704 struct i40e_mac_filter *f;
705
706 /* Track future changes to state separately */
707 enum i40e_filter_state state;
708 };
709
710 struct i40e_veb {
711 struct i40e_pf *pf;
712 u16 idx;
713 u16 veb_idx; /* index of VEB parent */
714 u16 seid;
715 u16 uplink_seid;
716 u16 stats_idx; /* index of VEB parent */
717 u8 enabled_tc;
718 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
719 u16 flags;
720 u16 bw_limit;
721 u8 bw_max_quanta;
722 bool is_abs_credits;
723 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
724 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
725 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
726 struct kobject *kobj;
727 bool stat_offsets_loaded;
728 struct i40e_eth_stats stats;
729 struct i40e_eth_stats stats_offsets;
730 struct i40e_veb_tc_stats tc_stats;
731 struct i40e_veb_tc_stats tc_stats_offsets;
732 };
733
734 /* struct that defines a VSI, associated with a dev */
735 struct i40e_vsi {
736 struct net_device *netdev;
737 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
738 bool netdev_registered;
739 bool stat_offsets_loaded;
740
741 u32 current_netdev_flags;
742 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
743 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
744 #define I40E_VSI_FLAG_VEB_OWNER BIT(1)
745 unsigned long flags;
746
747 /* Per VSI lock to protect elements/hash (MAC filter) */
748 spinlock_t mac_filter_hash_lock;
749 /* Fixed size hash table with 2^8 buckets for MAC filters */
750 DECLARE_HASHTABLE(mac_filter_hash, 8);
751 bool has_vlan_filter;
752
753 /* VSI stats */
754 struct rtnl_link_stats64 net_stats;
755 struct rtnl_link_stats64 net_stats_offsets;
756 struct i40e_eth_stats eth_stats;
757 struct i40e_eth_stats eth_stats_offsets;
758 u64 tx_restart;
759 u64 tx_busy;
760 u64 tx_linearize;
761 u64 tx_force_wb;
762 u64 rx_buf_failed;
763 u64 rx_page_failed;
764
765 /* These are containers of ring pointers, allocated at run-time */
766 struct i40e_ring **rx_rings;
767 struct i40e_ring **tx_rings;
768 struct i40e_ring **xdp_rings; /* XDP Tx rings */
769
770 u32 active_filters;
771 u32 promisc_threshold;
772
773 u16 work_limit;
774 u16 int_rate_limit; /* value in usecs */
775
776 u16 rss_table_size; /* HW RSS table size */
777 u16 rss_size; /* Allocated RSS queues */
778 u8 *rss_hkey_user; /* User configured hash keys */
779 u8 *rss_lut_user; /* User configured lookup table entries */
780
781
782 u16 max_frame;
783 u16 rx_buf_len;
784
785 struct bpf_prog *xdp_prog;
786
787 /* List of q_vectors allocated to this VSI */
788 struct i40e_q_vector **q_vectors;
789 int num_q_vectors;
790 int base_vector;
791 bool irqs_ready;
792
793 u16 seid; /* HW index of this VSI (absolute index) */
794 u16 id; /* VSI number */
795 u16 uplink_seid;
796
797 u16 base_queue; /* vsi's first queue in hw array */
798 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
799 u16 req_queue_pairs; /* User requested queue pairs */
800 u16 num_queue_pairs; /* Used tx and rx pairs */
801 u16 num_tx_desc;
802 u16 num_rx_desc;
803 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
804 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
805
806 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
807 struct i40e_tc_configuration tc_config;
808 struct i40e_aqc_vsi_properties_data info;
809
810 /* VSI BW limit (absolute across all TCs) */
811 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
812 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
813
814 /* Relative TC credits across VSIs */
815 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
816 /* TC BW limit credits within VSI */
817 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
818 /* TC BW limit max quanta within VSI */
819 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
820
821 struct i40e_pf *back; /* Backreference to associated PF */
822 u16 idx; /* index in pf->vsi[] */
823 u16 veb_idx; /* index of VEB parent */
824 struct kobject *kobj; /* sysfs object */
825 bool current_isup; /* Sync 'link up' logging */
826 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
827
828 /* channel specific fields */
829 u16 cnt_q_avail; /* num of queues available for channel usage */
830 u16 orig_rss_size;
831 u16 current_rss_size;
832 bool reconfig_rss;
833
834 u16 next_base_queue; /* next queue to be used for channel setup */
835
836 struct list_head ch_list;
837 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
838
839 /* macvlan fields */
840 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */
841 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */
842 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
843 struct list_head macvlan_list;
844 int macvlan_cnt;
845
846 void *priv; /* client driver data reference. */
847
848 /* VSI specific handlers */
849 irqreturn_t (*irq_handler)(int irq, void *data);
850
851 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
852 } ____cacheline_internodealigned_in_smp;
853
854 struct i40e_netdev_priv {
855 struct i40e_vsi *vsi;
856 };
857
858 /* struct that defines an interrupt vector */
859 struct i40e_q_vector {
860 struct i40e_vsi *vsi;
861
862 u16 v_idx; /* index in the vsi->q_vector array. */
863 u16 reg_idx; /* register index of the interrupt */
864
865 struct napi_struct napi;
866
867 struct i40e_ring_container rx;
868 struct i40e_ring_container tx;
869
870 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
871 u8 num_ringpairs; /* total number of ring pairs in vector */
872
873 cpumask_t affinity_mask;
874 struct irq_affinity_notify affinity_notify;
875
876 struct rcu_head rcu; /* to avoid race with update stats on free */
877 char name[I40E_INT_NAME_STR_LEN];
878 bool arm_wb_state;
879 } ____cacheline_internodealigned_in_smp;
880
881 /* lan device */
882 struct i40e_device {
883 struct list_head list;
884 struct i40e_pf *pf;
885 };
886
887 /**
888 * i40e_nvm_version_str - format the NVM version strings
889 * @hw: ptr to the hardware info
890 **/
i40e_nvm_version_str(struct i40e_hw * hw)891 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
892 {
893 static char buf[32];
894 u32 full_ver;
895
896 full_ver = hw->nvm.oem_ver;
897
898 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
899 u8 gen, snap;
900 u16 release;
901
902 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
903 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
904 I40E_OEM_SNAP_SHIFT);
905 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
906
907 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
908 } else {
909 u8 ver, patch;
910 u16 build;
911
912 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
913 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
914 I40E_OEM_VER_BUILD_MASK);
915 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
916
917 snprintf(buf, sizeof(buf),
918 "%x.%02x 0x%x %d.%d.%d",
919 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
920 I40E_NVM_VERSION_HI_SHIFT,
921 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
922 I40E_NVM_VERSION_LO_SHIFT,
923 hw->nvm.eetrack, ver, build, patch);
924 }
925
926 return buf;
927 }
928
929 /**
930 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
931 * @netdev: the corresponding netdev
932 *
933 * Return the PF struct for the given netdev
934 **/
i40e_netdev_to_pf(struct net_device * netdev)935 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
936 {
937 struct i40e_netdev_priv *np = netdev_priv(netdev);
938 struct i40e_vsi *vsi = np->vsi;
939
940 return vsi->back;
941 }
942
i40e_vsi_setup_irqhandler(struct i40e_vsi * vsi,irqreturn_t (* irq_handler)(int,void *))943 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
944 irqreturn_t (*irq_handler)(int, void *))
945 {
946 vsi->irq_handler = irq_handler;
947 }
948
949 /**
950 * i40e_get_fd_cnt_all - get the total FD filter space available
951 * @pf: pointer to the PF struct
952 **/
i40e_get_fd_cnt_all(struct i40e_pf * pf)953 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
954 {
955 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
956 }
957
958 /**
959 * i40e_read_fd_input_set - reads value of flow director input set register
960 * @pf: pointer to the PF struct
961 * @addr: register addr
962 *
963 * This function reads value of flow director input set register
964 * specified by 'addr' (which is specific to flow-type)
965 **/
i40e_read_fd_input_set(struct i40e_pf * pf,u16 addr)966 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
967 {
968 u64 val;
969
970 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
971 val <<= 32;
972 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
973
974 return val;
975 }
976
977 /**
978 * i40e_write_fd_input_set - writes value into flow director input set register
979 * @pf: pointer to the PF struct
980 * @addr: register addr
981 * @val: value to be written
982 *
983 * This function writes specified value to the register specified by 'addr'.
984 * This register is input set register based on flow-type.
985 **/
i40e_write_fd_input_set(struct i40e_pf * pf,u16 addr,u64 val)986 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
987 u16 addr, u64 val)
988 {
989 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
990 (u32)(val >> 32));
991 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
992 (u32)(val & 0xFFFFFFFFULL));
993 }
994
995 /**
996 * i40e_get_pf_count - get PCI PF count.
997 * @hw: pointer to a hw.
998 *
999 * Reports the function number of the highest PCI physical
1000 * function plus 1 as it is loaded from the NVM.
1001 *
1002 * Return: PCI PF count.
1003 **/
i40e_get_pf_count(struct i40e_hw * hw)1004 static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
1005 {
1006 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
1007 rd32(hw, I40E_GLGEN_PCIFCNCNT));
1008 }
1009
1010 /* needed by i40e_ethtool.c */
1011 int i40e_up(struct i40e_vsi *vsi);
1012 void i40e_down(struct i40e_vsi *vsi);
1013 extern const char i40e_driver_name[];
1014 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1015 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1016 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1017 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1018 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1019 u16 rss_table_size, u16 rss_size);
1020 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1021 /**
1022 * i40e_find_vsi_by_type - Find and return Flow Director VSI
1023 * @pf: PF to search for VSI
1024 * @type: Value indicating type of VSI we are looking for
1025 **/
1026 static inline struct i40e_vsi *
i40e_find_vsi_by_type(struct i40e_pf * pf,u16 type)1027 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1028 {
1029 int i;
1030
1031 for (i = 0; i < pf->num_alloc_vsi; i++) {
1032 struct i40e_vsi *vsi = pf->vsi[i];
1033
1034 if (vsi && vsi->type == type)
1035 return vsi;
1036 }
1037
1038 return NULL;
1039 }
1040 void i40e_update_stats(struct i40e_vsi *vsi);
1041 void i40e_update_veb_stats(struct i40e_veb *veb);
1042 void i40e_update_eth_stats(struct i40e_vsi *vsi);
1043 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1044 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1045 bool printconfig);
1046
1047 int i40e_add_del_fdir(struct i40e_vsi *vsi,
1048 struct i40e_fdir_filter *input, bool add);
1049 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1050 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1051 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1052 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1053 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1054 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1055 void i40e_set_ethtool_ops(struct net_device *netdev);
1056 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1057 const u8 *macaddr, s16 vlan);
1058 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1059 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1060 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1061 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1062 u16 uplink, u32 param1);
1063 int i40e_vsi_release(struct i40e_vsi *vsi);
1064 void i40e_service_event_schedule(struct i40e_pf *pf);
1065 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1066 u8 *msg, u16 len);
1067
1068 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1069 bool enable);
1070 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1071 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1072 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1073 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1074 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1075 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1076 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1077 u16 downlink_seid, u8 enabled_tc);
1078 void i40e_veb_release(struct i40e_veb *veb);
1079
1080 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1081 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1082 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1083 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1084 void i40e_pf_reset_stats(struct i40e_pf *pf);
1085 #ifdef CONFIG_DEBUG_FS
1086 void i40e_dbg_pf_init(struct i40e_pf *pf);
1087 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1088 void i40e_dbg_init(void);
1089 void i40e_dbg_exit(void);
1090 #else
i40e_dbg_pf_init(struct i40e_pf * pf)1091 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
i40e_dbg_pf_exit(struct i40e_pf * pf)1092 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
i40e_dbg_init(void)1093 static inline void i40e_dbg_init(void) {}
i40e_dbg_exit(void)1094 static inline void i40e_dbg_exit(void) {}
1095 #endif /* CONFIG_DEBUG_FS*/
1096 /* needed by client drivers */
1097 int i40e_lan_add_device(struct i40e_pf *pf);
1098 int i40e_lan_del_device(struct i40e_pf *pf);
1099 void i40e_client_subtask(struct i40e_pf *pf);
1100 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1101 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1102 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1103 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1104 void i40e_client_update_msix_info(struct i40e_pf *pf);
1105 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1106 /**
1107 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1108 * @vsi: pointer to a vsi
1109 * @vector: enable a particular Hw Interrupt vector, without base_vector
1110 **/
i40e_irq_dynamic_enable(struct i40e_vsi * vsi,int vector)1111 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1112 {
1113 struct i40e_pf *pf = vsi->back;
1114 struct i40e_hw *hw = &pf->hw;
1115 u32 val;
1116
1117 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1118 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1119 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1120 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1121 /* skip the flush */
1122 }
1123
1124 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1125 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1126 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1127 int i40e_open(struct net_device *netdev);
1128 int i40e_close(struct net_device *netdev);
1129 int i40e_vsi_open(struct i40e_vsi *vsi);
1130 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1131 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1132 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1133 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1134 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1135 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1136 const u8 *macaddr);
1137 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1138 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1139 int i40e_count_filters(struct i40e_vsi *vsi);
1140 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1141 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1142 #ifdef CONFIG_I40E_DCB
1143 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1144 struct i40e_dcbx_config *old_cfg,
1145 struct i40e_dcbx_config *new_cfg);
1146 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1147 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1148 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1149 struct i40e_dcbx_config *old_cfg,
1150 struct i40e_dcbx_config *new_cfg);
1151 #endif /* CONFIG_I40E_DCB */
1152 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1153 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1154 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1155 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1156 void i40e_ptp_set_increment(struct i40e_pf *pf);
1157 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1158 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1159 void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1160 void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1161 void i40e_ptp_init(struct i40e_pf *pf);
1162 void i40e_ptp_stop(struct i40e_pf *pf);
1163 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1164 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1165 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1166 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1167 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1168 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1169
1170 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1171
i40e_enabled_xdp_vsi(struct i40e_vsi * vsi)1172 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1173 {
1174 return !!READ_ONCE(vsi->xdp_prog);
1175 }
1176
1177 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1178 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1179 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1180 struct i40e_cloud_filter *filter,
1181 bool add);
1182 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1183 struct i40e_cloud_filter *filter,
1184 bool add);
1185 #endif /* _I40E_H_ */
1186