1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9 */
10
11 #include <linux/acpi.h>
12 #include <linux/bcd.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/rtc/ds1307.h>
18 #include <linux/rtc.h>
19 #include <linux/slab.h>
20 #include <linux/string.h>
21 #include <linux/hwmon.h>
22 #include <linux/hwmon-sysfs.h>
23 #include <linux/clk-provider.h>
24 #include <linux/regmap.h>
25 #include <linux/watchdog.h>
26
27 /*
28 * We can't determine type by probing, but if we expect pre-Linux code
29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
32 */
33 enum ds_type {
34 ds_1307,
35 ds_1308,
36 ds_1337,
37 ds_1338,
38 ds_1339,
39 ds_1340,
40 ds_1341,
41 ds_1388,
42 ds_3231,
43 m41t0,
44 m41t00,
45 m41t11,
46 mcp794xx,
47 rx_8025,
48 rx_8130,
49 last_ds_type /* always last */
50 /* rs5c372 too? different address... */
51 };
52
53 /* RTC registers don't differ much, except for the century flag */
54 #define DS1307_REG_SECS 0x00 /* 00-59 */
55 # define DS1307_BIT_CH 0x80
56 # define DS1340_BIT_nEOSC 0x80
57 # define MCP794XX_BIT_ST 0x80
58 #define DS1307_REG_MIN 0x01 /* 00-59 */
59 # define M41T0_BIT_OF 0x80
60 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
61 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
62 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
63 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
64 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
65 #define DS1307_REG_WDAY 0x03 /* 01-07 */
66 # define MCP794XX_BIT_VBATEN 0x08
67 #define DS1307_REG_MDAY 0x04 /* 01-31 */
68 #define DS1307_REG_MONTH 0x05 /* 01-12 */
69 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
70 #define DS1307_REG_YEAR 0x06 /* 00-99 */
71
72 /*
73 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
74 * start at 7, and they differ a LOT. Only control and status matter for
75 * basic RTC date and time functionality; be careful using them.
76 */
77 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
78 # define DS1307_BIT_OUT 0x80
79 # define DS1338_BIT_OSF 0x20
80 # define DS1307_BIT_SQWE 0x10
81 # define DS1307_BIT_RS1 0x02
82 # define DS1307_BIT_RS0 0x01
83 #define DS1337_REG_CONTROL 0x0e
84 # define DS1337_BIT_nEOSC 0x80
85 # define DS1339_BIT_BBSQI 0x20
86 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
87 # define DS1337_BIT_RS2 0x10
88 # define DS1337_BIT_RS1 0x08
89 # define DS1337_BIT_INTCN 0x04
90 # define DS1337_BIT_A2IE 0x02
91 # define DS1337_BIT_A1IE 0x01
92 #define DS1340_REG_CONTROL 0x07
93 # define DS1340_BIT_OUT 0x80
94 # define DS1340_BIT_FT 0x40
95 # define DS1340_BIT_CALIB_SIGN 0x20
96 # define DS1340_M_CALIBRATION 0x1f
97 #define DS1340_REG_FLAG 0x09
98 # define DS1340_BIT_OSF 0x80
99 #define DS1337_REG_STATUS 0x0f
100 # define DS1337_BIT_OSF 0x80
101 # define DS3231_BIT_EN32KHZ 0x08
102 # define DS1337_BIT_A2I 0x02
103 # define DS1337_BIT_A1I 0x01
104 #define DS1339_REG_ALARM1_SECS 0x07
105
106 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
107
108 #define RX8025_REG_CTRL1 0x0e
109 # define RX8025_BIT_2412 0x20
110 #define RX8025_REG_CTRL2 0x0f
111 # define RX8025_BIT_PON 0x10
112 # define RX8025_BIT_VDET 0x40
113 # define RX8025_BIT_XST 0x20
114
115 #define RX8130_REG_ALARM_MIN 0x17
116 #define RX8130_REG_ALARM_HOUR 0x18
117 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
118 #define RX8130_REG_EXTENSION 0x1c
119 #define RX8130_REG_EXTENSION_WADA BIT(3)
120 #define RX8130_REG_FLAG 0x1d
121 #define RX8130_REG_FLAG_VLF BIT(1)
122 #define RX8130_REG_FLAG_AF BIT(3)
123 #define RX8130_REG_CONTROL0 0x1e
124 #define RX8130_REG_CONTROL0_AIE BIT(3)
125 #define RX8130_REG_CONTROL1 0x1f
126 #define RX8130_REG_CONTROL1_INIEN BIT(4)
127 #define RX8130_REG_CONTROL1_CHGEN BIT(5)
128
129 #define MCP794XX_REG_CONTROL 0x07
130 # define MCP794XX_BIT_ALM0_EN 0x10
131 # define MCP794XX_BIT_ALM1_EN 0x20
132 #define MCP794XX_REG_ALARM0_BASE 0x0a
133 #define MCP794XX_REG_ALARM0_CTRL 0x0d
134 #define MCP794XX_REG_ALARM1_BASE 0x11
135 #define MCP794XX_REG_ALARM1_CTRL 0x14
136 # define MCP794XX_BIT_ALMX_IF BIT(3)
137 # define MCP794XX_BIT_ALMX_C0 BIT(4)
138 # define MCP794XX_BIT_ALMX_C1 BIT(5)
139 # define MCP794XX_BIT_ALMX_C2 BIT(6)
140 # define MCP794XX_BIT_ALMX_POL BIT(7)
141 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
142 MCP794XX_BIT_ALMX_C1 | \
143 MCP794XX_BIT_ALMX_C2)
144
145 #define M41TXX_REG_CONTROL 0x07
146 # define M41TXX_BIT_OUT BIT(7)
147 # define M41TXX_BIT_FT BIT(6)
148 # define M41TXX_BIT_CALIB_SIGN BIT(5)
149 # define M41TXX_M_CALIBRATION GENMASK(4, 0)
150
151 #define DS1388_REG_WDOG_HUN_SECS 0x08
152 #define DS1388_REG_WDOG_SECS 0x09
153 #define DS1388_REG_FLAG 0x0b
154 # define DS1388_BIT_WF BIT(6)
155 # define DS1388_BIT_OSF BIT(7)
156 #define DS1388_REG_CONTROL 0x0c
157 # define DS1388_BIT_RST BIT(0)
158 # define DS1388_BIT_WDE BIT(1)
159 # define DS1388_BIT_nEOSC BIT(7)
160
161 /* negative offset step is -2.034ppm */
162 #define M41TXX_NEG_OFFSET_STEP_PPB 2034
163 /* positive offset step is +4.068ppm */
164 #define M41TXX_POS_OFFSET_STEP_PPB 4068
165 /* Min and max values supported with 'offset' interface by M41TXX */
166 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
167 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
168
169 struct ds1307 {
170 enum ds_type type;
171 unsigned long flags;
172 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
173 #define HAS_ALARM 1 /* bit 1 == irq claimed */
174 struct device *dev;
175 struct regmap *regmap;
176 const char *name;
177 struct rtc_device *rtc;
178 #ifdef CONFIG_COMMON_CLK
179 struct clk_hw clks[2];
180 #endif
181 };
182
183 struct chip_desc {
184 unsigned alarm:1;
185 u16 nvram_offset;
186 u16 nvram_size;
187 u8 offset; /* register's offset */
188 u8 century_reg;
189 u8 century_enable_bit;
190 u8 century_bit;
191 u8 bbsqi_bit;
192 irq_handler_t irq_handler;
193 const struct rtc_class_ops *rtc_ops;
194 u16 trickle_charger_reg;
195 u8 (*do_trickle_setup)(struct ds1307 *, u32,
196 bool);
197 /* Does the RTC require trickle-resistor-ohms to select the value of
198 * the resistor between Vcc and Vbackup?
199 */
200 bool requires_trickle_resistor;
201 /* Some RTC's batteries and supercaps were charged by default, others
202 * allow charging but were not configured previously to do so.
203 * Remember this behavior to stay backwards compatible.
204 */
205 bool charge_default;
206 };
207
208 static const struct chip_desc chips[last_ds_type];
209
ds1307_get_time(struct device * dev,struct rtc_time * t)210 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
211 {
212 struct ds1307 *ds1307 = dev_get_drvdata(dev);
213 int tmp, ret;
214 const struct chip_desc *chip = &chips[ds1307->type];
215 u8 regs[7];
216
217 if (ds1307->type == rx_8130) {
218 unsigned int regflag;
219 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag);
220 if (ret) {
221 dev_err(dev, "%s error %d\n", "read", ret);
222 return ret;
223 }
224
225 if (regflag & RX8130_REG_FLAG_VLF) {
226 dev_warn_once(dev, "oscillator failed, set time!\n");
227 return -EINVAL;
228 }
229 }
230
231 /* read the RTC date and time registers all at once */
232 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
233 sizeof(regs));
234 if (ret) {
235 dev_err(dev, "%s error %d\n", "read", ret);
236 return ret;
237 }
238
239 dev_dbg(dev, "%s: %7ph\n", "read", regs);
240
241 /* if oscillator fail bit is set, no data can be trusted */
242 if (ds1307->type == m41t0 &&
243 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
244 dev_warn_once(dev, "oscillator failed, set time!\n");
245 return -EINVAL;
246 }
247
248 tmp = regs[DS1307_REG_SECS];
249 switch (ds1307->type) {
250 case ds_1307:
251 case m41t0:
252 case m41t00:
253 case m41t11:
254 if (tmp & DS1307_BIT_CH)
255 return -EINVAL;
256 break;
257 case ds_1308:
258 case ds_1338:
259 if (tmp & DS1307_BIT_CH)
260 return -EINVAL;
261
262 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
263 if (ret)
264 return ret;
265 if (tmp & DS1338_BIT_OSF)
266 return -EINVAL;
267 break;
268 case ds_1340:
269 if (tmp & DS1340_BIT_nEOSC)
270 return -EINVAL;
271
272 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
273 if (ret)
274 return ret;
275 if (tmp & DS1340_BIT_OSF)
276 return -EINVAL;
277 break;
278 case ds_1388:
279 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
280 if (ret)
281 return ret;
282 if (tmp & DS1388_BIT_OSF)
283 return -EINVAL;
284 break;
285 case mcp794xx:
286 if (!(tmp & MCP794XX_BIT_ST))
287 return -EINVAL;
288
289 break;
290 default:
291 break;
292 }
293
294 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
295 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
296 tmp = regs[DS1307_REG_HOUR] & 0x3f;
297 t->tm_hour = bcd2bin(tmp);
298 /* rx8130 is bit position, not BCD */
299 if (ds1307->type == rx_8130)
300 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
301 else
302 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
303 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
304 tmp = regs[DS1307_REG_MONTH] & 0x1f;
305 t->tm_mon = bcd2bin(tmp) - 1;
306 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
307
308 if (regs[chip->century_reg] & chip->century_bit &&
309 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
310 t->tm_year += 100;
311
312 dev_dbg(dev, "%s secs=%d, mins=%d, "
313 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
314 "read", t->tm_sec, t->tm_min,
315 t->tm_hour, t->tm_mday,
316 t->tm_mon, t->tm_year, t->tm_wday);
317
318 return 0;
319 }
320
ds1307_set_time(struct device * dev,struct rtc_time * t)321 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
322 {
323 struct ds1307 *ds1307 = dev_get_drvdata(dev);
324 const struct chip_desc *chip = &chips[ds1307->type];
325 int result;
326 int tmp;
327 u8 regs[7];
328
329 dev_dbg(dev, "%s secs=%d, mins=%d, "
330 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
331 "write", t->tm_sec, t->tm_min,
332 t->tm_hour, t->tm_mday,
333 t->tm_mon, t->tm_year, t->tm_wday);
334
335 if (t->tm_year < 100)
336 return -EINVAL;
337
338 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
339 if (t->tm_year > (chip->century_bit ? 299 : 199))
340 return -EINVAL;
341 #else
342 if (t->tm_year > 199)
343 return -EINVAL;
344 #endif
345
346 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
347 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
348 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
349 /* rx8130 is bit position, not BCD */
350 if (ds1307->type == rx_8130)
351 regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
352 else
353 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
354 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
355 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
356
357 /* assume 20YY not 19YY */
358 tmp = t->tm_year - 100;
359 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
360
361 if (chip->century_enable_bit)
362 regs[chip->century_reg] |= chip->century_enable_bit;
363 if (t->tm_year > 199 && chip->century_bit)
364 regs[chip->century_reg] |= chip->century_bit;
365
366 switch (ds1307->type) {
367 case ds_1308:
368 case ds_1338:
369 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
370 DS1338_BIT_OSF, 0);
371 break;
372 case ds_1340:
373 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
374 DS1340_BIT_OSF, 0);
375 break;
376 case ds_1388:
377 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
378 DS1388_BIT_OSF, 0);
379 break;
380 case mcp794xx:
381 /*
382 * these bits were cleared when preparing the date/time
383 * values and need to be set again before writing the
384 * regsfer out to the device.
385 */
386 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
387 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
388 break;
389 default:
390 break;
391 }
392
393 dev_dbg(dev, "%s: %7ph\n", "write", regs);
394
395 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
396 sizeof(regs));
397 if (result) {
398 dev_err(dev, "%s error %d\n", "write", result);
399 return result;
400 }
401
402 if (ds1307->type == rx_8130) {
403 /* clear Voltage Loss Flag as data is available now */
404 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
405 ~(u8)RX8130_REG_FLAG_VLF);
406 if (result) {
407 dev_err(dev, "%s error %d\n", "write", result);
408 return result;
409 }
410 }
411
412 return 0;
413 }
414
ds1337_read_alarm(struct device * dev,struct rtc_wkalrm * t)415 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
416 {
417 struct ds1307 *ds1307 = dev_get_drvdata(dev);
418 int ret;
419 u8 regs[9];
420
421 if (!test_bit(HAS_ALARM, &ds1307->flags))
422 return -EINVAL;
423
424 /* read all ALARM1, ALARM2, and status registers at once */
425 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
426 regs, sizeof(regs));
427 if (ret) {
428 dev_err(dev, "%s error %d\n", "alarm read", ret);
429 return ret;
430 }
431
432 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
433 ®s[0], ®s[4], ®s[7]);
434
435 /*
436 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
437 * and that all four fields are checked matches
438 */
439 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
440 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
441 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
442 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
443
444 /* ... and status */
445 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
446 t->pending = !!(regs[8] & DS1337_BIT_A1I);
447
448 dev_dbg(dev, "%s secs=%d, mins=%d, "
449 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
450 "alarm read", t->time.tm_sec, t->time.tm_min,
451 t->time.tm_hour, t->time.tm_mday,
452 t->enabled, t->pending);
453
454 return 0;
455 }
456
ds1337_set_alarm(struct device * dev,struct rtc_wkalrm * t)457 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
458 {
459 struct ds1307 *ds1307 = dev_get_drvdata(dev);
460 unsigned char regs[9];
461 u8 control, status;
462 int ret;
463
464 if (!test_bit(HAS_ALARM, &ds1307->flags))
465 return -EINVAL;
466
467 dev_dbg(dev, "%s secs=%d, mins=%d, "
468 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
469 "alarm set", t->time.tm_sec, t->time.tm_min,
470 t->time.tm_hour, t->time.tm_mday,
471 t->enabled, t->pending);
472
473 /* read current status of both alarms and the chip */
474 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
475 sizeof(regs));
476 if (ret) {
477 dev_err(dev, "%s error %d\n", "alarm write", ret);
478 return ret;
479 }
480 control = regs[7];
481 status = regs[8];
482
483 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
484 ®s[0], ®s[4], control, status);
485
486 /* set ALARM1, using 24 hour and day-of-month modes */
487 regs[0] = bin2bcd(t->time.tm_sec);
488 regs[1] = bin2bcd(t->time.tm_min);
489 regs[2] = bin2bcd(t->time.tm_hour);
490 regs[3] = bin2bcd(t->time.tm_mday);
491
492 /* set ALARM2 to non-garbage */
493 regs[4] = 0;
494 regs[5] = 0;
495 regs[6] = 0;
496
497 /* disable alarms */
498 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
499 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
500
501 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
502 sizeof(regs));
503 if (ret) {
504 dev_err(dev, "can't set alarm time\n");
505 return ret;
506 }
507
508 /* optionally enable ALARM1 */
509 if (t->enabled) {
510 dev_dbg(dev, "alarm IRQ armed\n");
511 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
512 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
513 }
514
515 return 0;
516 }
517
ds1307_alarm_irq_enable(struct device * dev,unsigned int enabled)518 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
519 {
520 struct ds1307 *ds1307 = dev_get_drvdata(dev);
521
522 if (!test_bit(HAS_ALARM, &ds1307->flags))
523 return -ENOTTY;
524
525 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
526 DS1337_BIT_A1IE,
527 enabled ? DS1337_BIT_A1IE : 0);
528 }
529
do_trickle_setup_ds1339(struct ds1307 * ds1307,u32 ohms,bool diode)530 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
531 {
532 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
533 DS1307_TRICKLE_CHARGER_NO_DIODE;
534
535 setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
536
537 switch (ohms) {
538 case 250:
539 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
540 break;
541 case 2000:
542 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
543 break;
544 case 4000:
545 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
546 break;
547 default:
548 dev_warn(ds1307->dev,
549 "Unsupported ohm value %u in dt\n", ohms);
550 return 0;
551 }
552 return setup;
553 }
554
do_trickle_setup_rx8130(struct ds1307 * ds1307,u32 ohms,bool diode)555 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
556 {
557 /* make sure that the backup battery is enabled */
558 u8 setup = RX8130_REG_CONTROL1_INIEN;
559 if (diode)
560 setup |= RX8130_REG_CONTROL1_CHGEN;
561
562 return setup;
563 }
564
rx8130_irq(int irq,void * dev_id)565 static irqreturn_t rx8130_irq(int irq, void *dev_id)
566 {
567 struct ds1307 *ds1307 = dev_id;
568 struct mutex *lock = &ds1307->rtc->ops_lock;
569 u8 ctl[3];
570 int ret;
571
572 mutex_lock(lock);
573
574 /* Read control registers. */
575 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
576 sizeof(ctl));
577 if (ret < 0)
578 goto out;
579 if (!(ctl[1] & RX8130_REG_FLAG_AF))
580 goto out;
581 ctl[1] &= ~RX8130_REG_FLAG_AF;
582 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
583
584 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
585 sizeof(ctl));
586 if (ret < 0)
587 goto out;
588
589 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
590
591 out:
592 mutex_unlock(lock);
593
594 return IRQ_HANDLED;
595 }
596
rx8130_read_alarm(struct device * dev,struct rtc_wkalrm * t)597 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
598 {
599 struct ds1307 *ds1307 = dev_get_drvdata(dev);
600 u8 ald[3], ctl[3];
601 int ret;
602
603 if (!test_bit(HAS_ALARM, &ds1307->flags))
604 return -EINVAL;
605
606 /* Read alarm registers. */
607 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
608 sizeof(ald));
609 if (ret < 0)
610 return ret;
611
612 /* Read control registers. */
613 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
614 sizeof(ctl));
615 if (ret < 0)
616 return ret;
617
618 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
619 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
620
621 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
622 t->time.tm_sec = -1;
623 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
624 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
625 t->time.tm_wday = -1;
626 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
627 t->time.tm_mon = -1;
628 t->time.tm_year = -1;
629 t->time.tm_yday = -1;
630 t->time.tm_isdst = -1;
631
632 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
633 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
634 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
635
636 return 0;
637 }
638
rx8130_set_alarm(struct device * dev,struct rtc_wkalrm * t)639 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
640 {
641 struct ds1307 *ds1307 = dev_get_drvdata(dev);
642 u8 ald[3], ctl[3];
643 int ret;
644
645 if (!test_bit(HAS_ALARM, &ds1307->flags))
646 return -EINVAL;
647
648 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
649 "enabled=%d pending=%d\n", __func__,
650 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
651 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
652 t->enabled, t->pending);
653
654 /* Read control registers. */
655 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
656 sizeof(ctl));
657 if (ret < 0)
658 return ret;
659
660 ctl[0] &= RX8130_REG_EXTENSION_WADA;
661 ctl[1] &= ~RX8130_REG_FLAG_AF;
662 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
663
664 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
665 sizeof(ctl));
666 if (ret < 0)
667 return ret;
668
669 /* Hardware alarm precision is 1 minute! */
670 ald[0] = bin2bcd(t->time.tm_min);
671 ald[1] = bin2bcd(t->time.tm_hour);
672 ald[2] = bin2bcd(t->time.tm_mday);
673
674 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
675 sizeof(ald));
676 if (ret < 0)
677 return ret;
678
679 if (!t->enabled)
680 return 0;
681
682 ctl[2] |= RX8130_REG_CONTROL0_AIE;
683
684 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
685 }
686
rx8130_alarm_irq_enable(struct device * dev,unsigned int enabled)687 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
688 {
689 struct ds1307 *ds1307 = dev_get_drvdata(dev);
690 int ret, reg;
691
692 if (!test_bit(HAS_ALARM, &ds1307->flags))
693 return -EINVAL;
694
695 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
696 if (ret < 0)
697 return ret;
698
699 if (enabled)
700 reg |= RX8130_REG_CONTROL0_AIE;
701 else
702 reg &= ~RX8130_REG_CONTROL0_AIE;
703
704 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
705 }
706
mcp794xx_irq(int irq,void * dev_id)707 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
708 {
709 struct ds1307 *ds1307 = dev_id;
710 struct mutex *lock = &ds1307->rtc->ops_lock;
711 int reg, ret;
712
713 mutex_lock(lock);
714
715 /* Check and clear alarm 0 interrupt flag. */
716 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
717 if (ret)
718 goto out;
719 if (!(reg & MCP794XX_BIT_ALMX_IF))
720 goto out;
721 reg &= ~MCP794XX_BIT_ALMX_IF;
722 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
723 if (ret)
724 goto out;
725
726 /* Disable alarm 0. */
727 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
728 MCP794XX_BIT_ALM0_EN, 0);
729 if (ret)
730 goto out;
731
732 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
733
734 out:
735 mutex_unlock(lock);
736
737 return IRQ_HANDLED;
738 }
739
mcp794xx_read_alarm(struct device * dev,struct rtc_wkalrm * t)740 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
741 {
742 struct ds1307 *ds1307 = dev_get_drvdata(dev);
743 u8 regs[10];
744 int ret;
745
746 if (!test_bit(HAS_ALARM, &ds1307->flags))
747 return -EINVAL;
748
749 /* Read control and alarm 0 registers. */
750 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
751 sizeof(regs));
752 if (ret)
753 return ret;
754
755 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
756
757 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
758 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
759 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
760 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
761 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
762 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
763 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
764 t->time.tm_year = -1;
765 t->time.tm_yday = -1;
766 t->time.tm_isdst = -1;
767
768 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
769 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
770 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
771 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
772 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
773 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
774 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
775
776 return 0;
777 }
778
779 /*
780 * We may have a random RTC weekday, therefore calculate alarm weekday based
781 * on current weekday we read from the RTC timekeeping regs
782 */
mcp794xx_alm_weekday(struct device * dev,struct rtc_time * tm_alarm)783 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
784 {
785 struct rtc_time tm_now;
786 int days_now, days_alarm, ret;
787
788 ret = ds1307_get_time(dev, &tm_now);
789 if (ret)
790 return ret;
791
792 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
793 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
794
795 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
796 }
797
mcp794xx_set_alarm(struct device * dev,struct rtc_wkalrm * t)798 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
799 {
800 struct ds1307 *ds1307 = dev_get_drvdata(dev);
801 unsigned char regs[10];
802 int wday, ret;
803
804 if (!test_bit(HAS_ALARM, &ds1307->flags))
805 return -EINVAL;
806
807 wday = mcp794xx_alm_weekday(dev, &t->time);
808 if (wday < 0)
809 return wday;
810
811 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
812 "enabled=%d pending=%d\n", __func__,
813 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
814 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
815 t->enabled, t->pending);
816
817 /* Read control and alarm 0 registers. */
818 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
819 sizeof(regs));
820 if (ret)
821 return ret;
822
823 /* Set alarm 0, using 24-hour and day-of-month modes. */
824 regs[3] = bin2bcd(t->time.tm_sec);
825 regs[4] = bin2bcd(t->time.tm_min);
826 regs[5] = bin2bcd(t->time.tm_hour);
827 regs[6] = wday;
828 regs[7] = bin2bcd(t->time.tm_mday);
829 regs[8] = bin2bcd(t->time.tm_mon + 1);
830
831 /* Clear the alarm 0 interrupt flag. */
832 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
833 /* Set alarm match: second, minute, hour, day, date, month. */
834 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
835 /* Disable interrupt. We will not enable until completely programmed */
836 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
837
838 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
839 sizeof(regs));
840 if (ret)
841 return ret;
842
843 if (!t->enabled)
844 return 0;
845 regs[0] |= MCP794XX_BIT_ALM0_EN;
846 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
847 }
848
mcp794xx_alarm_irq_enable(struct device * dev,unsigned int enabled)849 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
850 {
851 struct ds1307 *ds1307 = dev_get_drvdata(dev);
852
853 if (!test_bit(HAS_ALARM, &ds1307->flags))
854 return -EINVAL;
855
856 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
857 MCP794XX_BIT_ALM0_EN,
858 enabled ? MCP794XX_BIT_ALM0_EN : 0);
859 }
860
m41txx_rtc_read_offset(struct device * dev,long * offset)861 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
862 {
863 struct ds1307 *ds1307 = dev_get_drvdata(dev);
864 unsigned int ctrl_reg;
865 u8 val;
866
867 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
868
869 val = ctrl_reg & M41TXX_M_CALIBRATION;
870
871 /* check if positive */
872 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
873 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
874 else
875 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
876
877 return 0;
878 }
879
m41txx_rtc_set_offset(struct device * dev,long offset)880 static int m41txx_rtc_set_offset(struct device *dev, long offset)
881 {
882 struct ds1307 *ds1307 = dev_get_drvdata(dev);
883 unsigned int ctrl_reg;
884
885 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
886 return -ERANGE;
887
888 if (offset >= 0) {
889 ctrl_reg = DIV_ROUND_CLOSEST(offset,
890 M41TXX_POS_OFFSET_STEP_PPB);
891 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
892 } else {
893 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
894 M41TXX_NEG_OFFSET_STEP_PPB);
895 }
896
897 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
898 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
899 ctrl_reg);
900 }
901
902 #ifdef CONFIG_WATCHDOG_CORE
ds1388_wdt_start(struct watchdog_device * wdt_dev)903 static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
904 {
905 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
906 u8 regs[2];
907 int ret;
908
909 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
910 DS1388_BIT_WF, 0);
911 if (ret)
912 return ret;
913
914 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
915 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
916 if (ret)
917 return ret;
918
919 /*
920 * watchdog timeouts are measured in seconds. So ignore hundredths of
921 * seconds field.
922 */
923 regs[0] = 0;
924 regs[1] = bin2bcd(wdt_dev->timeout);
925
926 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
927 sizeof(regs));
928 if (ret)
929 return ret;
930
931 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
932 DS1388_BIT_WDE | DS1388_BIT_RST,
933 DS1388_BIT_WDE | DS1388_BIT_RST);
934 }
935
ds1388_wdt_stop(struct watchdog_device * wdt_dev)936 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
937 {
938 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
939
940 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
941 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
942 }
943
ds1388_wdt_ping(struct watchdog_device * wdt_dev)944 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
945 {
946 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
947 u8 regs[2];
948
949 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
950 sizeof(regs));
951 }
952
ds1388_wdt_set_timeout(struct watchdog_device * wdt_dev,unsigned int val)953 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
954 unsigned int val)
955 {
956 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
957 u8 regs[2];
958
959 wdt_dev->timeout = val;
960 regs[0] = 0;
961 regs[1] = bin2bcd(wdt_dev->timeout);
962
963 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
964 sizeof(regs));
965 }
966 #endif
967
968 static const struct rtc_class_ops rx8130_rtc_ops = {
969 .read_time = ds1307_get_time,
970 .set_time = ds1307_set_time,
971 .read_alarm = rx8130_read_alarm,
972 .set_alarm = rx8130_set_alarm,
973 .alarm_irq_enable = rx8130_alarm_irq_enable,
974 };
975
976 static const struct rtc_class_ops mcp794xx_rtc_ops = {
977 .read_time = ds1307_get_time,
978 .set_time = ds1307_set_time,
979 .read_alarm = mcp794xx_read_alarm,
980 .set_alarm = mcp794xx_set_alarm,
981 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
982 };
983
984 static const struct rtc_class_ops m41txx_rtc_ops = {
985 .read_time = ds1307_get_time,
986 .set_time = ds1307_set_time,
987 .read_alarm = ds1337_read_alarm,
988 .set_alarm = ds1337_set_alarm,
989 .alarm_irq_enable = ds1307_alarm_irq_enable,
990 .read_offset = m41txx_rtc_read_offset,
991 .set_offset = m41txx_rtc_set_offset,
992 };
993
994 static const struct chip_desc chips[last_ds_type] = {
995 [ds_1307] = {
996 .nvram_offset = 8,
997 .nvram_size = 56,
998 },
999 [ds_1308] = {
1000 .nvram_offset = 8,
1001 .nvram_size = 56,
1002 },
1003 [ds_1337] = {
1004 .alarm = 1,
1005 .century_reg = DS1307_REG_MONTH,
1006 .century_bit = DS1337_BIT_CENTURY,
1007 },
1008 [ds_1338] = {
1009 .nvram_offset = 8,
1010 .nvram_size = 56,
1011 },
1012 [ds_1339] = {
1013 .alarm = 1,
1014 .century_reg = DS1307_REG_MONTH,
1015 .century_bit = DS1337_BIT_CENTURY,
1016 .bbsqi_bit = DS1339_BIT_BBSQI,
1017 .trickle_charger_reg = 0x10,
1018 .do_trickle_setup = &do_trickle_setup_ds1339,
1019 .requires_trickle_resistor = true,
1020 .charge_default = true,
1021 },
1022 [ds_1340] = {
1023 .century_reg = DS1307_REG_HOUR,
1024 .century_enable_bit = DS1340_BIT_CENTURY_EN,
1025 .century_bit = DS1340_BIT_CENTURY,
1026 .do_trickle_setup = &do_trickle_setup_ds1339,
1027 .trickle_charger_reg = 0x08,
1028 .requires_trickle_resistor = true,
1029 .charge_default = true,
1030 },
1031 [ds_1341] = {
1032 .century_reg = DS1307_REG_MONTH,
1033 .century_bit = DS1337_BIT_CENTURY,
1034 },
1035 [ds_1388] = {
1036 .offset = 1,
1037 .trickle_charger_reg = 0x0a,
1038 },
1039 [ds_3231] = {
1040 .alarm = 1,
1041 .century_reg = DS1307_REG_MONTH,
1042 .century_bit = DS1337_BIT_CENTURY,
1043 .bbsqi_bit = DS3231_BIT_BBSQW,
1044 },
1045 [rx_8130] = {
1046 .alarm = 1,
1047 /* this is battery backed SRAM */
1048 .nvram_offset = 0x20,
1049 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1050 .offset = 0x10,
1051 .irq_handler = rx8130_irq,
1052 .rtc_ops = &rx8130_rtc_ops,
1053 .trickle_charger_reg = RX8130_REG_CONTROL1,
1054 .do_trickle_setup = &do_trickle_setup_rx8130,
1055 },
1056 [m41t0] = {
1057 .rtc_ops = &m41txx_rtc_ops,
1058 },
1059 [m41t00] = {
1060 .rtc_ops = &m41txx_rtc_ops,
1061 },
1062 [m41t11] = {
1063 /* this is battery backed SRAM */
1064 .nvram_offset = 8,
1065 .nvram_size = 56,
1066 .rtc_ops = &m41txx_rtc_ops,
1067 },
1068 [mcp794xx] = {
1069 .alarm = 1,
1070 /* this is battery backed SRAM */
1071 .nvram_offset = 0x20,
1072 .nvram_size = 0x40,
1073 .irq_handler = mcp794xx_irq,
1074 .rtc_ops = &mcp794xx_rtc_ops,
1075 },
1076 };
1077
1078 static const struct i2c_device_id ds1307_id[] = {
1079 { "ds1307", ds_1307 },
1080 { "ds1308", ds_1308 },
1081 { "ds1337", ds_1337 },
1082 { "ds1338", ds_1338 },
1083 { "ds1339", ds_1339 },
1084 { "ds1388", ds_1388 },
1085 { "ds1340", ds_1340 },
1086 { "ds1341", ds_1341 },
1087 { "ds3231", ds_3231 },
1088 { "m41t0", m41t0 },
1089 { "m41t00", m41t00 },
1090 { "m41t11", m41t11 },
1091 { "mcp7940x", mcp794xx },
1092 { "mcp7941x", mcp794xx },
1093 { "pt7c4338", ds_1307 },
1094 { "rx8025", rx_8025 },
1095 { "isl12057", ds_1337 },
1096 { "rx8130", rx_8130 },
1097 { }
1098 };
1099 MODULE_DEVICE_TABLE(i2c, ds1307_id);
1100
1101 #ifdef CONFIG_OF
1102 static const struct of_device_id ds1307_of_match[] = {
1103 {
1104 .compatible = "dallas,ds1307",
1105 .data = (void *)ds_1307
1106 },
1107 {
1108 .compatible = "dallas,ds1308",
1109 .data = (void *)ds_1308
1110 },
1111 {
1112 .compatible = "dallas,ds1337",
1113 .data = (void *)ds_1337
1114 },
1115 {
1116 .compatible = "dallas,ds1338",
1117 .data = (void *)ds_1338
1118 },
1119 {
1120 .compatible = "dallas,ds1339",
1121 .data = (void *)ds_1339
1122 },
1123 {
1124 .compatible = "dallas,ds1388",
1125 .data = (void *)ds_1388
1126 },
1127 {
1128 .compatible = "dallas,ds1340",
1129 .data = (void *)ds_1340
1130 },
1131 {
1132 .compatible = "dallas,ds1341",
1133 .data = (void *)ds_1341
1134 },
1135 {
1136 .compatible = "maxim,ds3231",
1137 .data = (void *)ds_3231
1138 },
1139 {
1140 .compatible = "st,m41t0",
1141 .data = (void *)m41t0
1142 },
1143 {
1144 .compatible = "st,m41t00",
1145 .data = (void *)m41t00
1146 },
1147 {
1148 .compatible = "st,m41t11",
1149 .data = (void *)m41t11
1150 },
1151 {
1152 .compatible = "microchip,mcp7940x",
1153 .data = (void *)mcp794xx
1154 },
1155 {
1156 .compatible = "microchip,mcp7941x",
1157 .data = (void *)mcp794xx
1158 },
1159 {
1160 .compatible = "pericom,pt7c4338",
1161 .data = (void *)ds_1307
1162 },
1163 {
1164 .compatible = "epson,rx8025",
1165 .data = (void *)rx_8025
1166 },
1167 {
1168 .compatible = "isil,isl12057",
1169 .data = (void *)ds_1337
1170 },
1171 {
1172 .compatible = "epson,rx8130",
1173 .data = (void *)rx_8130
1174 },
1175 { }
1176 };
1177 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1178 #endif
1179
1180 #ifdef CONFIG_ACPI
1181 static const struct acpi_device_id ds1307_acpi_ids[] = {
1182 { .id = "DS1307", .driver_data = ds_1307 },
1183 { .id = "DS1308", .driver_data = ds_1308 },
1184 { .id = "DS1337", .driver_data = ds_1337 },
1185 { .id = "DS1338", .driver_data = ds_1338 },
1186 { .id = "DS1339", .driver_data = ds_1339 },
1187 { .id = "DS1388", .driver_data = ds_1388 },
1188 { .id = "DS1340", .driver_data = ds_1340 },
1189 { .id = "DS1341", .driver_data = ds_1341 },
1190 { .id = "DS3231", .driver_data = ds_3231 },
1191 { .id = "M41T0", .driver_data = m41t0 },
1192 { .id = "M41T00", .driver_data = m41t00 },
1193 { .id = "M41T11", .driver_data = m41t11 },
1194 { .id = "MCP7940X", .driver_data = mcp794xx },
1195 { .id = "MCP7941X", .driver_data = mcp794xx },
1196 { .id = "PT7C4338", .driver_data = ds_1307 },
1197 { .id = "RX8025", .driver_data = rx_8025 },
1198 { .id = "ISL12057", .driver_data = ds_1337 },
1199 { .id = "RX8130", .driver_data = rx_8130 },
1200 { }
1201 };
1202 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
1203 #endif
1204
1205 /*
1206 * The ds1337 and ds1339 both have two alarms, but we only use the first
1207 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1208 * signal; ds1339 chips have only one alarm signal.
1209 */
ds1307_irq(int irq,void * dev_id)1210 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1211 {
1212 struct ds1307 *ds1307 = dev_id;
1213 struct mutex *lock = &ds1307->rtc->ops_lock;
1214 int stat, ret;
1215
1216 mutex_lock(lock);
1217 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1218 if (ret)
1219 goto out;
1220
1221 if (stat & DS1337_BIT_A1I) {
1222 stat &= ~DS1337_BIT_A1I;
1223 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1224
1225 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1226 DS1337_BIT_A1IE, 0);
1227 if (ret)
1228 goto out;
1229
1230 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1231 }
1232
1233 out:
1234 mutex_unlock(lock);
1235
1236 return IRQ_HANDLED;
1237 }
1238
1239 /*----------------------------------------------------------------------*/
1240
1241 static const struct rtc_class_ops ds13xx_rtc_ops = {
1242 .read_time = ds1307_get_time,
1243 .set_time = ds1307_set_time,
1244 .read_alarm = ds1337_read_alarm,
1245 .set_alarm = ds1337_set_alarm,
1246 .alarm_irq_enable = ds1307_alarm_irq_enable,
1247 };
1248
frequency_test_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1249 static ssize_t frequency_test_store(struct device *dev,
1250 struct device_attribute *attr,
1251 const char *buf, size_t count)
1252 {
1253 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1254 bool freq_test_en;
1255 int ret;
1256
1257 ret = kstrtobool(buf, &freq_test_en);
1258 if (ret) {
1259 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1260 return ret;
1261 }
1262
1263 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1264 freq_test_en ? M41TXX_BIT_FT : 0);
1265
1266 return count;
1267 }
1268
frequency_test_show(struct device * dev,struct device_attribute * attr,char * buf)1269 static ssize_t frequency_test_show(struct device *dev,
1270 struct device_attribute *attr,
1271 char *buf)
1272 {
1273 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1274 unsigned int ctrl_reg;
1275
1276 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1277
1278 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1279 "off\n");
1280 }
1281
1282 static DEVICE_ATTR_RW(frequency_test);
1283
1284 static struct attribute *rtc_freq_test_attrs[] = {
1285 &dev_attr_frequency_test.attr,
1286 NULL,
1287 };
1288
1289 static const struct attribute_group rtc_freq_test_attr_group = {
1290 .attrs = rtc_freq_test_attrs,
1291 };
1292
ds1307_add_frequency_test(struct ds1307 * ds1307)1293 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1294 {
1295 int err;
1296
1297 switch (ds1307->type) {
1298 case m41t0:
1299 case m41t00:
1300 case m41t11:
1301 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1302 if (err)
1303 return err;
1304 break;
1305 default:
1306 break;
1307 }
1308
1309 return 0;
1310 }
1311
1312 /*----------------------------------------------------------------------*/
1313
ds1307_nvram_read(void * priv,unsigned int offset,void * val,size_t bytes)1314 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1315 size_t bytes)
1316 {
1317 struct ds1307 *ds1307 = priv;
1318 const struct chip_desc *chip = &chips[ds1307->type];
1319
1320 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1321 val, bytes);
1322 }
1323
ds1307_nvram_write(void * priv,unsigned int offset,void * val,size_t bytes)1324 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1325 size_t bytes)
1326 {
1327 struct ds1307 *ds1307 = priv;
1328 const struct chip_desc *chip = &chips[ds1307->type];
1329
1330 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1331 val, bytes);
1332 }
1333
1334 /*----------------------------------------------------------------------*/
1335
ds1307_trickle_init(struct ds1307 * ds1307,const struct chip_desc * chip)1336 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1337 const struct chip_desc *chip)
1338 {
1339 u32 ohms, chargeable;
1340 bool diode = chip->charge_default;
1341
1342 if (!chip->do_trickle_setup)
1343 return 0;
1344
1345 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1346 &ohms) && chip->requires_trickle_resistor)
1347 return 0;
1348
1349 /* aux-voltage-chargeable takes precedence over the deprecated
1350 * trickle-diode-disable
1351 */
1352 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1353 &chargeable)) {
1354 switch (chargeable) {
1355 case 0:
1356 diode = false;
1357 break;
1358 case 1:
1359 diode = true;
1360 break;
1361 default:
1362 dev_warn(ds1307->dev,
1363 "unsupported aux-voltage-chargeable value\n");
1364 break;
1365 }
1366 } else if (device_property_read_bool(ds1307->dev,
1367 "trickle-diode-disable")) {
1368 diode = false;
1369 }
1370
1371 return chip->do_trickle_setup(ds1307, ohms, diode);
1372 }
1373
1374 /*----------------------------------------------------------------------*/
1375
1376 #if IS_REACHABLE(CONFIG_HWMON)
1377
1378 /*
1379 * Temperature sensor support for ds3231 devices.
1380 */
1381
1382 #define DS3231_REG_TEMPERATURE 0x11
1383
1384 /*
1385 * A user-initiated temperature conversion is not started by this function,
1386 * so the temperature is updated once every 64 seconds.
1387 */
ds3231_hwmon_read_temp(struct device * dev,s32 * mC)1388 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1389 {
1390 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1391 u8 temp_buf[2];
1392 s16 temp;
1393 int ret;
1394
1395 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1396 temp_buf, sizeof(temp_buf));
1397 if (ret)
1398 return ret;
1399 /*
1400 * Temperature is represented as a 10-bit code with a resolution of
1401 * 0.25 degree celsius and encoded in two's complement format.
1402 */
1403 temp = (temp_buf[0] << 8) | temp_buf[1];
1404 temp >>= 6;
1405 *mC = temp * 250;
1406
1407 return 0;
1408 }
1409
ds3231_hwmon_show_temp(struct device * dev,struct device_attribute * attr,char * buf)1410 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1411 struct device_attribute *attr, char *buf)
1412 {
1413 int ret;
1414 s32 temp;
1415
1416 ret = ds3231_hwmon_read_temp(dev, &temp);
1417 if (ret)
1418 return ret;
1419
1420 return sprintf(buf, "%d\n", temp);
1421 }
1422 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1423 NULL, 0);
1424
1425 static struct attribute *ds3231_hwmon_attrs[] = {
1426 &sensor_dev_attr_temp1_input.dev_attr.attr,
1427 NULL,
1428 };
1429 ATTRIBUTE_GROUPS(ds3231_hwmon);
1430
ds1307_hwmon_register(struct ds1307 * ds1307)1431 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1432 {
1433 struct device *dev;
1434
1435 if (ds1307->type != ds_3231)
1436 return;
1437
1438 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1439 ds1307,
1440 ds3231_hwmon_groups);
1441 if (IS_ERR(dev)) {
1442 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1443 PTR_ERR(dev));
1444 }
1445 }
1446
1447 #else
1448
ds1307_hwmon_register(struct ds1307 * ds1307)1449 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1450 {
1451 }
1452
1453 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1454
1455 /*----------------------------------------------------------------------*/
1456
1457 /*
1458 * Square-wave output support for DS3231
1459 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1460 */
1461 #ifdef CONFIG_COMMON_CLK
1462
1463 enum {
1464 DS3231_CLK_SQW = 0,
1465 DS3231_CLK_32KHZ,
1466 };
1467
1468 #define clk_sqw_to_ds1307(clk) \
1469 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1470 #define clk_32khz_to_ds1307(clk) \
1471 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1472
1473 static int ds3231_clk_sqw_rates[] = {
1474 1,
1475 1024,
1476 4096,
1477 8192,
1478 };
1479
ds1337_write_control(struct ds1307 * ds1307,u8 mask,u8 value)1480 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1481 {
1482 struct mutex *lock = &ds1307->rtc->ops_lock;
1483 int ret;
1484
1485 mutex_lock(lock);
1486 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1487 mask, value);
1488 mutex_unlock(lock);
1489
1490 return ret;
1491 }
1492
ds3231_clk_sqw_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1493 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1494 unsigned long parent_rate)
1495 {
1496 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1497 int control, ret;
1498 int rate_sel = 0;
1499
1500 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1501 if (ret)
1502 return ret;
1503 if (control & DS1337_BIT_RS1)
1504 rate_sel += 1;
1505 if (control & DS1337_BIT_RS2)
1506 rate_sel += 2;
1507
1508 return ds3231_clk_sqw_rates[rate_sel];
1509 }
1510
ds3231_clk_sqw_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1511 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1512 unsigned long *prate)
1513 {
1514 int i;
1515
1516 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1517 if (ds3231_clk_sqw_rates[i] <= rate)
1518 return ds3231_clk_sqw_rates[i];
1519 }
1520
1521 return 0;
1522 }
1523
ds3231_clk_sqw_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1524 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1525 unsigned long parent_rate)
1526 {
1527 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1528 int control = 0;
1529 int rate_sel;
1530
1531 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1532 rate_sel++) {
1533 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1534 break;
1535 }
1536
1537 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1538 return -EINVAL;
1539
1540 if (rate_sel & 1)
1541 control |= DS1337_BIT_RS1;
1542 if (rate_sel & 2)
1543 control |= DS1337_BIT_RS2;
1544
1545 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1546 control);
1547 }
1548
ds3231_clk_sqw_prepare(struct clk_hw * hw)1549 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1550 {
1551 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1552
1553 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1554 }
1555
ds3231_clk_sqw_unprepare(struct clk_hw * hw)1556 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1557 {
1558 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1559
1560 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1561 }
1562
ds3231_clk_sqw_is_prepared(struct clk_hw * hw)1563 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1564 {
1565 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1566 int control, ret;
1567
1568 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1569 if (ret)
1570 return ret;
1571
1572 return !(control & DS1337_BIT_INTCN);
1573 }
1574
1575 static const struct clk_ops ds3231_clk_sqw_ops = {
1576 .prepare = ds3231_clk_sqw_prepare,
1577 .unprepare = ds3231_clk_sqw_unprepare,
1578 .is_prepared = ds3231_clk_sqw_is_prepared,
1579 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1580 .round_rate = ds3231_clk_sqw_round_rate,
1581 .set_rate = ds3231_clk_sqw_set_rate,
1582 };
1583
ds3231_clk_32khz_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1584 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1585 unsigned long parent_rate)
1586 {
1587 return 32768;
1588 }
1589
ds3231_clk_32khz_control(struct ds1307 * ds1307,bool enable)1590 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1591 {
1592 struct mutex *lock = &ds1307->rtc->ops_lock;
1593 int ret;
1594
1595 mutex_lock(lock);
1596 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1597 DS3231_BIT_EN32KHZ,
1598 enable ? DS3231_BIT_EN32KHZ : 0);
1599 mutex_unlock(lock);
1600
1601 return ret;
1602 }
1603
ds3231_clk_32khz_prepare(struct clk_hw * hw)1604 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1605 {
1606 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1607
1608 return ds3231_clk_32khz_control(ds1307, true);
1609 }
1610
ds3231_clk_32khz_unprepare(struct clk_hw * hw)1611 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1612 {
1613 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1614
1615 ds3231_clk_32khz_control(ds1307, false);
1616 }
1617
ds3231_clk_32khz_is_prepared(struct clk_hw * hw)1618 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1619 {
1620 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1621 int status, ret;
1622
1623 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1624 if (ret)
1625 return ret;
1626
1627 return !!(status & DS3231_BIT_EN32KHZ);
1628 }
1629
1630 static const struct clk_ops ds3231_clk_32khz_ops = {
1631 .prepare = ds3231_clk_32khz_prepare,
1632 .unprepare = ds3231_clk_32khz_unprepare,
1633 .is_prepared = ds3231_clk_32khz_is_prepared,
1634 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1635 };
1636
1637 static struct clk_init_data ds3231_clks_init[] = {
1638 [DS3231_CLK_SQW] = {
1639 .name = "ds3231_clk_sqw",
1640 .ops = &ds3231_clk_sqw_ops,
1641 },
1642 [DS3231_CLK_32KHZ] = {
1643 .name = "ds3231_clk_32khz",
1644 .ops = &ds3231_clk_32khz_ops,
1645 },
1646 };
1647
ds3231_clks_register(struct ds1307 * ds1307)1648 static int ds3231_clks_register(struct ds1307 *ds1307)
1649 {
1650 struct device_node *node = ds1307->dev->of_node;
1651 struct clk_onecell_data *onecell;
1652 int i;
1653
1654 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1655 if (!onecell)
1656 return -ENOMEM;
1657
1658 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1659 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1660 sizeof(onecell->clks[0]), GFP_KERNEL);
1661 if (!onecell->clks)
1662 return -ENOMEM;
1663
1664 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1665 struct clk_init_data init = ds3231_clks_init[i];
1666
1667 /*
1668 * Interrupt signal due to alarm conditions and square-wave
1669 * output share same pin, so don't initialize both.
1670 */
1671 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1672 continue;
1673
1674 /* optional override of the clockname */
1675 of_property_read_string_index(node, "clock-output-names", i,
1676 &init.name);
1677 ds1307->clks[i].init = &init;
1678
1679 onecell->clks[i] = devm_clk_register(ds1307->dev,
1680 &ds1307->clks[i]);
1681 if (IS_ERR(onecell->clks[i]))
1682 return PTR_ERR(onecell->clks[i]);
1683 }
1684
1685 if (!node)
1686 return 0;
1687
1688 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1689
1690 return 0;
1691 }
1692
ds1307_clks_register(struct ds1307 * ds1307)1693 static void ds1307_clks_register(struct ds1307 *ds1307)
1694 {
1695 int ret;
1696
1697 if (ds1307->type != ds_3231)
1698 return;
1699
1700 ret = ds3231_clks_register(ds1307);
1701 if (ret) {
1702 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1703 ret);
1704 }
1705 }
1706
1707 #else
1708
ds1307_clks_register(struct ds1307 * ds1307)1709 static void ds1307_clks_register(struct ds1307 *ds1307)
1710 {
1711 }
1712
1713 #endif /* CONFIG_COMMON_CLK */
1714
1715 #ifdef CONFIG_WATCHDOG_CORE
1716 static const struct watchdog_info ds1388_wdt_info = {
1717 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1718 .identity = "DS1388 watchdog",
1719 };
1720
1721 static const struct watchdog_ops ds1388_wdt_ops = {
1722 .owner = THIS_MODULE,
1723 .start = ds1388_wdt_start,
1724 .stop = ds1388_wdt_stop,
1725 .ping = ds1388_wdt_ping,
1726 .set_timeout = ds1388_wdt_set_timeout,
1727
1728 };
1729
ds1307_wdt_register(struct ds1307 * ds1307)1730 static void ds1307_wdt_register(struct ds1307 *ds1307)
1731 {
1732 struct watchdog_device *wdt;
1733 int err;
1734 int val;
1735
1736 if (ds1307->type != ds_1388)
1737 return;
1738
1739 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1740 if (!wdt)
1741 return;
1742
1743 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1744 if (!err && val & DS1388_BIT_WF)
1745 wdt->bootstatus = WDIOF_CARDRESET;
1746
1747 wdt->info = &ds1388_wdt_info;
1748 wdt->ops = &ds1388_wdt_ops;
1749 wdt->timeout = 99;
1750 wdt->max_timeout = 99;
1751 wdt->min_timeout = 1;
1752
1753 watchdog_init_timeout(wdt, 0, ds1307->dev);
1754 watchdog_set_drvdata(wdt, ds1307);
1755 devm_watchdog_register_device(ds1307->dev, wdt);
1756 }
1757 #else
ds1307_wdt_register(struct ds1307 * ds1307)1758 static void ds1307_wdt_register(struct ds1307 *ds1307)
1759 {
1760 }
1761 #endif /* CONFIG_WATCHDOG_CORE */
1762
1763 static const struct regmap_config regmap_config = {
1764 .reg_bits = 8,
1765 .val_bits = 8,
1766 };
1767
ds1307_probe(struct i2c_client * client,const struct i2c_device_id * id)1768 static int ds1307_probe(struct i2c_client *client,
1769 const struct i2c_device_id *id)
1770 {
1771 struct ds1307 *ds1307;
1772 int err = -ENODEV;
1773 int tmp;
1774 const struct chip_desc *chip;
1775 bool want_irq;
1776 bool ds1307_can_wakeup_device = false;
1777 unsigned char regs[8];
1778 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1779 u8 trickle_charger_setup = 0;
1780
1781 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1782 if (!ds1307)
1783 return -ENOMEM;
1784
1785 dev_set_drvdata(&client->dev, ds1307);
1786 ds1307->dev = &client->dev;
1787 ds1307->name = client->name;
1788
1789 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1790 if (IS_ERR(ds1307->regmap)) {
1791 dev_err(ds1307->dev, "regmap allocation failed\n");
1792 return PTR_ERR(ds1307->regmap);
1793 }
1794
1795 i2c_set_clientdata(client, ds1307);
1796
1797 if (client->dev.of_node) {
1798 ds1307->type = (enum ds_type)
1799 of_device_get_match_data(&client->dev);
1800 chip = &chips[ds1307->type];
1801 } else if (id) {
1802 chip = &chips[id->driver_data];
1803 ds1307->type = id->driver_data;
1804 } else {
1805 const struct acpi_device_id *acpi_id;
1806
1807 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1808 ds1307->dev);
1809 if (!acpi_id)
1810 return -ENODEV;
1811 chip = &chips[acpi_id->driver_data];
1812 ds1307->type = acpi_id->driver_data;
1813 }
1814
1815 want_irq = client->irq > 0 && chip->alarm;
1816
1817 if (!pdata)
1818 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1819 else if (pdata->trickle_charger_setup)
1820 trickle_charger_setup = pdata->trickle_charger_setup;
1821
1822 if (trickle_charger_setup && chip->trickle_charger_reg) {
1823 dev_dbg(ds1307->dev,
1824 "writing trickle charger info 0x%x to 0x%x\n",
1825 trickle_charger_setup, chip->trickle_charger_reg);
1826 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1827 trickle_charger_setup);
1828 }
1829
1830 #ifdef CONFIG_OF
1831 /*
1832 * For devices with no IRQ directly connected to the SoC, the RTC chip
1833 * can be forced as a wakeup source by stating that explicitly in
1834 * the device's .dts file using the "wakeup-source" boolean property.
1835 * If the "wakeup-source" property is set, don't request an IRQ.
1836 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1837 * if supported by the RTC.
1838 */
1839 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1840 "wakeup-source"))
1841 ds1307_can_wakeup_device = true;
1842 #endif
1843
1844 switch (ds1307->type) {
1845 case ds_1337:
1846 case ds_1339:
1847 case ds_1341:
1848 case ds_3231:
1849 /* get registers that the "rtc" read below won't read... */
1850 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1851 regs, 2);
1852 if (err) {
1853 dev_dbg(ds1307->dev, "read error %d\n", err);
1854 goto exit;
1855 }
1856
1857 /* oscillator off? turn it on, so clock can tick. */
1858 if (regs[0] & DS1337_BIT_nEOSC)
1859 regs[0] &= ~DS1337_BIT_nEOSC;
1860
1861 /*
1862 * Using IRQ or defined as wakeup-source?
1863 * Disable the square wave and both alarms.
1864 * For some variants, be sure alarms can trigger when we're
1865 * running on Vbackup (BBSQI/BBSQW)
1866 */
1867 if (want_irq || ds1307_can_wakeup_device) {
1868 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1869 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1870 }
1871
1872 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1873 regs[0]);
1874
1875 /* oscillator fault? clear flag, and warn */
1876 if (regs[1] & DS1337_BIT_OSF) {
1877 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1878 regs[1] & ~DS1337_BIT_OSF);
1879 dev_warn(ds1307->dev, "SET TIME!\n");
1880 }
1881 break;
1882
1883 case rx_8025:
1884 err = regmap_bulk_read(ds1307->regmap,
1885 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1886 if (err) {
1887 dev_dbg(ds1307->dev, "read error %d\n", err);
1888 goto exit;
1889 }
1890
1891 /* oscillator off? turn it on, so clock can tick. */
1892 if (!(regs[1] & RX8025_BIT_XST)) {
1893 regs[1] |= RX8025_BIT_XST;
1894 regmap_write(ds1307->regmap,
1895 RX8025_REG_CTRL2 << 4 | 0x08,
1896 regs[1]);
1897 dev_warn(ds1307->dev,
1898 "oscillator stop detected - SET TIME!\n");
1899 }
1900
1901 if (regs[1] & RX8025_BIT_PON) {
1902 regs[1] &= ~RX8025_BIT_PON;
1903 regmap_write(ds1307->regmap,
1904 RX8025_REG_CTRL2 << 4 | 0x08,
1905 regs[1]);
1906 dev_warn(ds1307->dev, "power-on detected\n");
1907 }
1908
1909 if (regs[1] & RX8025_BIT_VDET) {
1910 regs[1] &= ~RX8025_BIT_VDET;
1911 regmap_write(ds1307->regmap,
1912 RX8025_REG_CTRL2 << 4 | 0x08,
1913 regs[1]);
1914 dev_warn(ds1307->dev, "voltage drop detected\n");
1915 }
1916
1917 /* make sure we are running in 24hour mode */
1918 if (!(regs[0] & RX8025_BIT_2412)) {
1919 u8 hour;
1920
1921 /* switch to 24 hour mode */
1922 regmap_write(ds1307->regmap,
1923 RX8025_REG_CTRL1 << 4 | 0x08,
1924 regs[0] | RX8025_BIT_2412);
1925
1926 err = regmap_bulk_read(ds1307->regmap,
1927 RX8025_REG_CTRL1 << 4 | 0x08,
1928 regs, 2);
1929 if (err) {
1930 dev_dbg(ds1307->dev, "read error %d\n", err);
1931 goto exit;
1932 }
1933
1934 /* correct hour */
1935 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1936 if (hour == 12)
1937 hour = 0;
1938 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1939 hour += 12;
1940
1941 regmap_write(ds1307->regmap,
1942 DS1307_REG_HOUR << 4 | 0x08, hour);
1943 }
1944 break;
1945 case ds_1388:
1946 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1947 if (err) {
1948 dev_dbg(ds1307->dev, "read error %d\n", err);
1949 goto exit;
1950 }
1951
1952 /* oscillator off? turn it on, so clock can tick. */
1953 if (tmp & DS1388_BIT_nEOSC) {
1954 tmp &= ~DS1388_BIT_nEOSC;
1955 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1956 }
1957 break;
1958 default:
1959 break;
1960 }
1961
1962 /* read RTC registers */
1963 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1964 sizeof(regs));
1965 if (err) {
1966 dev_dbg(ds1307->dev, "read error %d\n", err);
1967 goto exit;
1968 }
1969
1970 if (ds1307->type == mcp794xx &&
1971 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1972 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1973 regs[DS1307_REG_WDAY] |
1974 MCP794XX_BIT_VBATEN);
1975 }
1976
1977 tmp = regs[DS1307_REG_HOUR];
1978 switch (ds1307->type) {
1979 case ds_1340:
1980 case m41t0:
1981 case m41t00:
1982 case m41t11:
1983 /*
1984 * NOTE: ignores century bits; fix before deploying
1985 * systems that will run through year 2100.
1986 */
1987 break;
1988 case rx_8025:
1989 break;
1990 default:
1991 if (!(tmp & DS1307_BIT_12HR))
1992 break;
1993
1994 /*
1995 * Be sure we're in 24 hour mode. Multi-master systems
1996 * take note...
1997 */
1998 tmp = bcd2bin(tmp & 0x1f);
1999 if (tmp == 12)
2000 tmp = 0;
2001 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
2002 tmp += 12;
2003 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
2004 bin2bcd(tmp));
2005 }
2006
2007 if (want_irq || ds1307_can_wakeup_device) {
2008 device_set_wakeup_capable(ds1307->dev, true);
2009 set_bit(HAS_ALARM, &ds1307->flags);
2010 }
2011
2012 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
2013 if (IS_ERR(ds1307->rtc))
2014 return PTR_ERR(ds1307->rtc);
2015
2016 if (ds1307_can_wakeup_device && !want_irq) {
2017 dev_info(ds1307->dev,
2018 "'wakeup-source' is set, request for an IRQ is disabled!\n");
2019 /* We cannot support UIE mode if we do not have an IRQ line */
2020 ds1307->rtc->uie_unsupported = 1;
2021 }
2022
2023 if (want_irq) {
2024 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
2025 chip->irq_handler ?: ds1307_irq,
2026 IRQF_SHARED | IRQF_ONESHOT,
2027 ds1307->name, ds1307);
2028 if (err) {
2029 client->irq = 0;
2030 device_set_wakeup_capable(ds1307->dev, false);
2031 clear_bit(HAS_ALARM, &ds1307->flags);
2032 dev_err(ds1307->dev, "unable to request IRQ!\n");
2033 } else {
2034 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
2035 }
2036 }
2037
2038 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
2039 err = ds1307_add_frequency_test(ds1307);
2040 if (err)
2041 return err;
2042
2043 err = rtc_register_device(ds1307->rtc);
2044 if (err)
2045 return err;
2046
2047 if (chip->nvram_size) {
2048 struct nvmem_config nvmem_cfg = {
2049 .name = "ds1307_nvram",
2050 .word_size = 1,
2051 .stride = 1,
2052 .size = chip->nvram_size,
2053 .reg_read = ds1307_nvram_read,
2054 .reg_write = ds1307_nvram_write,
2055 .priv = ds1307,
2056 };
2057
2058 ds1307->rtc->nvram_old_abi = true;
2059 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
2060 }
2061
2062 ds1307_hwmon_register(ds1307);
2063 ds1307_clks_register(ds1307);
2064 ds1307_wdt_register(ds1307);
2065
2066 return 0;
2067
2068 exit:
2069 return err;
2070 }
2071
2072 static struct i2c_driver ds1307_driver = {
2073 .driver = {
2074 .name = "rtc-ds1307",
2075 .of_match_table = of_match_ptr(ds1307_of_match),
2076 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
2077 },
2078 .probe = ds1307_probe,
2079 .id_table = ds1307_id,
2080 };
2081
2082 module_i2c_driver(ds1307_driver);
2083
2084 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2085 MODULE_LICENSE("GPL");
2086