1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * An I2C and SPI driver for the NXP PCF2127/29 RTC
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
8 * Watchdog and tamper functions
9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com>
10 *
11 * based on the other drivers in this same directory.
12 *
13 * Datasheet: http://cache.nxp.com/documents/data_sheet/PCF2127.pdf
14 */
15
16 #include <linux/i2c.h>
17 #include <linux/spi/spi.h>
18 #include <linux/bcd.h>
19 #include <linux/rtc.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_irq.h>
24 #include <linux/regmap.h>
25 #include <linux/watchdog.h>
26
27 /* Control register 1 */
28 #define PCF2127_REG_CTRL1 0x00
29 #define PCF2127_BIT_CTRL1_TSF1 BIT(4)
30 /* Control register 2 */
31 #define PCF2127_REG_CTRL2 0x01
32 #define PCF2127_BIT_CTRL2_AIE BIT(1)
33 #define PCF2127_BIT_CTRL2_TSIE BIT(2)
34 #define PCF2127_BIT_CTRL2_AF BIT(4)
35 #define PCF2127_BIT_CTRL2_TSF2 BIT(5)
36 #define PCF2127_BIT_CTRL2_WDTF BIT(6)
37 /* Control register 3 */
38 #define PCF2127_REG_CTRL3 0x02
39 #define PCF2127_BIT_CTRL3_BLIE BIT(0)
40 #define PCF2127_BIT_CTRL3_BIE BIT(1)
41 #define PCF2127_BIT_CTRL3_BLF BIT(2)
42 #define PCF2127_BIT_CTRL3_BF BIT(3)
43 #define PCF2127_BIT_CTRL3_BTSE BIT(4)
44 /* Time and date registers */
45 #define PCF2127_REG_SC 0x03
46 #define PCF2127_BIT_SC_OSF BIT(7)
47 #define PCF2127_REG_MN 0x04
48 #define PCF2127_REG_HR 0x05
49 #define PCF2127_REG_DM 0x06
50 #define PCF2127_REG_DW 0x07
51 #define PCF2127_REG_MO 0x08
52 #define PCF2127_REG_YR 0x09
53 /* Alarm registers */
54 #define PCF2127_REG_ALARM_SC 0x0A
55 #define PCF2127_REG_ALARM_MN 0x0B
56 #define PCF2127_REG_ALARM_HR 0x0C
57 #define PCF2127_REG_ALARM_DM 0x0D
58 #define PCF2127_REG_ALARM_DW 0x0E
59 #define PCF2127_BIT_ALARM_AE BIT(7)
60 /* Watchdog registers */
61 #define PCF2127_REG_WD_CTL 0x10
62 #define PCF2127_BIT_WD_CTL_TF0 BIT(0)
63 #define PCF2127_BIT_WD_CTL_TF1 BIT(1)
64 #define PCF2127_BIT_WD_CTL_CD0 BIT(6)
65 #define PCF2127_BIT_WD_CTL_CD1 BIT(7)
66 #define PCF2127_REG_WD_VAL 0x11
67 /* Tamper timestamp registers */
68 #define PCF2127_REG_TS_CTRL 0x12
69 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
70 #define PCF2127_BIT_TS_CTRL_TSM BIT(7)
71 #define PCF2127_REG_TS_SC 0x13
72 #define PCF2127_REG_TS_MN 0x14
73 #define PCF2127_REG_TS_HR 0x15
74 #define PCF2127_REG_TS_DM 0x16
75 #define PCF2127_REG_TS_MO 0x17
76 #define PCF2127_REG_TS_YR 0x18
77 /*
78 * RAM registers
79 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
80 * battery backed and can survive a power outage.
81 * PCF2129 doesn't have this feature.
82 */
83 #define PCF2127_REG_RAM_ADDR_MSB 0x1A
84 #define PCF2127_REG_RAM_WRT_CMD 0x1C
85 #define PCF2127_REG_RAM_RD_CMD 0x1D
86
87 /* Watchdog timer value constants */
88 #define PCF2127_WD_VAL_STOP 0
89 #define PCF2127_WD_VAL_MIN 2
90 #define PCF2127_WD_VAL_MAX 255
91 #define PCF2127_WD_VAL_DEFAULT 60
92
93 struct pcf2127 {
94 struct rtc_device *rtc;
95 struct watchdog_device wdd;
96 struct regmap *regmap;
97 };
98
99 /*
100 * In the routines that deal directly with the pcf2127 hardware, we use
101 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
102 */
pcf2127_rtc_read_time(struct device * dev,struct rtc_time * tm)103 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
104 {
105 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
106 unsigned char buf[10];
107 int ret;
108
109 /*
110 * Avoid reading CTRL2 register as it causes WD_VAL register
111 * value to reset to 0 which means watchdog is stopped.
112 */
113 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL3,
114 (buf + PCF2127_REG_CTRL3),
115 ARRAY_SIZE(buf) - PCF2127_REG_CTRL3);
116 if (ret) {
117 dev_err(dev, "%s: read error\n", __func__);
118 return ret;
119 }
120
121 if (buf[PCF2127_REG_CTRL3] & PCF2127_BIT_CTRL3_BLF)
122 dev_info(dev,
123 "low voltage detected, check/replace RTC battery.\n");
124
125 /* Clock integrity is not guaranteed when OSF flag is set. */
126 if (buf[PCF2127_REG_SC] & PCF2127_BIT_SC_OSF) {
127 /*
128 * no need clear the flag here,
129 * it will be cleared once the new date is saved
130 */
131 dev_warn(dev,
132 "oscillator stop detected, date/time is not reliable\n");
133 return -EINVAL;
134 }
135
136 dev_dbg(dev,
137 "%s: raw data is cr3=%02x, sec=%02x, min=%02x, hr=%02x, "
138 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n",
139 __func__, buf[PCF2127_REG_CTRL3], buf[PCF2127_REG_SC],
140 buf[PCF2127_REG_MN], buf[PCF2127_REG_HR],
141 buf[PCF2127_REG_DM], buf[PCF2127_REG_DW],
142 buf[PCF2127_REG_MO], buf[PCF2127_REG_YR]);
143
144 tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F);
145 tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
146 tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F); /* rtc hr 0-23 */
147 tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
148 tm->tm_wday = buf[PCF2127_REG_DW] & 0x07;
149 tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */
150 tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]);
151 tm->tm_year += 100;
152
153 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
154 "mday=%d, mon=%d, year=%d, wday=%d\n",
155 __func__,
156 tm->tm_sec, tm->tm_min, tm->tm_hour,
157 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
158
159 return 0;
160 }
161
pcf2127_rtc_set_time(struct device * dev,struct rtc_time * tm)162 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
163 {
164 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
165 unsigned char buf[7];
166 int i = 0, err;
167
168 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
169 "mday=%d, mon=%d, year=%d, wday=%d\n",
170 __func__,
171 tm->tm_sec, tm->tm_min, tm->tm_hour,
172 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
173
174 /* hours, minutes and seconds */
175 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */
176 buf[i++] = bin2bcd(tm->tm_min);
177 buf[i++] = bin2bcd(tm->tm_hour);
178 buf[i++] = bin2bcd(tm->tm_mday);
179 buf[i++] = tm->tm_wday & 0x07;
180
181 /* month, 1 - 12 */
182 buf[i++] = bin2bcd(tm->tm_mon + 1);
183
184 /* year */
185 buf[i++] = bin2bcd(tm->tm_year - 100);
186
187 /* write register's data */
188 err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i);
189 if (err) {
190 dev_err(dev,
191 "%s: err=%d", __func__, err);
192 return err;
193 }
194
195 return 0;
196 }
197
pcf2127_rtc_ioctl(struct device * dev,unsigned int cmd,unsigned long arg)198 static int pcf2127_rtc_ioctl(struct device *dev,
199 unsigned int cmd, unsigned long arg)
200 {
201 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
202 int val, touser = 0;
203 int ret;
204
205 switch (cmd) {
206 case RTC_VL_READ:
207 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val);
208 if (ret)
209 return ret;
210
211 if (val & PCF2127_BIT_CTRL3_BLF)
212 touser |= RTC_VL_BACKUP_LOW;
213
214 if (val & PCF2127_BIT_CTRL3_BF)
215 touser |= RTC_VL_BACKUP_SWITCH;
216
217 return put_user(touser, (unsigned int __user *)arg);
218
219 case RTC_VL_CLR:
220 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
221 PCF2127_BIT_CTRL3_BF, 0);
222
223 default:
224 return -ENOIOCTLCMD;
225 }
226 }
227
228 static const struct rtc_class_ops pcf2127_rtc_ops = {
229 .ioctl = pcf2127_rtc_ioctl,
230 .read_time = pcf2127_rtc_read_time,
231 .set_time = pcf2127_rtc_set_time,
232 };
233
pcf2127_nvmem_read(void * priv,unsigned int offset,void * val,size_t bytes)234 static int pcf2127_nvmem_read(void *priv, unsigned int offset,
235 void *val, size_t bytes)
236 {
237 struct pcf2127 *pcf2127 = priv;
238 int ret;
239 unsigned char offsetbuf[] = { offset >> 8, offset };
240
241 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
242 offsetbuf, 2);
243 if (ret)
244 return ret;
245
246 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD,
247 val, bytes);
248 }
249
pcf2127_nvmem_write(void * priv,unsigned int offset,void * val,size_t bytes)250 static int pcf2127_nvmem_write(void *priv, unsigned int offset,
251 void *val, size_t bytes)
252 {
253 struct pcf2127 *pcf2127 = priv;
254 int ret;
255 unsigned char offsetbuf[] = { offset >> 8, offset };
256
257 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
258 offsetbuf, 2);
259 if (ret)
260 return ret;
261
262 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD,
263 val, bytes);
264 }
265
266 /* watchdog driver */
267
pcf2127_wdt_ping(struct watchdog_device * wdd)268 static int pcf2127_wdt_ping(struct watchdog_device *wdd)
269 {
270 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
271
272 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout);
273 }
274
275 /*
276 * Restart watchdog timer if feature is active.
277 *
278 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
279 * since register also contain control/status flags for other features.
280 * Always call this function after reading CTRL2 register.
281 */
pcf2127_wdt_active_ping(struct watchdog_device * wdd)282 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd)
283 {
284 int ret = 0;
285
286 if (watchdog_active(wdd)) {
287 ret = pcf2127_wdt_ping(wdd);
288 if (ret)
289 dev_err(wdd->parent,
290 "%s: watchdog restart failed, ret=%d\n",
291 __func__, ret);
292 }
293
294 return ret;
295 }
296
pcf2127_wdt_start(struct watchdog_device * wdd)297 static int pcf2127_wdt_start(struct watchdog_device *wdd)
298 {
299 return pcf2127_wdt_ping(wdd);
300 }
301
pcf2127_wdt_stop(struct watchdog_device * wdd)302 static int pcf2127_wdt_stop(struct watchdog_device *wdd)
303 {
304 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
305
306 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL,
307 PCF2127_WD_VAL_STOP);
308 }
309
pcf2127_wdt_set_timeout(struct watchdog_device * wdd,unsigned int new_timeout)310 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
311 unsigned int new_timeout)
312 {
313 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
314 new_timeout, wdd->timeout);
315
316 wdd->timeout = new_timeout;
317
318 return pcf2127_wdt_active_ping(wdd);
319 }
320
321 static const struct watchdog_info pcf2127_wdt_info = {
322 .identity = "NXP PCF2127/PCF2129 Watchdog",
323 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
324 };
325
326 static const struct watchdog_ops pcf2127_watchdog_ops = {
327 .owner = THIS_MODULE,
328 .start = pcf2127_wdt_start,
329 .stop = pcf2127_wdt_stop,
330 .ping = pcf2127_wdt_ping,
331 .set_timeout = pcf2127_wdt_set_timeout,
332 };
333
pcf2127_watchdog_init(struct device * dev,struct pcf2127 * pcf2127)334 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
335 {
336 u32 wdd_timeout;
337 int ret;
338
339 if (!IS_ENABLED(CONFIG_WATCHDOG) ||
340 !device_property_read_bool(dev, "reset-source"))
341 return 0;
342
343 pcf2127->wdd.parent = dev;
344 pcf2127->wdd.info = &pcf2127_wdt_info;
345 pcf2127->wdd.ops = &pcf2127_watchdog_ops;
346 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN;
347 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX;
348 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT;
349 pcf2127->wdd.min_hw_heartbeat_ms = 500;
350 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
351
352 watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
353
354 /* Test if watchdog timer is started by bootloader */
355 ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout);
356 if (ret)
357 return ret;
358
359 if (wdd_timeout)
360 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
361
362 return devm_watchdog_register_device(dev, &pcf2127->wdd);
363 }
364
365 /* Alarm */
pcf2127_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)366 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
367 {
368 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
369 u8 buf[5];
370 unsigned int ctrl2;
371 int ret;
372
373 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
374 if (ret)
375 return ret;
376
377 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
378 if (ret)
379 return ret;
380
381 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
382 sizeof(buf));
383 if (ret)
384 return ret;
385
386 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE;
387 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF;
388
389 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
390 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F);
391 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F);
392 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F);
393
394 return 0;
395 }
396
pcf2127_rtc_alarm_irq_enable(struct device * dev,u32 enable)397 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable)
398 {
399 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
400 int ret;
401
402 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
403 PCF2127_BIT_CTRL2_AIE,
404 enable ? PCF2127_BIT_CTRL2_AIE : 0);
405 if (ret)
406 return ret;
407
408 return pcf2127_wdt_active_ping(&pcf2127->wdd);
409 }
410
pcf2127_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)411 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
412 {
413 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
414 uint8_t buf[5];
415 int ret;
416
417 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
418 PCF2127_BIT_CTRL2_AF, 0);
419 if (ret)
420 return ret;
421
422 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
423 if (ret)
424 return ret;
425
426 buf[0] = bin2bcd(alrm->time.tm_sec);
427 buf[1] = bin2bcd(alrm->time.tm_min);
428 buf[2] = bin2bcd(alrm->time.tm_hour);
429 buf[3] = bin2bcd(alrm->time.tm_mday);
430 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */
431
432 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
433 sizeof(buf));
434 if (ret)
435 return ret;
436
437 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
438 }
439
pcf2127_rtc_irq(int irq,void * dev)440 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
441 {
442 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
443 unsigned int ctrl2 = 0;
444 int ret = 0;
445
446 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
447 if (ret)
448 return IRQ_NONE;
449
450 if (!(ctrl2 & PCF2127_BIT_CTRL2_AF))
451 return IRQ_NONE;
452
453 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
454 ctrl2 & ~(PCF2127_BIT_CTRL2_AF | PCF2127_BIT_CTRL2_WDTF));
455
456 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
457
458 pcf2127_wdt_active_ping(&pcf2127->wdd);
459
460 return IRQ_HANDLED;
461 }
462
463 static const struct rtc_class_ops pcf2127_rtc_alrm_ops = {
464 .ioctl = pcf2127_rtc_ioctl,
465 .read_time = pcf2127_rtc_read_time,
466 .set_time = pcf2127_rtc_set_time,
467 .read_alarm = pcf2127_rtc_read_alarm,
468 .set_alarm = pcf2127_rtc_set_alarm,
469 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
470 };
471
472 /* sysfs interface */
473
timestamp0_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)474 static ssize_t timestamp0_store(struct device *dev,
475 struct device_attribute *attr,
476 const char *buf, size_t count)
477 {
478 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
479 int ret;
480
481 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
482 PCF2127_BIT_CTRL1_TSF1, 0);
483 if (ret) {
484 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret);
485 return ret;
486 }
487
488 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
489 PCF2127_BIT_CTRL2_TSF2, 0);
490 if (ret) {
491 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret);
492 return ret;
493 }
494
495 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
496 if (ret)
497 return ret;
498
499 return count;
500 };
501
timestamp0_show(struct device * dev,struct device_attribute * attr,char * buf)502 static ssize_t timestamp0_show(struct device *dev,
503 struct device_attribute *attr, char *buf)
504 {
505 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
506 struct rtc_time tm;
507 int ret;
508 unsigned char data[25];
509
510 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL1, data,
511 sizeof(data));
512 if (ret) {
513 dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
514 return ret;
515 }
516
517 dev_dbg(dev,
518 "%s: raw data is cr1=%02x, cr2=%02x, cr3=%02x, ts_sc=%02x, "
519 "ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
520 __func__, data[PCF2127_REG_CTRL1], data[PCF2127_REG_CTRL2],
521 data[PCF2127_REG_CTRL3], data[PCF2127_REG_TS_SC],
522 data[PCF2127_REG_TS_MN], data[PCF2127_REG_TS_HR],
523 data[PCF2127_REG_TS_DM], data[PCF2127_REG_TS_MO],
524 data[PCF2127_REG_TS_YR]);
525
526 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
527 if (ret)
528 return ret;
529
530 if (!(data[PCF2127_REG_CTRL1] & PCF2127_BIT_CTRL1_TSF1) &&
531 !(data[PCF2127_REG_CTRL2] & PCF2127_BIT_CTRL2_TSF2))
532 return 0;
533
534 tm.tm_sec = bcd2bin(data[PCF2127_REG_TS_SC] & 0x7F);
535 tm.tm_min = bcd2bin(data[PCF2127_REG_TS_MN] & 0x7F);
536 tm.tm_hour = bcd2bin(data[PCF2127_REG_TS_HR] & 0x3F);
537 tm.tm_mday = bcd2bin(data[PCF2127_REG_TS_DM] & 0x3F);
538 /* TS_MO register (month) value range: 1-12 */
539 tm.tm_mon = bcd2bin(data[PCF2127_REG_TS_MO] & 0x1F) - 1;
540 tm.tm_year = bcd2bin(data[PCF2127_REG_TS_YR]);
541 if (tm.tm_year < 70)
542 tm.tm_year += 100; /* assume we are in 1970...2069 */
543
544 ret = rtc_valid_tm(&tm);
545 if (ret)
546 return ret;
547
548 return sprintf(buf, "%llu\n",
549 (unsigned long long)rtc_tm_to_time64(&tm));
550 };
551
552 static DEVICE_ATTR_RW(timestamp0);
553
554 static struct attribute *pcf2127_attrs[] = {
555 &dev_attr_timestamp0.attr,
556 NULL
557 };
558
559 static const struct attribute_group pcf2127_attr_group = {
560 .attrs = pcf2127_attrs,
561 };
562
pcf2127_probe(struct device * dev,struct regmap * regmap,int alarm_irq,const char * name,bool has_nvmem)563 static int pcf2127_probe(struct device *dev, struct regmap *regmap,
564 int alarm_irq, const char *name, bool has_nvmem)
565 {
566 struct pcf2127 *pcf2127;
567 int ret = 0;
568
569 dev_dbg(dev, "%s\n", __func__);
570
571 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL);
572 if (!pcf2127)
573 return -ENOMEM;
574
575 pcf2127->regmap = regmap;
576
577 dev_set_drvdata(dev, pcf2127);
578
579 pcf2127->rtc = devm_rtc_allocate_device(dev);
580 if (IS_ERR(pcf2127->rtc))
581 return PTR_ERR(pcf2127->rtc);
582
583 pcf2127->rtc->ops = &pcf2127_rtc_ops;
584 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
585 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099;
586 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
587 pcf2127->rtc->uie_unsupported = 1;
588
589 if (alarm_irq > 0) {
590 ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
591 pcf2127_rtc_irq,
592 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
593 dev_name(dev), dev);
594 if (ret) {
595 dev_err(dev, "failed to request alarm irq\n");
596 return ret;
597 }
598 }
599
600 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
601 device_init_wakeup(dev, true);
602 pcf2127->rtc->ops = &pcf2127_rtc_alrm_ops;
603 }
604
605 if (has_nvmem) {
606 struct nvmem_config nvmem_cfg = {
607 .priv = pcf2127,
608 .reg_read = pcf2127_nvmem_read,
609 .reg_write = pcf2127_nvmem_write,
610 .size = 512,
611 };
612
613 ret = rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
614 }
615
616 /*
617 * Watchdog timer enabled and reset pin /RST activated when timed out.
618 * Select 1Hz clock source for watchdog timer.
619 * Note: Countdown timer disabled and not available.
620 */
621 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
622 PCF2127_BIT_WD_CTL_CD1 |
623 PCF2127_BIT_WD_CTL_CD0 |
624 PCF2127_BIT_WD_CTL_TF1 |
625 PCF2127_BIT_WD_CTL_TF0,
626 PCF2127_BIT_WD_CTL_CD1 |
627 PCF2127_BIT_WD_CTL_CD0 |
628 PCF2127_BIT_WD_CTL_TF1);
629 if (ret) {
630 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
631 return ret;
632 }
633
634 pcf2127_watchdog_init(dev, pcf2127);
635
636 /*
637 * Disable battery low/switch-over timestamp and interrupts.
638 * Clear battery interrupt flags which can block new trigger events.
639 * Note: This is the default chip behaviour but added to ensure
640 * correct tamper timestamp and interrupt function.
641 */
642 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
643 PCF2127_BIT_CTRL3_BTSE |
644 PCF2127_BIT_CTRL3_BIE |
645 PCF2127_BIT_CTRL3_BLIE, 0);
646 if (ret) {
647 dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
648 __func__);
649 return ret;
650 }
651
652 /*
653 * Enable timestamp function and store timestamp of first trigger
654 * event until TSF1 and TFS2 interrupt flags are cleared.
655 */
656 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL,
657 PCF2127_BIT_TS_CTRL_TSOFF |
658 PCF2127_BIT_TS_CTRL_TSM,
659 PCF2127_BIT_TS_CTRL_TSM);
660 if (ret) {
661 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n",
662 __func__);
663 return ret;
664 }
665
666 /*
667 * Enable interrupt generation when TSF1 or TSF2 timestamp flags
668 * are set. Interrupt signal is an open-drain output and can be
669 * left floating if unused.
670 */
671 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
672 PCF2127_BIT_CTRL2_TSIE,
673 PCF2127_BIT_CTRL2_TSIE);
674 if (ret) {
675 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n",
676 __func__);
677 return ret;
678 }
679
680 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group);
681 if (ret) {
682 dev_err(dev, "%s: tamper sysfs registering failed\n",
683 __func__);
684 return ret;
685 }
686
687 return rtc_register_device(pcf2127->rtc);
688 }
689
690 #ifdef CONFIG_OF
691 static const struct of_device_id pcf2127_of_match[] = {
692 { .compatible = "nxp,pcf2127" },
693 { .compatible = "nxp,pcf2129" },
694 { .compatible = "nxp,pca2129" },
695 {}
696 };
697 MODULE_DEVICE_TABLE(of, pcf2127_of_match);
698 #endif
699
700 #if IS_ENABLED(CONFIG_I2C)
701
pcf2127_i2c_write(void * context,const void * data,size_t count)702 static int pcf2127_i2c_write(void *context, const void *data, size_t count)
703 {
704 struct device *dev = context;
705 struct i2c_client *client = to_i2c_client(dev);
706 int ret;
707
708 ret = i2c_master_send(client, data, count);
709 if (ret != count)
710 return ret < 0 ? ret : -EIO;
711
712 return 0;
713 }
714
pcf2127_i2c_gather_write(void * context,const void * reg,size_t reg_size,const void * val,size_t val_size)715 static int pcf2127_i2c_gather_write(void *context,
716 const void *reg, size_t reg_size,
717 const void *val, size_t val_size)
718 {
719 struct device *dev = context;
720 struct i2c_client *client = to_i2c_client(dev);
721 int ret;
722 void *buf;
723
724 if (WARN_ON(reg_size != 1))
725 return -EINVAL;
726
727 buf = kmalloc(val_size + 1, GFP_KERNEL);
728 if (!buf)
729 return -ENOMEM;
730
731 memcpy(buf, reg, 1);
732 memcpy(buf + 1, val, val_size);
733
734 ret = i2c_master_send(client, buf, val_size + 1);
735
736 kfree(buf);
737
738 if (ret != val_size + 1)
739 return ret < 0 ? ret : -EIO;
740
741 return 0;
742 }
743
pcf2127_i2c_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)744 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size,
745 void *val, size_t val_size)
746 {
747 struct device *dev = context;
748 struct i2c_client *client = to_i2c_client(dev);
749 int ret;
750
751 if (WARN_ON(reg_size != 1))
752 return -EINVAL;
753
754 ret = i2c_master_send(client, reg, 1);
755 if (ret != 1)
756 return ret < 0 ? ret : -EIO;
757
758 ret = i2c_master_recv(client, val, val_size);
759 if (ret != val_size)
760 return ret < 0 ? ret : -EIO;
761
762 return 0;
763 }
764
765 /*
766 * The reason we need this custom regmap_bus instead of using regmap_init_i2c()
767 * is that the STOP condition is required between set register address and
768 * read register data when reading from registers.
769 */
770 static const struct regmap_bus pcf2127_i2c_regmap = {
771 .write = pcf2127_i2c_write,
772 .gather_write = pcf2127_i2c_gather_write,
773 .read = pcf2127_i2c_read,
774 };
775
776 static struct i2c_driver pcf2127_i2c_driver;
777
pcf2127_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)778 static int pcf2127_i2c_probe(struct i2c_client *client,
779 const struct i2c_device_id *id)
780 {
781 struct regmap *regmap;
782 static const struct regmap_config config = {
783 .reg_bits = 8,
784 .val_bits = 8,
785 .max_register = 0x1d,
786 };
787
788 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
789 return -ENODEV;
790
791 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap,
792 &client->dev, &config);
793 if (IS_ERR(regmap)) {
794 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
795 __func__, PTR_ERR(regmap));
796 return PTR_ERR(regmap);
797 }
798
799 return pcf2127_probe(&client->dev, regmap, client->irq,
800 pcf2127_i2c_driver.driver.name, id->driver_data);
801 }
802
803 static const struct i2c_device_id pcf2127_i2c_id[] = {
804 { "pcf2127", 1 },
805 { "pcf2129", 0 },
806 { "pca2129", 0 },
807 { }
808 };
809 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
810
811 static struct i2c_driver pcf2127_i2c_driver = {
812 .driver = {
813 .name = "rtc-pcf2127-i2c",
814 .of_match_table = of_match_ptr(pcf2127_of_match),
815 },
816 .probe = pcf2127_i2c_probe,
817 .id_table = pcf2127_i2c_id,
818 };
819
pcf2127_i2c_register_driver(void)820 static int pcf2127_i2c_register_driver(void)
821 {
822 return i2c_add_driver(&pcf2127_i2c_driver);
823 }
824
pcf2127_i2c_unregister_driver(void)825 static void pcf2127_i2c_unregister_driver(void)
826 {
827 i2c_del_driver(&pcf2127_i2c_driver);
828 }
829
830 #else
831
pcf2127_i2c_register_driver(void)832 static int pcf2127_i2c_register_driver(void)
833 {
834 return 0;
835 }
836
pcf2127_i2c_unregister_driver(void)837 static void pcf2127_i2c_unregister_driver(void)
838 {
839 }
840
841 #endif
842
843 #if IS_ENABLED(CONFIG_SPI_MASTER)
844
845 static struct spi_driver pcf2127_spi_driver;
846
pcf2127_spi_probe(struct spi_device * spi)847 static int pcf2127_spi_probe(struct spi_device *spi)
848 {
849 static const struct regmap_config config = {
850 .reg_bits = 8,
851 .val_bits = 8,
852 .read_flag_mask = 0xa0,
853 .write_flag_mask = 0x20,
854 .max_register = 0x1d,
855 };
856 struct regmap *regmap;
857
858 regmap = devm_regmap_init_spi(spi, &config);
859 if (IS_ERR(regmap)) {
860 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
861 __func__, PTR_ERR(regmap));
862 return PTR_ERR(regmap);
863 }
864
865 return pcf2127_probe(&spi->dev, regmap, spi->irq,
866 pcf2127_spi_driver.driver.name,
867 spi_get_device_id(spi)->driver_data);
868 }
869
870 static const struct spi_device_id pcf2127_spi_id[] = {
871 { "pcf2127", 1 },
872 { "pcf2129", 0 },
873 { "pca2129", 0 },
874 { }
875 };
876 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
877
878 static struct spi_driver pcf2127_spi_driver = {
879 .driver = {
880 .name = "rtc-pcf2127-spi",
881 .of_match_table = of_match_ptr(pcf2127_of_match),
882 },
883 .probe = pcf2127_spi_probe,
884 .id_table = pcf2127_spi_id,
885 };
886
pcf2127_spi_register_driver(void)887 static int pcf2127_spi_register_driver(void)
888 {
889 return spi_register_driver(&pcf2127_spi_driver);
890 }
891
pcf2127_spi_unregister_driver(void)892 static void pcf2127_spi_unregister_driver(void)
893 {
894 spi_unregister_driver(&pcf2127_spi_driver);
895 }
896
897 #else
898
pcf2127_spi_register_driver(void)899 static int pcf2127_spi_register_driver(void)
900 {
901 return 0;
902 }
903
pcf2127_spi_unregister_driver(void)904 static void pcf2127_spi_unregister_driver(void)
905 {
906 }
907
908 #endif
909
pcf2127_init(void)910 static int __init pcf2127_init(void)
911 {
912 int ret;
913
914 ret = pcf2127_i2c_register_driver();
915 if (ret) {
916 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret);
917 return ret;
918 }
919
920 ret = pcf2127_spi_register_driver();
921 if (ret) {
922 pr_err("Failed to register pcf2127 spi driver: %d\n", ret);
923 pcf2127_i2c_unregister_driver();
924 }
925
926 return ret;
927 }
module_init(pcf2127_init)928 module_init(pcf2127_init)
929
930 static void __exit pcf2127_exit(void)
931 {
932 pcf2127_spi_unregister_driver();
933 pcf2127_i2c_unregister_driver();
934 }
935 module_exit(pcf2127_exit)
936
937 MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
938 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver");
939 MODULE_LICENSE("GPL v2");
940