1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * 8250-core based driver for the OMAP internal UART
4 *
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 *
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
8 *
9 */
10
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/serial_8250.h>
16 #include <linux/serial_reg.h>
17 #include <linux/tty_flip.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_irq.h>
24 #include <linux/delay.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/console.h>
27 #include <linux/pm_qos.h>
28 #include <linux/pm_wakeirq.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/sys_soc.h>
31
32 #include "8250.h"
33
34 #define DEFAULT_CLK_SPEED 48000000
35
36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
38 #define OMAP_DMA_TX_KICK (1 << 2)
39 /*
40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
41 * The same errata is applicable to AM335x and DRA7x processors too.
42 */
43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
44 #define UART_HAS_EFR2 BIT(4)
45 #define UART_HAS_RHR_IT_DIS BIT(5)
46 #define UART_RX_TIMEOUT_QUIRK BIT(6)
47
48 #define OMAP_UART_FCR_RX_TRIG 6
49 #define OMAP_UART_FCR_TX_TRIG 4
50
51 /* SCR register bitmasks */
52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
54 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
55 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
56 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
57 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
58
59 /* MVR register bitmasks */
60 #define OMAP_UART_MVR_SCHEME_SHIFT 30
61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
63 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
64 #define OMAP_UART_MVR_MAJ_MASK 0x700
65 #define OMAP_UART_MVR_MAJ_SHIFT 8
66 #define OMAP_UART_MVR_MIN_MASK 0x3f
67
68 /* SYSC register bitmasks */
69 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
70
71 /* SYSS register bitmasks */
72 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
73
74 #define UART_TI752_TLR_TX 0
75 #define UART_TI752_TLR_RX 4
76
77 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
78 #define TRIGGER_FCR_MASK(x) (x & 3)
79
80 /* Enable XON/XOFF flow control on output */
81 #define OMAP_UART_SW_TX 0x08
82 /* Enable XON/XOFF flow control on input */
83 #define OMAP_UART_SW_RX 0x02
84
85 #define OMAP_UART_WER_MOD_WKUP 0x7f
86 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
87
88 #define TX_TRIGGER 1
89 #define RX_TRIGGER 48
90
91 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
92 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
93
94 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
95
96 #define OMAP_UART_REV_46 0x0406
97 #define OMAP_UART_REV_52 0x0502
98 #define OMAP_UART_REV_63 0x0603
99
100 /* Interrupt Enable Register 2 */
101 #define UART_OMAP_IER2 0x1B
102 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2)
103
104 /* Enhanced features register 2 */
105 #define UART_OMAP_EFR2 0x23
106 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6)
107
108 /* RX FIFO occupancy indicator */
109 #define UART_OMAP_RX_LVL 0x19
110
111 struct omap8250_priv {
112 int line;
113 u8 habit;
114 u8 mdr1;
115 u8 efr;
116 u8 scr;
117 u8 wer;
118 u8 xon;
119 u8 xoff;
120 u8 delayed_restore;
121 u16 quot;
122
123 u8 tx_trigger;
124 u8 rx_trigger;
125 bool is_suspending;
126 int wakeirq;
127 int wakeups_enabled;
128 u32 latency;
129 u32 calc_latency;
130 struct pm_qos_request pm_qos_request;
131 struct work_struct qos_work;
132 struct uart_8250_dma omap8250_dma;
133 spinlock_t rx_dma_lock;
134 bool rx_dma_broken;
135 bool throttled;
136 };
137
138 struct omap8250_dma_params {
139 u32 rx_size;
140 u8 rx_trigger;
141 u8 tx_trigger;
142 };
143
144 struct omap8250_platdata {
145 struct omap8250_dma_params *dma_params;
146 u8 habit;
147 };
148
149 #ifdef CONFIG_SERIAL_8250_DMA
150 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
151 #else
omap_8250_rx_dma_flush(struct uart_8250_port * p)152 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
153 #endif
154
uart_read(struct uart_8250_port * up,u32 reg)155 static u32 uart_read(struct uart_8250_port *up, u32 reg)
156 {
157 return readl(up->port.membase + (reg << up->port.regshift));
158 }
159
160 /*
161 * Called on runtime PM resume path from omap8250_restore_regs(), and
162 * omap8250_set_mctrl().
163 */
__omap8250_set_mctrl(struct uart_port * port,unsigned int mctrl)164 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
165 {
166 struct uart_8250_port *up = up_to_u8250p(port);
167 struct omap8250_priv *priv = up->port.private_data;
168 u8 lcr;
169
170 serial8250_do_set_mctrl(port, mctrl);
171
172 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
173 /*
174 * Turn off autoRTS if RTS is lowered and restore autoRTS
175 * setting if RTS is raised
176 */
177 lcr = serial_in(up, UART_LCR);
178 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
179 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
180 priv->efr |= UART_EFR_RTS;
181 else
182 priv->efr &= ~UART_EFR_RTS;
183 serial_out(up, UART_EFR, priv->efr);
184 serial_out(up, UART_LCR, lcr);
185 }
186 }
187
omap8250_set_mctrl(struct uart_port * port,unsigned int mctrl)188 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
189 {
190 int err;
191
192 err = pm_runtime_resume_and_get(port->dev);
193 if (err)
194 return;
195
196 __omap8250_set_mctrl(port, mctrl);
197
198 pm_runtime_mark_last_busy(port->dev);
199 pm_runtime_put_autosuspend(port->dev);
200 }
201
202 /*
203 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
204 * The access to uart register after MDR1 Access
205 * causes UART to corrupt data.
206 *
207 * Need a delay =
208 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
209 * give 10 times as much
210 */
omap_8250_mdr1_errataset(struct uart_8250_port * up,struct omap8250_priv * priv)211 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
212 struct omap8250_priv *priv)
213 {
214 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
215 udelay(2);
216 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
217 UART_FCR_CLEAR_RCVR);
218 }
219
omap_8250_get_divisor(struct uart_port * port,unsigned int baud,struct omap8250_priv * priv)220 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
221 struct omap8250_priv *priv)
222 {
223 unsigned int uartclk = port->uartclk;
224 unsigned int div_13, div_16;
225 unsigned int abs_d13, abs_d16;
226
227 /*
228 * Old custom speed handling.
229 */
230 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
231 priv->quot = port->custom_divisor & UART_DIV_MAX;
232 /*
233 * I assume that nobody is using this. But hey, if somebody
234 * would like to specify the divisor _and_ the mode then the
235 * driver is ready and waiting for it.
236 */
237 if (port->custom_divisor & (1 << 16))
238 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
239 else
240 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
241 return;
242 }
243 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
244 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
245
246 if (!div_13)
247 div_13 = 1;
248 if (!div_16)
249 div_16 = 1;
250
251 abs_d13 = abs(baud - uartclk / 13 / div_13);
252 abs_d16 = abs(baud - uartclk / 16 / div_16);
253
254 if (abs_d13 >= abs_d16) {
255 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
256 priv->quot = div_16;
257 } else {
258 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
259 priv->quot = div_13;
260 }
261 }
262
omap8250_update_scr(struct uart_8250_port * up,struct omap8250_priv * priv)263 static void omap8250_update_scr(struct uart_8250_port *up,
264 struct omap8250_priv *priv)
265 {
266 u8 old_scr;
267
268 old_scr = serial_in(up, UART_OMAP_SCR);
269 if (old_scr == priv->scr)
270 return;
271
272 /*
273 * The manual recommends not to enable the DMA mode selector in the SCR
274 * (instead of the FCR) register _and_ selecting the DMA mode as one
275 * register write because this may lead to malfunction.
276 */
277 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
278 serial_out(up, UART_OMAP_SCR,
279 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
280 serial_out(up, UART_OMAP_SCR, priv->scr);
281 }
282
omap8250_update_mdr1(struct uart_8250_port * up,struct omap8250_priv * priv)283 static void omap8250_update_mdr1(struct uart_8250_port *up,
284 struct omap8250_priv *priv)
285 {
286 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
287 omap_8250_mdr1_errataset(up, priv);
288 else
289 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
290 }
291
omap8250_restore_regs(struct uart_8250_port * up)292 static void omap8250_restore_regs(struct uart_8250_port *up)
293 {
294 struct omap8250_priv *priv = up->port.private_data;
295 struct uart_8250_dma *dma = up->dma;
296 u8 mcr = serial8250_in_MCR(up);
297
298 if (dma && dma->tx_running) {
299 /*
300 * TCSANOW requests the change to occur immediately however if
301 * we have a TX-DMA operation in progress then it has been
302 * observed that it might stall and never complete. Therefore we
303 * delay DMA completes to prevent this hang from happen.
304 */
305 priv->delayed_restore = 1;
306 return;
307 }
308
309 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
310 serial_out(up, UART_EFR, UART_EFR_ECB);
311
312 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
313 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
314 serial_out(up, UART_FCR, up->fcr);
315
316 omap8250_update_scr(up, priv);
317
318 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
319
320 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
321 OMAP_UART_TCR_HALT(52));
322 serial_out(up, UART_TI752_TLR,
323 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
324 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
325
326 serial_out(up, UART_LCR, 0);
327
328 /* drop TCR + TLR access, we setup XON/XOFF later */
329 serial8250_out_MCR(up, mcr);
330
331 serial_out(up, UART_IER, up->ier);
332
333 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
334 serial_dl_write(up, priv->quot);
335
336 serial_out(up, UART_EFR, priv->efr);
337
338 /* Configure flow control */
339 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
340 serial_out(up, UART_XON1, priv->xon);
341 serial_out(up, UART_XOFF1, priv->xoff);
342
343 serial_out(up, UART_LCR, up->lcr);
344
345 omap8250_update_mdr1(up, priv);
346
347 __omap8250_set_mctrl(&up->port, up->port.mctrl);
348
349 if (up->port.rs485.flags & SER_RS485_ENABLED)
350 serial8250_em485_stop_tx(up);
351 }
352
353 /*
354 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
355 * some differences in how we want to handle flow control.
356 */
omap_8250_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)357 static void omap_8250_set_termios(struct uart_port *port,
358 struct ktermios *termios,
359 struct ktermios *old)
360 {
361 struct uart_8250_port *up = up_to_u8250p(port);
362 struct omap8250_priv *priv = up->port.private_data;
363 unsigned char cval = 0;
364 unsigned int baud;
365
366 switch (termios->c_cflag & CSIZE) {
367 case CS5:
368 cval = UART_LCR_WLEN5;
369 break;
370 case CS6:
371 cval = UART_LCR_WLEN6;
372 break;
373 case CS7:
374 cval = UART_LCR_WLEN7;
375 break;
376 default:
377 case CS8:
378 cval = UART_LCR_WLEN8;
379 break;
380 }
381
382 if (termios->c_cflag & CSTOPB)
383 cval |= UART_LCR_STOP;
384 if (termios->c_cflag & PARENB)
385 cval |= UART_LCR_PARITY;
386 if (!(termios->c_cflag & PARODD))
387 cval |= UART_LCR_EPAR;
388 if (termios->c_cflag & CMSPAR)
389 cval |= UART_LCR_SPAR;
390
391 /*
392 * Ask the core to calculate the divisor for us.
393 */
394 baud = uart_get_baud_rate(port, termios, old,
395 port->uartclk / 16 / UART_DIV_MAX,
396 port->uartclk / 13);
397 omap_8250_get_divisor(port, baud, priv);
398
399 /*
400 * Ok, we're now changing the port state. Do it with
401 * interrupts disabled.
402 */
403 pm_runtime_get_sync(port->dev);
404 spin_lock_irq(&port->lock);
405
406 /*
407 * Update the per-port timeout.
408 */
409 uart_update_timeout(port, termios->c_cflag, baud);
410
411 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
412 if (termios->c_iflag & INPCK)
413 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
414 if (termios->c_iflag & (IGNBRK | PARMRK))
415 up->port.read_status_mask |= UART_LSR_BI;
416
417 /*
418 * Characters to ignore
419 */
420 up->port.ignore_status_mask = 0;
421 if (termios->c_iflag & IGNPAR)
422 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
423 if (termios->c_iflag & IGNBRK) {
424 up->port.ignore_status_mask |= UART_LSR_BI;
425 /*
426 * If we're ignoring parity and break indicators,
427 * ignore overruns too (for real raw support).
428 */
429 if (termios->c_iflag & IGNPAR)
430 up->port.ignore_status_mask |= UART_LSR_OE;
431 }
432
433 /*
434 * ignore all characters if CREAD is not set
435 */
436 if ((termios->c_cflag & CREAD) == 0)
437 up->port.ignore_status_mask |= UART_LSR_DR;
438
439 /*
440 * Modem status interrupts
441 */
442 up->ier &= ~UART_IER_MSI;
443 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
444 up->ier |= UART_IER_MSI;
445
446 up->lcr = cval;
447 /* Up to here it was mostly serial8250_do_set_termios() */
448
449 /*
450 * We enable TRIG_GRANU for RX and TX and additionally we set
451 * SCR_TX_EMPTY bit. The result is the following:
452 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
453 * - less than RX_TRIGGER number of bytes will also cause an interrupt
454 * once the UART decides that there no new bytes arriving.
455 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
456 * empty - the trigger level is ignored here.
457 *
458 * Once DMA is enabled:
459 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
460 * bytes in the TX FIFO. On each assert the DMA engine will move
461 * TX_TRIGGER bytes into the FIFO.
462 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
463 * the FIFO and move RX_TRIGGER bytes.
464 * This is because threshold and trigger values are the same.
465 */
466 up->fcr = UART_FCR_ENABLE_FIFO;
467 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
468 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
469
470 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
471 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
472
473 if (up->dma)
474 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
475 OMAP_UART_SCR_DMAMODE_CTL;
476
477 priv->xon = termios->c_cc[VSTART];
478 priv->xoff = termios->c_cc[VSTOP];
479
480 priv->efr = 0;
481 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
482
483 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
484 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
485 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
486 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
487 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
488 priv->efr |= UART_EFR_CTS;
489 } else if (up->port.flags & UPF_SOFT_FLOW) {
490 /*
491 * OMAP rx s/w flow control is borked; the transmitter remains
492 * stuck off even if rx flow control is subsequently disabled
493 */
494
495 /*
496 * IXOFF Flag:
497 * Enable XON/XOFF flow control on output.
498 * Transmit XON1, XOFF1
499 */
500 if (termios->c_iflag & IXOFF) {
501 up->port.status |= UPSTAT_AUTOXOFF;
502 priv->efr |= OMAP_UART_SW_TX;
503 }
504 }
505 omap8250_restore_regs(up);
506
507 spin_unlock_irq(&up->port.lock);
508 pm_runtime_mark_last_busy(port->dev);
509 pm_runtime_put_autosuspend(port->dev);
510
511 /* calculate wakeup latency constraint */
512 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
513 priv->latency = priv->calc_latency;
514
515 schedule_work(&priv->qos_work);
516
517 /* Don't rewrite B0 */
518 if (tty_termios_baud_rate(termios))
519 tty_termios_encode_baud_rate(termios, baud, baud);
520 }
521
522 /* same as 8250 except that we may have extra flow bits set in EFR */
omap_8250_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)523 static void omap_8250_pm(struct uart_port *port, unsigned int state,
524 unsigned int oldstate)
525 {
526 struct uart_8250_port *up = up_to_u8250p(port);
527 u8 efr;
528
529 pm_runtime_get_sync(port->dev);
530 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
531 efr = serial_in(up, UART_EFR);
532 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
533 serial_out(up, UART_LCR, 0);
534
535 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
536 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
537 serial_out(up, UART_EFR, efr);
538 serial_out(up, UART_LCR, 0);
539
540 pm_runtime_mark_last_busy(port->dev);
541 pm_runtime_put_autosuspend(port->dev);
542 }
543
omap_serial_fill_features_erratas(struct uart_8250_port * up,struct omap8250_priv * priv)544 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
545 struct omap8250_priv *priv)
546 {
547 const struct soc_device_attribute k3_soc_devices[] = {
548 { .family = "AM65X", },
549 { .family = "J721E", .revision = "SR1.0" },
550 { /* sentinel */ }
551 };
552 u32 mvr, scheme;
553 u16 revision, major, minor;
554
555 mvr = uart_read(up, UART_OMAP_MVER);
556
557 /* Check revision register scheme */
558 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
559
560 switch (scheme) {
561 case 0: /* Legacy Scheme: OMAP2/3 */
562 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
563 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
564 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
565 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
566 break;
567 case 1:
568 /* New Scheme: OMAP4+ */
569 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
570 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
571 OMAP_UART_MVR_MAJ_SHIFT;
572 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
573 break;
574 default:
575 dev_warn(up->port.dev,
576 "Unknown revision, defaulting to highest\n");
577 /* highest possible revision */
578 major = 0xff;
579 minor = 0xff;
580 }
581 /* normalize revision for the driver */
582 revision = UART_BUILD_REVISION(major, minor);
583
584 switch (revision) {
585 case OMAP_UART_REV_46:
586 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
587 break;
588 case OMAP_UART_REV_52:
589 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
590 OMAP_UART_WER_HAS_TX_WAKEUP;
591 break;
592 case OMAP_UART_REV_63:
593 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
594 OMAP_UART_WER_HAS_TX_WAKEUP;
595 break;
596 default:
597 break;
598 }
599
600 /*
601 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
602 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
603 * to enable errata workaround.
604 */
605 if (soc_device_match(k3_soc_devices))
606 priv->habit &= ~UART_HAS_RHR_IT_DIS;
607 }
608
omap8250_uart_qos_work(struct work_struct * work)609 static void omap8250_uart_qos_work(struct work_struct *work)
610 {
611 struct omap8250_priv *priv;
612
613 priv = container_of(work, struct omap8250_priv, qos_work);
614 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
615 }
616
617 #ifdef CONFIG_SERIAL_8250_DMA
618 static int omap_8250_dma_handle_irq(struct uart_port *port);
619 #endif
620
omap8250_irq(int irq,void * dev_id)621 static irqreturn_t omap8250_irq(int irq, void *dev_id)
622 {
623 struct uart_port *port = dev_id;
624 struct omap8250_priv *priv = port->private_data;
625 struct uart_8250_port *up = up_to_u8250p(port);
626 unsigned int iir, lsr;
627 int ret;
628
629 #ifdef CONFIG_SERIAL_8250_DMA
630 if (up->dma) {
631 ret = omap_8250_dma_handle_irq(port);
632 return IRQ_RETVAL(ret);
633 }
634 #endif
635
636 serial8250_rpm_get(up);
637 lsr = serial_port_in(port, UART_LSR);
638 iir = serial_port_in(port, UART_IIR);
639 ret = serial8250_handle_irq(port, iir);
640
641 /*
642 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
643 * FIFO has been drained, in which case a dummy read of RX FIFO
644 * is required to clear RX TIMEOUT condition.
645 */
646 if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
647 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
648 serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
649 serial_port_in(port, UART_RX);
650 }
651
652 /* Stop processing interrupts on input overrun */
653 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
654 unsigned long delay;
655
656 up->ier = port->serial_in(port, UART_IER);
657 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
658 port->ops->stop_rx(port);
659 } else {
660 /* Keep restarting the timer until
661 * the input overrun subsides.
662 */
663 cancel_delayed_work(&up->overrun_backoff);
664 }
665
666 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
667 schedule_delayed_work(&up->overrun_backoff, delay);
668 }
669
670 serial8250_rpm_put(up);
671
672 return IRQ_RETVAL(ret);
673 }
674
omap_8250_startup(struct uart_port * port)675 static int omap_8250_startup(struct uart_port *port)
676 {
677 struct uart_8250_port *up = up_to_u8250p(port);
678 struct omap8250_priv *priv = port->private_data;
679 int ret;
680
681 if (priv->wakeirq) {
682 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
683 if (ret)
684 return ret;
685 }
686
687 pm_runtime_get_sync(port->dev);
688
689 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
690
691 serial_out(up, UART_LCR, UART_LCR_WLEN8);
692
693 up->lsr_saved_flags = 0;
694 up->msr_saved_flags = 0;
695
696 /* Disable DMA for console UART */
697 if (uart_console(port))
698 up->dma = NULL;
699
700 if (up->dma) {
701 ret = serial8250_request_dma(up);
702 if (ret) {
703 dev_warn_ratelimited(port->dev,
704 "failed to request DMA\n");
705 up->dma = NULL;
706 }
707 }
708
709 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
710 dev_name(port->dev), port);
711 if (ret < 0)
712 goto err;
713
714 up->ier = UART_IER_RLSI | UART_IER_RDI;
715 serial_out(up, UART_IER, up->ier);
716
717 #ifdef CONFIG_PM
718 up->capabilities |= UART_CAP_RPM;
719 #endif
720
721 /* Enable module level wake up */
722 priv->wer = OMAP_UART_WER_MOD_WKUP;
723 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
724 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
725 serial_out(up, UART_OMAP_WER, priv->wer);
726
727 if (up->dma && !(priv->habit & UART_HAS_EFR2))
728 up->dma->rx_dma(up);
729
730 pm_runtime_mark_last_busy(port->dev);
731 pm_runtime_put_autosuspend(port->dev);
732 return 0;
733 err:
734 pm_runtime_mark_last_busy(port->dev);
735 pm_runtime_put_autosuspend(port->dev);
736 dev_pm_clear_wake_irq(port->dev);
737 return ret;
738 }
739
omap_8250_shutdown(struct uart_port * port)740 static void omap_8250_shutdown(struct uart_port *port)
741 {
742 struct uart_8250_port *up = up_to_u8250p(port);
743 struct omap8250_priv *priv = port->private_data;
744
745 flush_work(&priv->qos_work);
746 if (up->dma)
747 omap_8250_rx_dma_flush(up);
748
749 pm_runtime_get_sync(port->dev);
750
751 serial_out(up, UART_OMAP_WER, 0);
752 if (priv->habit & UART_HAS_EFR2)
753 serial_out(up, UART_OMAP_EFR2, 0x0);
754
755 up->ier = 0;
756 serial_out(up, UART_IER, 0);
757
758 if (up->dma)
759 serial8250_release_dma(up);
760
761 /*
762 * Disable break condition and FIFOs
763 */
764 if (up->lcr & UART_LCR_SBC)
765 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
766 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
767
768 pm_runtime_mark_last_busy(port->dev);
769 pm_runtime_put_autosuspend(port->dev);
770 free_irq(port->irq, port);
771 dev_pm_clear_wake_irq(port->dev);
772 }
773
omap_8250_throttle(struct uart_port * port)774 static void omap_8250_throttle(struct uart_port *port)
775 {
776 struct omap8250_priv *priv = port->private_data;
777 unsigned long flags;
778
779 pm_runtime_get_sync(port->dev);
780
781 spin_lock_irqsave(&port->lock, flags);
782 port->ops->stop_rx(port);
783 priv->throttled = true;
784 spin_unlock_irqrestore(&port->lock, flags);
785
786 pm_runtime_mark_last_busy(port->dev);
787 pm_runtime_put_autosuspend(port->dev);
788 }
789
omap_8250_unthrottle(struct uart_port * port)790 static void omap_8250_unthrottle(struct uart_port *port)
791 {
792 struct omap8250_priv *priv = port->private_data;
793 struct uart_8250_port *up = up_to_u8250p(port);
794 unsigned long flags;
795
796 pm_runtime_get_sync(port->dev);
797
798 spin_lock_irqsave(&port->lock, flags);
799 priv->throttled = false;
800 if (up->dma)
801 up->dma->rx_dma(up);
802 up->ier |= UART_IER_RLSI | UART_IER_RDI;
803 port->read_status_mask |= UART_LSR_DR;
804 serial_out(up, UART_IER, up->ier);
805 spin_unlock_irqrestore(&port->lock, flags);
806
807 pm_runtime_mark_last_busy(port->dev);
808 pm_runtime_put_autosuspend(port->dev);
809 }
810
811 #ifdef CONFIG_SERIAL_8250_DMA
812 static int omap_8250_rx_dma(struct uart_8250_port *p);
813
814 /* Must be called while priv->rx_dma_lock is held */
__dma_rx_do_complete(struct uart_8250_port * p)815 static void __dma_rx_do_complete(struct uart_8250_port *p)
816 {
817 struct uart_8250_dma *dma = p->dma;
818 struct tty_port *tty_port = &p->port.state->port;
819 struct omap8250_priv *priv = p->port.private_data;
820 struct dma_chan *rxchan = dma->rxchan;
821 dma_cookie_t cookie;
822 struct dma_tx_state state;
823 int count;
824 int ret;
825 u32 reg;
826
827 if (!dma->rx_running)
828 goto out;
829
830 cookie = dma->rx_cookie;
831 dma->rx_running = 0;
832
833 /* Re-enable RX FIFO interrupt now that transfer is complete */
834 if (priv->habit & UART_HAS_RHR_IT_DIS) {
835 reg = serial_in(p, UART_OMAP_IER2);
836 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
837 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
838 }
839
840 dmaengine_tx_status(rxchan, cookie, &state);
841
842 count = dma->rx_size - state.residue + state.in_flight_bytes;
843 if (count < dma->rx_size) {
844 dmaengine_terminate_async(rxchan);
845
846 /*
847 * Poll for teardown to complete which guarantees in
848 * flight data is drained.
849 */
850 if (state.in_flight_bytes) {
851 int poll_count = 25;
852
853 while (dmaengine_tx_status(rxchan, cookie, NULL) &&
854 poll_count--)
855 cpu_relax();
856
857 if (poll_count == -1)
858 dev_err(p->port.dev, "teardown incomplete\n");
859 }
860 }
861 if (!count)
862 goto out;
863 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
864
865 p->port.icount.rx += ret;
866 p->port.icount.buf_overrun += count - ret;
867 out:
868
869 tty_flip_buffer_push(tty_port);
870 }
871
__dma_rx_complete(void * param)872 static void __dma_rx_complete(void *param)
873 {
874 struct uart_8250_port *p = param;
875 struct omap8250_priv *priv = p->port.private_data;
876 struct uart_8250_dma *dma = p->dma;
877 struct dma_tx_state state;
878 unsigned long flags;
879
880 spin_lock_irqsave(&p->port.lock, flags);
881
882 /*
883 * If the tx status is not DMA_COMPLETE, then this is a delayed
884 * completion callback. A previous RX timeout flush would have
885 * already pushed the data, so exit.
886 */
887 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
888 DMA_COMPLETE) {
889 spin_unlock_irqrestore(&p->port.lock, flags);
890 return;
891 }
892 __dma_rx_do_complete(p);
893 if (!priv->throttled) {
894 p->ier |= UART_IER_RLSI | UART_IER_RDI;
895 serial_out(p, UART_IER, p->ier);
896 if (!(priv->habit & UART_HAS_EFR2))
897 omap_8250_rx_dma(p);
898 }
899
900 spin_unlock_irqrestore(&p->port.lock, flags);
901 }
902
omap_8250_rx_dma_flush(struct uart_8250_port * p)903 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
904 {
905 struct omap8250_priv *priv = p->port.private_data;
906 struct uart_8250_dma *dma = p->dma;
907 struct dma_tx_state state;
908 unsigned long flags;
909 int ret;
910
911 spin_lock_irqsave(&priv->rx_dma_lock, flags);
912
913 if (!dma->rx_running) {
914 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
915 return;
916 }
917
918 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
919 if (ret == DMA_IN_PROGRESS) {
920 ret = dmaengine_pause(dma->rxchan);
921 if (WARN_ON_ONCE(ret))
922 priv->rx_dma_broken = true;
923 }
924 __dma_rx_do_complete(p);
925 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
926 }
927
omap_8250_rx_dma(struct uart_8250_port * p)928 static int omap_8250_rx_dma(struct uart_8250_port *p)
929 {
930 struct omap8250_priv *priv = p->port.private_data;
931 struct uart_8250_dma *dma = p->dma;
932 int err = 0;
933 struct dma_async_tx_descriptor *desc;
934 unsigned long flags;
935 u32 reg;
936
937 if (priv->rx_dma_broken)
938 return -EINVAL;
939
940 spin_lock_irqsave(&priv->rx_dma_lock, flags);
941
942 if (dma->rx_running) {
943 enum dma_status state;
944
945 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
946 if (state == DMA_COMPLETE) {
947 /*
948 * Disable RX interrupts to allow RX DMA completion
949 * callback to run.
950 */
951 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
952 serial_out(p, UART_IER, p->ier);
953 }
954 goto out;
955 }
956
957 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
958 dma->rx_size, DMA_DEV_TO_MEM,
959 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
960 if (!desc) {
961 err = -EBUSY;
962 goto out;
963 }
964
965 dma->rx_running = 1;
966 desc->callback = __dma_rx_complete;
967 desc->callback_param = p;
968
969 dma->rx_cookie = dmaengine_submit(desc);
970
971 /*
972 * Disable RX FIFO interrupt while RX DMA is enabled, else
973 * spurious interrupt may be raised when data is in the RX FIFO
974 * but is yet to be drained by DMA.
975 */
976 if (priv->habit & UART_HAS_RHR_IT_DIS) {
977 reg = serial_in(p, UART_OMAP_IER2);
978 reg |= UART_OMAP_IER2_RHR_IT_DIS;
979 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
980 }
981
982 dma_async_issue_pending(dma->rxchan);
983 out:
984 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
985 return err;
986 }
987
988 static int omap_8250_tx_dma(struct uart_8250_port *p);
989
omap_8250_dma_tx_complete(void * param)990 static void omap_8250_dma_tx_complete(void *param)
991 {
992 struct uart_8250_port *p = param;
993 struct uart_8250_dma *dma = p->dma;
994 struct circ_buf *xmit = &p->port.state->xmit;
995 unsigned long flags;
996 bool en_thri = false;
997 struct omap8250_priv *priv = p->port.private_data;
998
999 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
1000 UART_XMIT_SIZE, DMA_TO_DEVICE);
1001
1002 spin_lock_irqsave(&p->port.lock, flags);
1003
1004 dma->tx_running = 0;
1005
1006 xmit->tail += dma->tx_size;
1007 xmit->tail &= UART_XMIT_SIZE - 1;
1008 p->port.icount.tx += dma->tx_size;
1009
1010 if (priv->delayed_restore) {
1011 priv->delayed_restore = 0;
1012 omap8250_restore_regs(p);
1013 }
1014
1015 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1016 uart_write_wakeup(&p->port);
1017
1018 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1019 int ret;
1020
1021 ret = omap_8250_tx_dma(p);
1022 if (ret)
1023 en_thri = true;
1024 } else if (p->capabilities & UART_CAP_RPM) {
1025 en_thri = true;
1026 }
1027
1028 if (en_thri) {
1029 dma->tx_err = 1;
1030 serial8250_set_THRI(p);
1031 }
1032
1033 spin_unlock_irqrestore(&p->port.lock, flags);
1034 }
1035
omap_8250_tx_dma(struct uart_8250_port * p)1036 static int omap_8250_tx_dma(struct uart_8250_port *p)
1037 {
1038 struct uart_8250_dma *dma = p->dma;
1039 struct omap8250_priv *priv = p->port.private_data;
1040 struct circ_buf *xmit = &p->port.state->xmit;
1041 struct dma_async_tx_descriptor *desc;
1042 unsigned int skip_byte = 0;
1043 int ret;
1044
1045 if (dma->tx_running)
1046 return 0;
1047 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1048
1049 /*
1050 * Even if no data, we need to return an error for the two cases
1051 * below so serial8250_tx_chars() is invoked and properly clears
1052 * THRI and/or runtime suspend.
1053 */
1054 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1055 ret = -EBUSY;
1056 goto err;
1057 }
1058 serial8250_clear_THRI(p);
1059 return 0;
1060 }
1061
1062 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1063 if (priv->habit & OMAP_DMA_TX_KICK) {
1064 u8 tx_lvl;
1065
1066 /*
1067 * We need to put the first byte into the FIFO in order to start
1068 * the DMA transfer. For transfers smaller than four bytes we
1069 * don't bother doing DMA at all. It seem not matter if there
1070 * are still bytes in the FIFO from the last transfer (in case
1071 * we got here directly from omap_8250_dma_tx_complete()). Bytes
1072 * leaving the FIFO seem not to trigger the DMA transfer. It is
1073 * really the byte that we put into the FIFO.
1074 * If the FIFO is already full then we most likely got here from
1075 * omap_8250_dma_tx_complete(). And this means the DMA engine
1076 * just completed its work. We don't have to wait the complete
1077 * 86us at 115200,8n1 but around 60us (not to mention lower
1078 * baudrates). So in that case we take the interrupt and try
1079 * again with an empty FIFO.
1080 */
1081 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1082 if (tx_lvl == p->tx_loadsz) {
1083 ret = -EBUSY;
1084 goto err;
1085 }
1086 if (dma->tx_size < 4) {
1087 ret = -EINVAL;
1088 goto err;
1089 }
1090 skip_byte = 1;
1091 }
1092
1093 desc = dmaengine_prep_slave_single(dma->txchan,
1094 dma->tx_addr + xmit->tail + skip_byte,
1095 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1096 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1097 if (!desc) {
1098 ret = -EBUSY;
1099 goto err;
1100 }
1101
1102 dma->tx_running = 1;
1103
1104 desc->callback = omap_8250_dma_tx_complete;
1105 desc->callback_param = p;
1106
1107 dma->tx_cookie = dmaengine_submit(desc);
1108
1109 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1110 UART_XMIT_SIZE, DMA_TO_DEVICE);
1111
1112 dma_async_issue_pending(dma->txchan);
1113 if (dma->tx_err)
1114 dma->tx_err = 0;
1115
1116 serial8250_clear_THRI(p);
1117 if (skip_byte)
1118 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1119 return 0;
1120 err:
1121 dma->tx_err = 1;
1122 return ret;
1123 }
1124
handle_rx_dma(struct uart_8250_port * up,unsigned int iir)1125 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1126 {
1127 switch (iir & 0x3f) {
1128 case UART_IIR_RLSI:
1129 case UART_IIR_RX_TIMEOUT:
1130 case UART_IIR_RDI:
1131 omap_8250_rx_dma_flush(up);
1132 return true;
1133 }
1134 return omap_8250_rx_dma(up);
1135 }
1136
omap_8250_handle_rx_dma(struct uart_8250_port * up,u8 iir,unsigned char status)1137 static unsigned char omap_8250_handle_rx_dma(struct uart_8250_port *up,
1138 u8 iir, unsigned char status)
1139 {
1140 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1141 (iir & UART_IIR_RDI)) {
1142 if (handle_rx_dma(up, iir)) {
1143 status = serial8250_rx_chars(up, status);
1144 omap_8250_rx_dma(up);
1145 }
1146 }
1147
1148 return status;
1149 }
1150
am654_8250_handle_rx_dma(struct uart_8250_port * up,u8 iir,unsigned char status)1151 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1152 unsigned char status)
1153 {
1154 /*
1155 * Queue a new transfer if FIFO has data.
1156 */
1157 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1158 (up->ier & UART_IER_RDI)) {
1159 omap_8250_rx_dma(up);
1160 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1161 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1162 /*
1163 * Disable RX timeout, read IIR to clear
1164 * current timeout condition, clear EFR2 to
1165 * periodic timeouts, re-enable interrupts.
1166 */
1167 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1168 serial_out(up, UART_IER, up->ier);
1169 omap_8250_rx_dma_flush(up);
1170 serial_in(up, UART_IIR);
1171 serial_out(up, UART_OMAP_EFR2, 0x0);
1172 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1173 serial_out(up, UART_IER, up->ier);
1174 }
1175 }
1176
1177 /*
1178 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1179 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1180 * use the default routine in the non-DMA case and this one for with DMA.
1181 */
omap_8250_dma_handle_irq(struct uart_port * port)1182 static int omap_8250_dma_handle_irq(struct uart_port *port)
1183 {
1184 struct uart_8250_port *up = up_to_u8250p(port);
1185 struct omap8250_priv *priv = up->port.private_data;
1186 unsigned char status;
1187 unsigned long flags;
1188 u8 iir;
1189
1190 serial8250_rpm_get(up);
1191
1192 iir = serial_port_in(port, UART_IIR);
1193 if (iir & UART_IIR_NO_INT) {
1194 serial8250_rpm_put(up);
1195 return IRQ_HANDLED;
1196 }
1197
1198 spin_lock_irqsave(&port->lock, flags);
1199
1200 status = serial_port_in(port, UART_LSR);
1201
1202 if (priv->habit & UART_HAS_EFR2)
1203 am654_8250_handle_rx_dma(up, iir, status);
1204 else
1205 status = omap_8250_handle_rx_dma(up, iir, status);
1206
1207 serial8250_modem_status(up);
1208 if (status & UART_LSR_THRE && up->dma->tx_err) {
1209 if (uart_tx_stopped(&up->port) ||
1210 uart_circ_empty(&up->port.state->xmit)) {
1211 up->dma->tx_err = 0;
1212 serial8250_tx_chars(up);
1213 } else {
1214 /*
1215 * try again due to an earlier failer which
1216 * might have been resolved by now.
1217 */
1218 if (omap_8250_tx_dma(up))
1219 serial8250_tx_chars(up);
1220 }
1221 }
1222
1223 uart_unlock_and_check_sysrq(port, flags);
1224 serial8250_rpm_put(up);
1225 return 1;
1226 }
1227
the_no_dma_filter_fn(struct dma_chan * chan,void * param)1228 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1229 {
1230 return false;
1231 }
1232
1233 #else
1234
omap_8250_rx_dma(struct uart_8250_port * p)1235 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1236 {
1237 return -EINVAL;
1238 }
1239 #endif
1240
omap8250_no_handle_irq(struct uart_port * port)1241 static int omap8250_no_handle_irq(struct uart_port *port)
1242 {
1243 /* IRQ has not been requested but handling irq? */
1244 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1245 return 0;
1246 }
1247
1248 static struct omap8250_dma_params am654_dma = {
1249 .rx_size = SZ_2K,
1250 .rx_trigger = 1,
1251 .tx_trigger = TX_TRIGGER,
1252 };
1253
1254 static struct omap8250_dma_params am33xx_dma = {
1255 .rx_size = RX_TRIGGER,
1256 .rx_trigger = RX_TRIGGER,
1257 .tx_trigger = TX_TRIGGER,
1258 };
1259
1260 static struct omap8250_platdata am654_platdata = {
1261 .dma_params = &am654_dma,
1262 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1263 UART_RX_TIMEOUT_QUIRK,
1264 };
1265
1266 static struct omap8250_platdata am33xx_platdata = {
1267 .dma_params = &am33xx_dma,
1268 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1269 };
1270
1271 static struct omap8250_platdata omap4_platdata = {
1272 .dma_params = &am33xx_dma,
1273 .habit = UART_ERRATA_CLOCK_DISABLE,
1274 };
1275
1276 static const struct of_device_id omap8250_dt_ids[] = {
1277 { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1278 { .compatible = "ti,omap2-uart" },
1279 { .compatible = "ti,omap3-uart" },
1280 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1281 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1282 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1283 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1284 {},
1285 };
1286 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1287
omap8250_probe(struct platform_device * pdev)1288 static int omap8250_probe(struct platform_device *pdev)
1289 {
1290 struct device_node *np = pdev->dev.of_node;
1291 struct omap8250_priv *priv;
1292 const struct omap8250_platdata *pdata;
1293 struct uart_8250_port up;
1294 struct resource *regs;
1295 void __iomem *membase;
1296 int irq, ret;
1297
1298 irq = platform_get_irq(pdev, 0);
1299 if (irq < 0)
1300 return irq;
1301
1302 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1303 if (!regs) {
1304 dev_err(&pdev->dev, "missing registers\n");
1305 return -EINVAL;
1306 }
1307
1308 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1309 if (!priv)
1310 return -ENOMEM;
1311
1312 membase = devm_ioremap(&pdev->dev, regs->start,
1313 resource_size(regs));
1314 if (!membase)
1315 return -ENODEV;
1316
1317 memset(&up, 0, sizeof(up));
1318 up.port.dev = &pdev->dev;
1319 up.port.mapbase = regs->start;
1320 up.port.membase = membase;
1321 up.port.irq = irq;
1322 /*
1323 * It claims to be 16C750 compatible however it is a little different.
1324 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1325 * have) is enabled via EFR instead of MCR. The type is set here 8250
1326 * just to get things going. UNKNOWN does not work for a few reasons and
1327 * we don't need our own type since we don't use 8250's set_termios()
1328 * or pm callback.
1329 */
1330 up.port.type = PORT_8250;
1331 up.port.iotype = UPIO_MEM;
1332 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1333 UPF_HARD_FLOW;
1334 up.port.private_data = priv;
1335
1336 up.port.regshift = 2;
1337 up.port.fifosize = 64;
1338 up.tx_loadsz = 64;
1339 up.capabilities = UART_CAP_FIFO;
1340 #ifdef CONFIG_PM
1341 /*
1342 * Runtime PM is mostly transparent. However to do it right we need to a
1343 * TX empty interrupt before we can put the device to auto idle. So if
1344 * PM is not enabled we don't add that flag and can spare that one extra
1345 * interrupt in the TX path.
1346 */
1347 up.capabilities |= UART_CAP_RPM;
1348 #endif
1349 up.port.set_termios = omap_8250_set_termios;
1350 up.port.set_mctrl = omap8250_set_mctrl;
1351 up.port.pm = omap_8250_pm;
1352 up.port.startup = omap_8250_startup;
1353 up.port.shutdown = omap_8250_shutdown;
1354 up.port.throttle = omap_8250_throttle;
1355 up.port.unthrottle = omap_8250_unthrottle;
1356 up.port.rs485_config = serial8250_em485_config;
1357 up.rs485_start_tx = serial8250_em485_start_tx;
1358 up.rs485_stop_tx = serial8250_em485_stop_tx;
1359 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1360
1361 ret = of_alias_get_id(np, "serial");
1362 if (ret < 0) {
1363 dev_err(&pdev->dev, "failed to get alias\n");
1364 return ret;
1365 }
1366 up.port.line = ret;
1367
1368 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1369 struct clk *clk;
1370
1371 clk = devm_clk_get(&pdev->dev, NULL);
1372 if (IS_ERR(clk)) {
1373 if (PTR_ERR(clk) == -EPROBE_DEFER)
1374 return -EPROBE_DEFER;
1375 } else {
1376 up.port.uartclk = clk_get_rate(clk);
1377 }
1378 }
1379
1380 if (of_property_read_u32(np, "overrun-throttle-ms",
1381 &up.overrun_backoff_time_ms) != 0)
1382 up.overrun_backoff_time_ms = 0;
1383
1384 priv->wakeirq = irq_of_parse_and_map(np, 1);
1385
1386 pdata = of_device_get_match_data(&pdev->dev);
1387 if (pdata)
1388 priv->habit |= pdata->habit;
1389
1390 if (!up.port.uartclk) {
1391 up.port.uartclk = DEFAULT_CLK_SPEED;
1392 dev_warn(&pdev->dev,
1393 "No clock speed specified: using default: %d\n",
1394 DEFAULT_CLK_SPEED);
1395 }
1396
1397 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1398 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1399 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1400 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1401
1402 spin_lock_init(&priv->rx_dma_lock);
1403
1404 device_init_wakeup(&pdev->dev, true);
1405 pm_runtime_enable(&pdev->dev);
1406 pm_runtime_use_autosuspend(&pdev->dev);
1407
1408 /*
1409 * Disable runtime PM until autosuspend delay unless specifically
1410 * enabled by the user via sysfs. This is the historic way to
1411 * prevent an unsafe default policy with lossy characters on wake-up.
1412 * For serdev devices this is not needed, the policy can be managed by
1413 * the serdev driver.
1414 */
1415 if (!of_get_available_child_count(pdev->dev.of_node))
1416 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1417
1418 pm_runtime_irq_safe(&pdev->dev);
1419
1420 pm_runtime_get_sync(&pdev->dev);
1421
1422 omap_serial_fill_features_erratas(&up, priv);
1423 up.port.handle_irq = omap8250_no_handle_irq;
1424 priv->rx_trigger = RX_TRIGGER;
1425 priv->tx_trigger = TX_TRIGGER;
1426 #ifdef CONFIG_SERIAL_8250_DMA
1427 /*
1428 * Oh DMA support. If there are no DMA properties in the DT then
1429 * we will fall back to a generic DMA channel which does not
1430 * really work here. To ensure that we do not get a generic DMA
1431 * channel assigned, we have the the_no_dma_filter_fn() here.
1432 * To avoid "failed to request DMA" messages we check for DMA
1433 * properties in DT.
1434 */
1435 ret = of_property_count_strings(np, "dma-names");
1436 if (ret == 2) {
1437 struct omap8250_dma_params *dma_params = NULL;
1438
1439 up.dma = &priv->omap8250_dma;
1440 up.dma->fn = the_no_dma_filter_fn;
1441 up.dma->tx_dma = omap_8250_tx_dma;
1442 up.dma->rx_dma = omap_8250_rx_dma;
1443 if (pdata)
1444 dma_params = pdata->dma_params;
1445
1446 if (dma_params) {
1447 up.dma->rx_size = dma_params->rx_size;
1448 up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
1449 up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
1450 priv->rx_trigger = dma_params->rx_trigger;
1451 priv->tx_trigger = dma_params->tx_trigger;
1452 } else {
1453 up.dma->rx_size = RX_TRIGGER;
1454 up.dma->rxconf.src_maxburst = RX_TRIGGER;
1455 up.dma->txconf.dst_maxburst = TX_TRIGGER;
1456 }
1457 }
1458 #endif
1459 ret = serial8250_register_8250_port(&up);
1460 if (ret < 0) {
1461 dev_err(&pdev->dev, "unable to register 8250 port\n");
1462 goto err;
1463 }
1464 priv->line = ret;
1465 platform_set_drvdata(pdev, priv);
1466 pm_runtime_mark_last_busy(&pdev->dev);
1467 pm_runtime_put_autosuspend(&pdev->dev);
1468 return 0;
1469 err:
1470 pm_runtime_dont_use_autosuspend(&pdev->dev);
1471 pm_runtime_put_sync(&pdev->dev);
1472 pm_runtime_disable(&pdev->dev);
1473 return ret;
1474 }
1475
omap8250_remove(struct platform_device * pdev)1476 static int omap8250_remove(struct platform_device *pdev)
1477 {
1478 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1479 int err;
1480
1481 err = pm_runtime_resume_and_get(&pdev->dev);
1482 if (err)
1483 return err;
1484
1485 pm_runtime_dont_use_autosuspend(&pdev->dev);
1486 pm_runtime_put_sync(&pdev->dev);
1487 flush_work(&priv->qos_work);
1488 pm_runtime_disable(&pdev->dev);
1489 serial8250_unregister_port(priv->line);
1490 cpu_latency_qos_remove_request(&priv->pm_qos_request);
1491 device_init_wakeup(&pdev->dev, false);
1492 return 0;
1493 }
1494
1495 #ifdef CONFIG_PM_SLEEP
omap8250_prepare(struct device * dev)1496 static int omap8250_prepare(struct device *dev)
1497 {
1498 struct omap8250_priv *priv = dev_get_drvdata(dev);
1499
1500 if (!priv)
1501 return 0;
1502 priv->is_suspending = true;
1503 return 0;
1504 }
1505
omap8250_complete(struct device * dev)1506 static void omap8250_complete(struct device *dev)
1507 {
1508 struct omap8250_priv *priv = dev_get_drvdata(dev);
1509
1510 if (!priv)
1511 return;
1512 priv->is_suspending = false;
1513 }
1514
omap8250_suspend(struct device * dev)1515 static int omap8250_suspend(struct device *dev)
1516 {
1517 struct omap8250_priv *priv = dev_get_drvdata(dev);
1518 struct uart_8250_port *up = serial8250_get_port(priv->line);
1519
1520 serial8250_suspend_port(priv->line);
1521
1522 pm_runtime_get_sync(dev);
1523 if (!device_may_wakeup(dev))
1524 priv->wer = 0;
1525 serial_out(up, UART_OMAP_WER, priv->wer);
1526 pm_runtime_mark_last_busy(dev);
1527 pm_runtime_put_autosuspend(dev);
1528
1529 flush_work(&priv->qos_work);
1530 return 0;
1531 }
1532
omap8250_resume(struct device * dev)1533 static int omap8250_resume(struct device *dev)
1534 {
1535 struct omap8250_priv *priv = dev_get_drvdata(dev);
1536
1537 serial8250_resume_port(priv->line);
1538 return 0;
1539 }
1540 #else
1541 #define omap8250_prepare NULL
1542 #define omap8250_complete NULL
1543 #endif
1544
1545 #ifdef CONFIG_PM
omap8250_lost_context(struct uart_8250_port * up)1546 static int omap8250_lost_context(struct uart_8250_port *up)
1547 {
1548 u32 val;
1549
1550 val = serial_in(up, UART_OMAP_SCR);
1551 /*
1552 * If we lose context, then SCR is set to its reset value of zero.
1553 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1554 * among other bits, to never set the register back to zero again.
1555 */
1556 if (!val)
1557 return 1;
1558 return 0;
1559 }
1560
1561 /* TODO: in future, this should happen via API in drivers/reset/ */
omap8250_soft_reset(struct device * dev)1562 static int omap8250_soft_reset(struct device *dev)
1563 {
1564 struct omap8250_priv *priv = dev_get_drvdata(dev);
1565 struct uart_8250_port *up = serial8250_get_port(priv->line);
1566 int timeout = 100;
1567 int sysc;
1568 int syss;
1569
1570 /*
1571 * At least on omap4, unused uarts may not idle after reset without
1572 * a basic scr dma configuration even with no dma in use. The
1573 * module clkctrl status bits will be 1 instead of 3 blocking idle
1574 * for the whole clockdomain. The softreset below will clear scr,
1575 * and we restore it on resume so this is safe to do on all SoCs
1576 * needing omap8250_soft_reset() quirk. Do it in two writes as
1577 * recommended in the comment for omap8250_update_scr().
1578 */
1579 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1580 serial_out(up, UART_OMAP_SCR,
1581 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1582
1583 sysc = serial_in(up, UART_OMAP_SYSC);
1584
1585 /* softreset the UART */
1586 sysc |= OMAP_UART_SYSC_SOFTRESET;
1587 serial_out(up, UART_OMAP_SYSC, sysc);
1588
1589 /* By experiments, 1us enough for reset complete on AM335x */
1590 do {
1591 udelay(1);
1592 syss = serial_in(up, UART_OMAP_SYSS);
1593 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1594
1595 if (!timeout) {
1596 dev_err(dev, "timed out waiting for reset done\n");
1597 return -ETIMEDOUT;
1598 }
1599
1600 return 0;
1601 }
1602
omap8250_runtime_suspend(struct device * dev)1603 static int omap8250_runtime_suspend(struct device *dev)
1604 {
1605 struct omap8250_priv *priv = dev_get_drvdata(dev);
1606 struct uart_8250_port *up;
1607
1608 /* In case runtime-pm tries this before we are setup */
1609 if (!priv)
1610 return 0;
1611
1612 up = serial8250_get_port(priv->line);
1613 /*
1614 * When using 'no_console_suspend', the console UART must not be
1615 * suspended. Since driver suspend is managed by runtime suspend,
1616 * preventing runtime suspend (by returning error) will keep device
1617 * active during suspend.
1618 */
1619 if (priv->is_suspending && !console_suspend_enabled) {
1620 if (uart_console(&up->port))
1621 return -EBUSY;
1622 }
1623
1624 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1625 int ret;
1626
1627 ret = omap8250_soft_reset(dev);
1628 if (ret)
1629 return ret;
1630
1631 /* Restore to UART mode after reset (for wakeup) */
1632 omap8250_update_mdr1(up, priv);
1633 /* Restore wakeup enable register */
1634 serial_out(up, UART_OMAP_WER, priv->wer);
1635 }
1636
1637 if (up->dma && up->dma->rxchan)
1638 omap_8250_rx_dma_flush(up);
1639
1640 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1641 schedule_work(&priv->qos_work);
1642
1643 return 0;
1644 }
1645
omap8250_runtime_resume(struct device * dev)1646 static int omap8250_runtime_resume(struct device *dev)
1647 {
1648 struct omap8250_priv *priv = dev_get_drvdata(dev);
1649 struct uart_8250_port *up;
1650
1651 /* In case runtime-pm tries this before we are setup */
1652 if (!priv)
1653 return 0;
1654
1655 up = serial8250_get_port(priv->line);
1656
1657 if (omap8250_lost_context(up))
1658 omap8250_restore_regs(up);
1659
1660 if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
1661 omap_8250_rx_dma(up);
1662
1663 priv->latency = priv->calc_latency;
1664 schedule_work(&priv->qos_work);
1665 return 0;
1666 }
1667 #endif
1668
1669 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
omap8250_console_fixup(void)1670 static int __init omap8250_console_fixup(void)
1671 {
1672 char *omap_str;
1673 char *options;
1674 u8 idx;
1675
1676 if (strstr(boot_command_line, "console=ttyS"))
1677 /* user set a ttyS based name for the console */
1678 return 0;
1679
1680 omap_str = strstr(boot_command_line, "console=ttyO");
1681 if (!omap_str)
1682 /* user did not set ttyO based console, so we don't care */
1683 return 0;
1684
1685 omap_str += 12;
1686 if ('0' <= *omap_str && *omap_str <= '9')
1687 idx = *omap_str - '0';
1688 else
1689 return 0;
1690
1691 omap_str++;
1692 if (omap_str[0] == ',') {
1693 omap_str++;
1694 options = omap_str;
1695 } else {
1696 options = NULL;
1697 }
1698
1699 add_preferred_console("ttyS", idx, options);
1700 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1701 idx, idx);
1702 pr_err("This ensures that you still see kernel messages. Please\n");
1703 pr_err("update your kernel commandline.\n");
1704 return 0;
1705 }
1706 console_initcall(omap8250_console_fixup);
1707 #endif
1708
1709 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1710 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1711 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1712 omap8250_runtime_resume, NULL)
1713 .prepare = omap8250_prepare,
1714 .complete = omap8250_complete,
1715 };
1716
1717 static struct platform_driver omap8250_platform_driver = {
1718 .driver = {
1719 .name = "omap8250",
1720 .pm = &omap8250_dev_pm_ops,
1721 .of_match_table = omap8250_dt_ids,
1722 },
1723 .probe = omap8250_probe,
1724 .remove = omap8250_remove,
1725 };
1726 module_platform_driver(omap8250_platform_driver);
1727
1728 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1729 MODULE_DESCRIPTION("OMAP 8250 Driver");
1730 MODULE_LICENSE("GPL v2");
1731