1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author:
5 * Zhigang.Wei <zhigang.wei@mediatek.com>
6 * Chunfeng.Yun <chunfeng.yun@mediatek.com>
7 */
8
9 #ifndef _XHCI_MTK_H_
10 #define _XHCI_MTK_H_
11
12 #include "xhci.h"
13
14 /**
15 * To simplify scheduler algorithm, set a upper limit for ESIT,
16 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
17 * round down to the limit value, that means allocating more
18 * bandwidth to it.
19 */
20 #define XHCI_MTK_MAX_ESIT 64
21
22 /**
23 * @fs_bus_bw: array to keep track of bandwidth already used for FS
24 * @ep_list: Endpoints using this TT
25 * @usb_tt: usb TT related
26 * @tt_port: TT port number
27 */
28 struct mu3h_sch_tt {
29 u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
30 struct list_head ep_list;
31 struct usb_tt *usb_tt;
32 int tt_port;
33 };
34
35 /**
36 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
37 *
38 * @bus_bw: array to keep track of bandwidth already used at each uframes
39 * @bw_ep_list: eps in the bandwidth domain
40 *
41 * treat a HS root port as a bandwidth domain, but treat a SS root port as
42 * two bandwidth domains, one for IN eps and another for OUT eps.
43 */
44 struct mu3h_sch_bw_info {
45 u32 bus_bw[XHCI_MTK_MAX_ESIT];
46 struct list_head bw_ep_list;
47 };
48
49 /**
50 * struct mu3h_sch_ep_info: schedule information for endpoint
51 *
52 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
53 * @num_budget_microframes: number of continuous uframes
54 * (@repeat==1) scheduled within the interval
55 * @bw_cost_per_microframe: bandwidth cost per microframe
56 * @endpoint: linked into bandwidth domain which it belongs to
57 * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
58 * @sch_tt: mu3h_sch_tt linked into
59 * @ep_type: endpoint type
60 * @maxpkt: max packet size of endpoint
61 * @ep: address of usb_host_endpoint struct
62 * @allocated: the bandwidth is aready allocated from bus_bw
63 * @offset: which uframe of the interval that transfer should be
64 * scheduled first time within the interval
65 * @repeat: the time gap between two uframes that transfers are
66 * scheduled within a interval. in the simple algorithm, only
67 * assign 0 or 1 to it; 0 means using only one uframe in a
68 * interval, and 1 means using @num_budget_microframes
69 * continuous uframes
70 * @pkts: number of packets to be transferred in the scheduled uframes
71 * @cs_count: number of CS that host will trigger
72 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
73 * distribute the bMaxBurst+1 packets for a single burst
74 * according to @pkts and @repeat, repeate the burst multiple
75 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
76 * according to @pkts and @repeat. normal mode is used by
77 * default
78 * @bw_budget_table: table to record bandwidth budget per microframe
79 */
80 struct mu3h_sch_ep_info {
81 u32 esit;
82 u32 num_budget_microframes;
83 u32 bw_cost_per_microframe;
84 struct list_head endpoint;
85 struct list_head tt_endpoint;
86 struct mu3h_sch_tt *sch_tt;
87 u32 ep_type;
88 u32 maxpkt;
89 void *ep;
90 bool allocated;
91 /*
92 * mtk xHCI scheduling information put into reserved DWs
93 * in ep context
94 */
95 u32 offset;
96 u32 repeat;
97 u32 pkts;
98 u32 cs_count;
99 u32 burst_mode;
100 u32 bw_budget_table[];
101 };
102
103 #define MU3C_U3_PORT_MAX 4
104 #define MU3C_U2_PORT_MAX 5
105
106 /**
107 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
108 * @ip_pw_ctr0~3: ip power and clock control registers
109 * @ip_pw_sts1~2: ip power and clock status registers
110 * @ip_xhci_cap: ip xHCI capability register
111 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
112 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
113 * @u2_phy_pll: usb2 phy pll control register
114 */
115 struct mu3c_ippc_regs {
116 __le32 ip_pw_ctr0;
117 __le32 ip_pw_ctr1;
118 __le32 ip_pw_ctr2;
119 __le32 ip_pw_ctr3;
120 __le32 ip_pw_sts1;
121 __le32 ip_pw_sts2;
122 __le32 reserved0[3];
123 __le32 ip_xhci_cap;
124 __le32 reserved1[2];
125 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
126 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
127 __le32 reserved2;
128 __le32 u2_phy_pll;
129 __le32 reserved3[33]; /* 0x80 ~ 0xff */
130 };
131
132 struct xhci_hcd_mtk {
133 struct device *dev;
134 struct usb_hcd *hcd;
135 struct mu3h_sch_bw_info *sch_array;
136 struct list_head bw_ep_chk_list;
137 struct mu3c_ippc_regs __iomem *ippc_regs;
138 bool has_ippc;
139 int num_u2_ports;
140 int num_u3_ports;
141 int u3p_dis_msk;
142 struct regulator *vusb33;
143 struct regulator *vbus;
144 struct clk *sys_clk; /* sys and mac clock */
145 struct clk *xhci_clk;
146 struct clk *ref_clk;
147 struct clk *mcu_clk;
148 struct clk *dma_clk;
149 struct regmap *pericfg;
150 struct phy **phys;
151 int num_phys;
152 bool lpm_support;
153 bool u2_lpm_disable;
154 /* usb remote wakeup */
155 bool uwk_en;
156 struct regmap *uwk;
157 u32 uwk_reg_base;
158 u32 uwk_vers;
159 };
160
hcd_to_mtk(struct usb_hcd * hcd)161 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
162 {
163 return dev_get_drvdata(hcd->self.controller);
164 }
165
166 #if IS_ENABLED(CONFIG_USB_XHCI_MTK)
167 int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
168 void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
169 int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
170 struct usb_host_endpoint *ep);
171 void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
172 struct usb_host_endpoint *ep);
173 int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
174 void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
175
176 #else
xhci_mtk_add_ep_quirk(struct usb_hcd * hcd,struct usb_device * udev,struct usb_host_endpoint * ep)177 static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
178 struct usb_device *udev, struct usb_host_endpoint *ep)
179 {
180 return 0;
181 }
182
xhci_mtk_drop_ep_quirk(struct usb_hcd * hcd,struct usb_device * udev,struct usb_host_endpoint * ep)183 static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
184 struct usb_device *udev, struct usb_host_endpoint *ep)
185 {
186 }
187
xhci_mtk_check_bandwidth(struct usb_hcd * hcd,struct usb_device * udev)188 static inline int xhci_mtk_check_bandwidth(struct usb_hcd *hcd,
189 struct usb_device *udev)
190 {
191 return 0;
192 }
193
xhci_mtk_reset_bandwidth(struct usb_hcd * hcd,struct usb_device * udev)194 static inline void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd,
195 struct usb_device *udev)
196 {
197 }
198 #endif
199
200 #endif /* _XHCI_MTK_H_ */
201