1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2018 NXP
3
4 #include <linux/clk.h>
5 #include <linux/device.h>
6 #include <linux/interrupt.h>
7 #include <linux/kobject.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/of_platform.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/sysfs.h>
17 #include <linux/types.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
22 #include <sound/core.h>
23
24 #include "fsl_micfil.h"
25 #include "imx-pcm.h"
26
27 #define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
28 #define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
29
30 struct fsl_micfil {
31 struct platform_device *pdev;
32 struct regmap *regmap;
33 const struct fsl_micfil_soc_data *soc;
34 struct clk *mclk;
35 struct snd_dmaengine_dai_dma_data dma_params_rx;
36 unsigned int dataline;
37 char name[32];
38 int irq[MICFIL_IRQ_LINES];
39 unsigned int mclk_streams;
40 int quality; /*QUALITY 2-0 bits */
41 bool slave_mode;
42 int channel_gain[8];
43 };
44
45 struct fsl_micfil_soc_data {
46 unsigned int fifos;
47 unsigned int fifo_depth;
48 unsigned int dataline;
49 bool imx;
50 };
51
52 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
53 .imx = true,
54 .fifos = 8,
55 .fifo_depth = 8,
56 .dataline = 0xf,
57 };
58
59 static const struct of_device_id fsl_micfil_dt_ids[] = {
60 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
61 {}
62 };
63 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
64
65 /* Table 5. Quality Modes
66 * Medium 0 0 0
67 * High 0 0 1
68 * Very Low 2 1 0 0
69 * Very Low 1 1 0 1
70 * Very Low 0 1 1 0
71 * Low 1 1 1
72 */
73 static const char * const micfil_quality_select_texts[] = {
74 "Medium", "High",
75 "N/A", "N/A",
76 "VLow2", "VLow1",
77 "VLow0", "Low",
78 };
79
80 static const struct soc_enum fsl_micfil_quality_enum =
81 SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
82 MICFIL_CTRL2_QSEL_SHIFT,
83 ARRAY_SIZE(micfil_quality_select_texts),
84 micfil_quality_select_texts);
85
86 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
87
88 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
89 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
90 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
91 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
92 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv),
93 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
94 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv),
95 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
96 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv),
97 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
98 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv),
99 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
100 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv),
101 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
102 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv),
103 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
104 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
105 SOC_ENUM_EXT("MICFIL Quality Select",
106 fsl_micfil_quality_enum,
107 snd_soc_get_enum_double, snd_soc_put_enum_double),
108 };
109
get_pdm_clk(struct fsl_micfil * micfil,unsigned int rate)110 static inline int get_pdm_clk(struct fsl_micfil *micfil,
111 unsigned int rate)
112 {
113 u32 ctrl2_reg;
114 int qsel, osr;
115 int bclk;
116
117 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
118 osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
119 >> MICFIL_CTRL2_CICOSR_SHIFT);
120
121 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
122 qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
123
124 switch (qsel) {
125 case MICFIL_HIGH_QUALITY:
126 bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
127 break;
128 case MICFIL_MEDIUM_QUALITY:
129 case MICFIL_VLOW0_QUALITY:
130 bclk = rate * 4 * osr * 1; /* kfactor = 1 */
131 break;
132 case MICFIL_LOW_QUALITY:
133 case MICFIL_VLOW1_QUALITY:
134 bclk = rate * 2 * osr * 2; /* kfactor = 2 */
135 break;
136 case MICFIL_VLOW2_QUALITY:
137 bclk = rate * osr * 4; /* kfactor = 4 */
138 break;
139 default:
140 dev_err(&micfil->pdev->dev,
141 "Please make sure you select a valid quality.\n");
142 bclk = -1;
143 break;
144 }
145
146 return bclk;
147 }
148
get_clk_div(struct fsl_micfil * micfil,unsigned int rate)149 static inline int get_clk_div(struct fsl_micfil *micfil,
150 unsigned int rate)
151 {
152 u32 ctrl2_reg;
153 long mclk_rate;
154 int clk_div;
155
156 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
157
158 mclk_rate = clk_get_rate(micfil->mclk);
159
160 clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
161
162 return clk_div;
163 }
164
165 /* The SRES is a self-negated bit which provides the CPU with the
166 * capability to initialize the PDM Interface module through the
167 * slave-bus interface. This bit always reads as zero, and this
168 * bit is only effective when MDIS is cleared
169 */
fsl_micfil_reset(struct device * dev)170 static int fsl_micfil_reset(struct device *dev)
171 {
172 struct fsl_micfil *micfil = dev_get_drvdata(dev);
173 int ret;
174
175 ret = regmap_update_bits(micfil->regmap,
176 REG_MICFIL_CTRL1,
177 MICFIL_CTRL1_MDIS_MASK,
178 0);
179 if (ret) {
180 dev_err(dev, "failed to clear MDIS bit %d\n", ret);
181 return ret;
182 }
183
184 ret = regmap_update_bits(micfil->regmap,
185 REG_MICFIL_CTRL1,
186 MICFIL_CTRL1_SRES_MASK,
187 MICFIL_CTRL1_SRES);
188 if (ret) {
189 dev_err(dev, "failed to reset MICFIL: %d\n", ret);
190 return ret;
191 }
192
193 /*
194 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
195 * as non-volatile register, so SRES still remain in regmap
196 * cache after set, that every update of REG_MICFIL_CTRL1,
197 * software reset happens. so clear it explicitly.
198 */
199 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
200 MICFIL_CTRL1_SRES);
201 if (ret)
202 return ret;
203
204 /*
205 * Set SRES should clear CHnF flags, But even add delay here
206 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
207 */
208 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
209 if (ret)
210 return ret;
211
212 return 0;
213 }
214
fsl_micfil_set_mclk_rate(struct fsl_micfil * micfil,unsigned int freq)215 static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
216 unsigned int freq)
217 {
218 struct device *dev = &micfil->pdev->dev;
219 int ret;
220
221 clk_disable_unprepare(micfil->mclk);
222
223 ret = clk_set_rate(micfil->mclk, freq * 1024);
224 if (ret)
225 dev_warn(dev, "failed to set rate (%u): %d\n",
226 freq * 1024, ret);
227
228 clk_prepare_enable(micfil->mclk);
229
230 return ret;
231 }
232
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)233 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
234 struct snd_soc_dai *dai)
235 {
236 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
237
238 if (!micfil) {
239 dev_err(dai->dev, "micfil dai priv_data not set\n");
240 return -EINVAL;
241 }
242
243 return 0;
244 }
245
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)246 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
247 struct snd_soc_dai *dai)
248 {
249 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
250 struct device *dev = &micfil->pdev->dev;
251 int ret;
252
253 switch (cmd) {
254 case SNDRV_PCM_TRIGGER_START:
255 case SNDRV_PCM_TRIGGER_RESUME:
256 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
257 ret = fsl_micfil_reset(dev);
258 if (ret) {
259 dev_err(dev, "failed to soft reset\n");
260 return ret;
261 }
262
263 /* DMA Interrupt Selection - DISEL bits
264 * 00 - DMA and IRQ disabled
265 * 01 - DMA req enabled
266 * 10 - IRQ enabled
267 * 11 - reserved
268 */
269 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
270 MICFIL_CTRL1_DISEL_MASK,
271 (1 << MICFIL_CTRL1_DISEL_SHIFT));
272 if (ret) {
273 dev_err(dev, "failed to update DISEL bits\n");
274 return ret;
275 }
276
277 /* Enable the module */
278 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
279 MICFIL_CTRL1_PDMIEN_MASK,
280 MICFIL_CTRL1_PDMIEN);
281 if (ret) {
282 dev_err(dev, "failed to enable the module\n");
283 return ret;
284 }
285
286 break;
287 case SNDRV_PCM_TRIGGER_STOP:
288 case SNDRV_PCM_TRIGGER_SUSPEND:
289 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
290 /* Disable the module */
291 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
292 MICFIL_CTRL1_PDMIEN_MASK,
293 0);
294 if (ret) {
295 dev_err(dev, "failed to enable the module\n");
296 return ret;
297 }
298
299 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
300 MICFIL_CTRL1_DISEL_MASK,
301 (0 << MICFIL_CTRL1_DISEL_SHIFT));
302 if (ret) {
303 dev_err(dev, "failed to update DISEL bits\n");
304 return ret;
305 }
306 break;
307 default:
308 return -EINVAL;
309 }
310 return 0;
311 }
312
fsl_set_clock_params(struct device * dev,unsigned int rate)313 static int fsl_set_clock_params(struct device *dev, unsigned int rate)
314 {
315 struct fsl_micfil *micfil = dev_get_drvdata(dev);
316 int clk_div;
317 int ret;
318
319 ret = fsl_micfil_set_mclk_rate(micfil, rate);
320 if (ret < 0)
321 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
322 clk_get_rate(micfil->mclk), rate);
323
324 /* set CICOSR */
325 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
326 MICFIL_CTRL2_CICOSR_MASK,
327 MICFIL_CTRL2_OSR_DEFAULT);
328 if (ret)
329 dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
330 REG_MICFIL_CTRL2);
331
332 /* set CLK_DIV */
333 clk_div = get_clk_div(micfil, rate);
334 if (clk_div < 0)
335 ret = -EINVAL;
336
337 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
338 MICFIL_CTRL2_CLKDIV_MASK, clk_div);
339 if (ret)
340 dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
341 REG_MICFIL_CTRL2);
342
343 return ret;
344 }
345
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)346 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
347 struct snd_pcm_hw_params *params,
348 struct snd_soc_dai *dai)
349 {
350 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
351 unsigned int channels = params_channels(params);
352 unsigned int rate = params_rate(params);
353 struct device *dev = &micfil->pdev->dev;
354 int ret;
355
356 /* 1. Disable the module */
357 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
358 MICFIL_CTRL1_PDMIEN_MASK, 0);
359 if (ret) {
360 dev_err(dev, "failed to disable the module\n");
361 return ret;
362 }
363
364 /* enable channels */
365 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
366 0xFF, ((1 << channels) - 1));
367 if (ret) {
368 dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
369 REG_MICFIL_CTRL1);
370 return ret;
371 }
372
373 ret = fsl_set_clock_params(dev, rate);
374 if (ret < 0) {
375 dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
376 return ret;
377 }
378
379 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
380
381 return 0;
382 }
383
fsl_micfil_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)384 static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
385 unsigned int freq, int dir)
386 {
387 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
388 struct device *dev = &micfil->pdev->dev;
389
390 int ret;
391
392 if (!freq)
393 return 0;
394
395 ret = fsl_micfil_set_mclk_rate(micfil, freq);
396 if (ret < 0)
397 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
398 clk_get_rate(micfil->mclk), freq);
399
400 return ret;
401 }
402
403 static struct snd_soc_dai_ops fsl_micfil_dai_ops = {
404 .startup = fsl_micfil_startup,
405 .trigger = fsl_micfil_trigger,
406 .hw_params = fsl_micfil_hw_params,
407 .set_sysclk = fsl_micfil_set_dai_sysclk,
408 };
409
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)410 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
411 {
412 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
413 struct device *dev = cpu_dai->dev;
414 unsigned int val;
415 int ret;
416 int i;
417
418 /* set qsel to medium */
419 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
420 MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
421 if (ret) {
422 dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
423 REG_MICFIL_CTRL2);
424 return ret;
425 }
426
427 /* set default gain to max_gain */
428 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
429 for (i = 0; i < 8; i++)
430 micfil->channel_gain[i] = 0xF;
431
432 snd_soc_dai_init_dma_data(cpu_dai, NULL,
433 &micfil->dma_params_rx);
434
435 /* FIFO Watermark Control - FIFOWMK*/
436 val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
437 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
438 MICFIL_FIFO_CTRL_FIFOWMK_MASK,
439 val);
440 if (ret) {
441 dev_err(dev, "failed to set FIFOWMK\n");
442 return ret;
443 }
444
445 snd_soc_dai_set_drvdata(cpu_dai, micfil);
446
447 return 0;
448 }
449
450 static struct snd_soc_dai_driver fsl_micfil_dai = {
451 .probe = fsl_micfil_dai_probe,
452 .capture = {
453 .stream_name = "CPU-Capture",
454 .channels_min = 1,
455 .channels_max = 8,
456 .rates = FSL_MICFIL_RATES,
457 .formats = FSL_MICFIL_FORMATS,
458 },
459 .ops = &fsl_micfil_dai_ops,
460 };
461
462 static const struct snd_soc_component_driver fsl_micfil_component = {
463 .name = "fsl-micfil-dai",
464 .controls = fsl_micfil_snd_controls,
465 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
466
467 };
468
469 /* REGMAP */
470 static const struct reg_default fsl_micfil_reg_defaults[] = {
471 {REG_MICFIL_CTRL1, 0x00000000},
472 {REG_MICFIL_CTRL2, 0x00000000},
473 {REG_MICFIL_STAT, 0x00000000},
474 {REG_MICFIL_FIFO_CTRL, 0x00000007},
475 {REG_MICFIL_FIFO_STAT, 0x00000000},
476 {REG_MICFIL_DATACH0, 0x00000000},
477 {REG_MICFIL_DATACH1, 0x00000000},
478 {REG_MICFIL_DATACH2, 0x00000000},
479 {REG_MICFIL_DATACH3, 0x00000000},
480 {REG_MICFIL_DATACH4, 0x00000000},
481 {REG_MICFIL_DATACH5, 0x00000000},
482 {REG_MICFIL_DATACH6, 0x00000000},
483 {REG_MICFIL_DATACH7, 0x00000000},
484 {REG_MICFIL_DC_CTRL, 0x00000000},
485 {REG_MICFIL_OUT_CTRL, 0x00000000},
486 {REG_MICFIL_OUT_STAT, 0x00000000},
487 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
488 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
489 {REG_MICFIL_VAD0_STAT, 0x00000000},
490 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
491 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
492 {REG_MICFIL_VAD0_NDATA, 0x00000000},
493 {REG_MICFIL_VAD0_ZCD, 0x00000004},
494 };
495
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)496 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
497 {
498 switch (reg) {
499 case REG_MICFIL_CTRL1:
500 case REG_MICFIL_CTRL2:
501 case REG_MICFIL_STAT:
502 case REG_MICFIL_FIFO_CTRL:
503 case REG_MICFIL_FIFO_STAT:
504 case REG_MICFIL_DATACH0:
505 case REG_MICFIL_DATACH1:
506 case REG_MICFIL_DATACH2:
507 case REG_MICFIL_DATACH3:
508 case REG_MICFIL_DATACH4:
509 case REG_MICFIL_DATACH5:
510 case REG_MICFIL_DATACH6:
511 case REG_MICFIL_DATACH7:
512 case REG_MICFIL_DC_CTRL:
513 case REG_MICFIL_OUT_CTRL:
514 case REG_MICFIL_OUT_STAT:
515 case REG_MICFIL_VAD0_CTRL1:
516 case REG_MICFIL_VAD0_CTRL2:
517 case REG_MICFIL_VAD0_STAT:
518 case REG_MICFIL_VAD0_SCONFIG:
519 case REG_MICFIL_VAD0_NCONFIG:
520 case REG_MICFIL_VAD0_NDATA:
521 case REG_MICFIL_VAD0_ZCD:
522 return true;
523 default:
524 return false;
525 }
526 }
527
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)528 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
529 {
530 switch (reg) {
531 case REG_MICFIL_CTRL1:
532 case REG_MICFIL_CTRL2:
533 case REG_MICFIL_STAT: /* Write 1 to Clear */
534 case REG_MICFIL_FIFO_CTRL:
535 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
536 case REG_MICFIL_DC_CTRL:
537 case REG_MICFIL_OUT_CTRL:
538 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
539 case REG_MICFIL_VAD0_CTRL1:
540 case REG_MICFIL_VAD0_CTRL2:
541 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
542 case REG_MICFIL_VAD0_SCONFIG:
543 case REG_MICFIL_VAD0_NCONFIG:
544 case REG_MICFIL_VAD0_ZCD:
545 return true;
546 default:
547 return false;
548 }
549 }
550
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)551 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
552 {
553 switch (reg) {
554 case REG_MICFIL_STAT:
555 case REG_MICFIL_DATACH0:
556 case REG_MICFIL_DATACH1:
557 case REG_MICFIL_DATACH2:
558 case REG_MICFIL_DATACH3:
559 case REG_MICFIL_DATACH4:
560 case REG_MICFIL_DATACH5:
561 case REG_MICFIL_DATACH6:
562 case REG_MICFIL_DATACH7:
563 case REG_MICFIL_VAD0_STAT:
564 case REG_MICFIL_VAD0_NDATA:
565 return true;
566 default:
567 return false;
568 }
569 }
570
571 static const struct regmap_config fsl_micfil_regmap_config = {
572 .reg_bits = 32,
573 .reg_stride = 4,
574 .val_bits = 32,
575
576 .max_register = REG_MICFIL_VAD0_ZCD,
577 .reg_defaults = fsl_micfil_reg_defaults,
578 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
579 .readable_reg = fsl_micfil_readable_reg,
580 .volatile_reg = fsl_micfil_volatile_reg,
581 .writeable_reg = fsl_micfil_writeable_reg,
582 .cache_type = REGCACHE_RBTREE,
583 };
584
585 /* END OF REGMAP */
586
micfil_isr(int irq,void * devid)587 static irqreturn_t micfil_isr(int irq, void *devid)
588 {
589 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
590 struct platform_device *pdev = micfil->pdev;
591 u32 stat_reg;
592 u32 fifo_stat_reg;
593 u32 ctrl1_reg;
594 bool dma_enabled;
595 int i;
596
597 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
598 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
599 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
600
601 dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
602
603 /* Channel 0-7 Output Data Flags */
604 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
605 if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
606 dev_dbg(&pdev->dev,
607 "Data available in Data Channel %d\n", i);
608 /* if DMA is not enabled, field must be written with 1
609 * to clear
610 */
611 if (!dma_enabled)
612 regmap_write_bits(micfil->regmap,
613 REG_MICFIL_STAT,
614 MICFIL_STAT_CHXF_MASK(i),
615 1);
616 }
617
618 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
619 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
620 dev_dbg(&pdev->dev,
621 "FIFO Overflow Exception flag for channel %d\n",
622 i);
623
624 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
625 dev_dbg(&pdev->dev,
626 "FIFO Underflow Exception flag for channel %d\n",
627 i);
628 }
629
630 return IRQ_HANDLED;
631 }
632
micfil_err_isr(int irq,void * devid)633 static irqreturn_t micfil_err_isr(int irq, void *devid)
634 {
635 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
636 struct platform_device *pdev = micfil->pdev;
637 u32 stat_reg;
638
639 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
640
641 if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
642 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
643
644 if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
645 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
646
647 if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
648 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
649 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
650 MICFIL_STAT_LOWFREQF_MASK, 1);
651 }
652
653 return IRQ_HANDLED;
654 }
655
fsl_micfil_probe(struct platform_device * pdev)656 static int fsl_micfil_probe(struct platform_device *pdev)
657 {
658 struct device_node *np = pdev->dev.of_node;
659 const struct of_device_id *of_id;
660 struct fsl_micfil *micfil;
661 struct resource *res;
662 void __iomem *regs;
663 int ret, i;
664 unsigned long irqflag = 0;
665
666 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
667 if (!micfil)
668 return -ENOMEM;
669
670 micfil->pdev = pdev;
671 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
672
673 of_id = of_match_device(fsl_micfil_dt_ids, &pdev->dev);
674 if (!of_id || !of_id->data)
675 return -EINVAL;
676
677 micfil->soc = of_id->data;
678
679 /* ipg_clk is used to control the registers
680 * ipg_clk_app is used to operate the filter
681 */
682 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
683 if (IS_ERR(micfil->mclk)) {
684 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
685 PTR_ERR(micfil->mclk));
686 return PTR_ERR(micfil->mclk);
687 }
688
689 /* init regmap */
690 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
691 regs = devm_ioremap_resource(&pdev->dev, res);
692 if (IS_ERR(regs))
693 return PTR_ERR(regs);
694
695 micfil->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
696 "ipg_clk",
697 regs,
698 &fsl_micfil_regmap_config);
699 if (IS_ERR(micfil->regmap)) {
700 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
701 PTR_ERR(micfil->regmap));
702 return PTR_ERR(micfil->regmap);
703 }
704
705 /* dataline mask for RX */
706 ret = of_property_read_u32_index(np,
707 "fsl,dataline",
708 0,
709 &micfil->dataline);
710 if (ret)
711 micfil->dataline = 1;
712
713 if (micfil->dataline & ~micfil->soc->dataline) {
714 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
715 micfil->soc->dataline);
716 return -EINVAL;
717 }
718
719 /* get IRQs */
720 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
721 micfil->irq[i] = platform_get_irq(pdev, i);
722 dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
723 if (micfil->irq[i] < 0)
724 return micfil->irq[i];
725 }
726
727 if (of_property_read_bool(np, "fsl,shared-interrupt"))
728 irqflag = IRQF_SHARED;
729
730 /* Digital Microphone interface interrupt */
731 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
732 micfil_isr, irqflag,
733 micfil->name, micfil);
734 if (ret) {
735 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
736 micfil->irq[0]);
737 return ret;
738 }
739
740 /* Digital Microphone interface error interrupt */
741 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
742 micfil_err_isr, irqflag,
743 micfil->name, micfil);
744 if (ret) {
745 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
746 micfil->irq[1]);
747 return ret;
748 }
749
750 micfil->dma_params_rx.chan_name = "rx";
751 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
752 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
753
754
755 platform_set_drvdata(pdev, micfil);
756
757 pm_runtime_enable(&pdev->dev);
758
759 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
760 &fsl_micfil_dai, 1);
761 if (ret) {
762 dev_err(&pdev->dev, "failed to register component %s\n",
763 fsl_micfil_component.name);
764 return ret;
765 }
766
767 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
768 if (ret)
769 dev_err(&pdev->dev, "failed to pcm register\n");
770
771 return ret;
772 }
773
fsl_micfil_runtime_suspend(struct device * dev)774 static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
775 {
776 struct fsl_micfil *micfil = dev_get_drvdata(dev);
777
778 regcache_cache_only(micfil->regmap, true);
779
780 clk_disable_unprepare(micfil->mclk);
781
782 return 0;
783 }
784
fsl_micfil_runtime_resume(struct device * dev)785 static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
786 {
787 struct fsl_micfil *micfil = dev_get_drvdata(dev);
788 int ret;
789
790 ret = clk_prepare_enable(micfil->mclk);
791 if (ret < 0)
792 return ret;
793
794 regcache_cache_only(micfil->regmap, false);
795 regcache_mark_dirty(micfil->regmap);
796 regcache_sync(micfil->regmap);
797
798 return 0;
799 }
800
fsl_micfil_suspend(struct device * dev)801 static int __maybe_unused fsl_micfil_suspend(struct device *dev)
802 {
803 pm_runtime_force_suspend(dev);
804
805 return 0;
806 }
807
fsl_micfil_resume(struct device * dev)808 static int __maybe_unused fsl_micfil_resume(struct device *dev)
809 {
810 pm_runtime_force_resume(dev);
811
812 return 0;
813 }
814
815 static const struct dev_pm_ops fsl_micfil_pm_ops = {
816 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
817 fsl_micfil_runtime_resume,
818 NULL)
819 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
820 fsl_micfil_resume)
821 };
822
823 static struct platform_driver fsl_micfil_driver = {
824 .probe = fsl_micfil_probe,
825 .driver = {
826 .name = "fsl-micfil-dai",
827 .pm = &fsl_micfil_pm_ops,
828 .of_match_table = fsl_micfil_dt_ids,
829 },
830 };
831 module_platform_driver(fsl_micfil_driver);
832
833 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
834 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
835 MODULE_LICENSE("GPL v2");
836