1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef __AMDGPU_DRM_H__ 7 #define __AMDGPU_DRM_H__ 8 #include "drm.h" 9 #if defined(__cplusplus) 10 extern "C" { 11 #endif 12 #define DRM_AMDGPU_GEM_CREATE 0x00 13 #define DRM_AMDGPU_GEM_MMAP 0x01 14 #define DRM_AMDGPU_CTX 0x02 15 #define DRM_AMDGPU_BO_LIST 0x03 16 #define DRM_AMDGPU_CS 0x04 17 #define DRM_AMDGPU_INFO 0x05 18 #define DRM_AMDGPU_GEM_METADATA 0x06 19 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 20 #define DRM_AMDGPU_GEM_VA 0x08 21 #define DRM_AMDGPU_WAIT_CS 0x09 22 #define DRM_AMDGPU_GEM_OP 0x10 23 #define DRM_AMDGPU_GEM_USERPTR 0x11 24 #define DRM_AMDGPU_WAIT_FENCES 0x12 25 #define DRM_AMDGPU_VM 0x13 26 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 27 #define DRM_AMDGPU_SCHED 0x15 28 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 29 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 30 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 31 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 32 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 33 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 34 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 35 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 36 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 37 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 38 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 39 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 40 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 41 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 42 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 43 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 44 #define AMDGPU_GEM_DOMAIN_CPU 0x1 45 #define AMDGPU_GEM_DOMAIN_GTT 0x2 46 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 47 #define AMDGPU_GEM_DOMAIN_GDS 0x8 48 #define AMDGPU_GEM_DOMAIN_GWS 0x10 49 #define AMDGPU_GEM_DOMAIN_OA 0x20 50 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 51 AMDGPU_GEM_DOMAIN_GTT | \ 52 AMDGPU_GEM_DOMAIN_VRAM | \ 53 AMDGPU_GEM_DOMAIN_GDS | \ 54 AMDGPU_GEM_DOMAIN_GWS | \ 55 AMDGPU_GEM_DOMAIN_OA) 56 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 57 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 58 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 59 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 60 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 61 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 62 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 63 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 64 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) 65 struct drm_amdgpu_gem_create_in { 66 67 __u64 bo_size; 68 69 __u64 alignment; 70 71 __u64 domains; 72 73 __u64 domain_flags; 74 }; 75 struct drm_amdgpu_gem_create_out { 76 77 __u32 handle; 78 __u32 _pad; 79 }; 80 union drm_amdgpu_gem_create { 81 struct drm_amdgpu_gem_create_in in; 82 struct drm_amdgpu_gem_create_out out; 83 }; 84 #define AMDGPU_BO_LIST_OP_CREATE 0 85 #define AMDGPU_BO_LIST_OP_DESTROY 1 86 #define AMDGPU_BO_LIST_OP_UPDATE 2 87 struct drm_amdgpu_bo_list_in { 88 89 __u32 operation; 90 91 __u32 list_handle; 92 93 __u32 bo_number; 94 95 __u32 bo_info_size; 96 97 __u64 bo_info_ptr; 98 }; 99 struct drm_amdgpu_bo_list_entry { 100 101 __u32 bo_handle; 102 103 __u32 bo_priority; 104 }; 105 struct drm_amdgpu_bo_list_out { 106 107 __u32 list_handle; 108 __u32 _pad; 109 }; 110 union drm_amdgpu_bo_list { 111 struct drm_amdgpu_bo_list_in in; 112 struct drm_amdgpu_bo_list_out out; 113 }; 114 #define AMDGPU_CTX_OP_ALLOC_CTX 1 115 #define AMDGPU_CTX_OP_FREE_CTX 2 116 #define AMDGPU_CTX_OP_QUERY_STATE 3 117 #define AMDGPU_CTX_OP_QUERY_STATE2 4 118 #define AMDGPU_CTX_NO_RESET 0 119 #define AMDGPU_CTX_GUILTY_RESET 1 120 #define AMDGPU_CTX_INNOCENT_RESET 2 121 #define AMDGPU_CTX_UNKNOWN_RESET 3 122 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 123 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 124 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 125 #define AMDGPU_CTX_PRIORITY_UNSET -2048 126 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 127 #define AMDGPU_CTX_PRIORITY_LOW -512 128 #define AMDGPU_CTX_PRIORITY_NORMAL 0 129 #define AMDGPU_CTX_PRIORITY_HIGH 512 130 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 131 struct drm_amdgpu_ctx_in { 132 133 __u32 op; 134 135 __u32 flags; 136 __u32 ctx_id; 137 __s32 priority; 138 }; 139 union drm_amdgpu_ctx_out { 140 struct { 141 __u32 ctx_id; 142 __u32 _pad; 143 } alloc; 144 struct { 145 146 __u64 flags; 147 148 __u32 hangs; 149 150 __u32 reset_status; 151 } state; 152 }; 153 union drm_amdgpu_ctx { 154 struct drm_amdgpu_ctx_in in; 155 union drm_amdgpu_ctx_out out; 156 }; 157 #define AMDGPU_VM_OP_RESERVE_VMID 1 158 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 159 struct drm_amdgpu_vm_in { 160 161 __u32 op; 162 __u32 flags; 163 }; 164 struct drm_amdgpu_vm_out { 165 166 __u64 flags; 167 }; 168 union drm_amdgpu_vm { 169 struct drm_amdgpu_vm_in in; 170 struct drm_amdgpu_vm_out out; 171 }; 172 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 173 struct drm_amdgpu_sched_in { 174 175 __u32 op; 176 __u32 fd; 177 __s32 priority; 178 __u32 flags; 179 }; 180 union drm_amdgpu_sched { 181 struct drm_amdgpu_sched_in in; 182 }; 183 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 184 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 185 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 186 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 187 struct drm_amdgpu_gem_userptr { 188 __u64 addr; 189 __u64 size; 190 191 __u32 flags; 192 193 __u32 handle; 194 }; 195 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 196 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 197 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 198 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 199 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 200 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 201 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 202 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 203 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 204 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 205 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 206 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 207 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 208 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 209 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 210 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 211 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 212 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 213 #define AMDGPU_TILING_SET(field, value) \ 214 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 215 #define AMDGPU_TILING_GET(value, field) \ 216 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 217 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 218 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 219 struct drm_amdgpu_gem_metadata { 220 221 __u32 handle; 222 223 __u32 op; 224 struct { 225 226 __u64 flags; 227 228 __u64 tiling_info; 229 __u32 data_size_bytes; 230 __u32 data[64]; 231 } data; 232 }; 233 struct drm_amdgpu_gem_mmap_in { 234 235 __u32 handle; 236 __u32 _pad; 237 }; 238 struct drm_amdgpu_gem_mmap_out { 239 240 __u64 addr_ptr; 241 }; 242 union drm_amdgpu_gem_mmap { 243 struct drm_amdgpu_gem_mmap_in in; 244 struct drm_amdgpu_gem_mmap_out out; 245 }; 246 struct drm_amdgpu_gem_wait_idle_in { 247 248 __u32 handle; 249 250 __u32 flags; 251 252 __u64 timeout; 253 }; 254 struct drm_amdgpu_gem_wait_idle_out { 255 256 __u32 status; 257 258 __u32 domain; 259 }; 260 union drm_amdgpu_gem_wait_idle { 261 struct drm_amdgpu_gem_wait_idle_in in; 262 struct drm_amdgpu_gem_wait_idle_out out; 263 }; 264 struct drm_amdgpu_wait_cs_in { 265 266 __u64 handle; 267 268 __u64 timeout; 269 __u32 ip_type; 270 __u32 ip_instance; 271 __u32 ring; 272 __u32 ctx_id; 273 }; 274 struct drm_amdgpu_wait_cs_out { 275 276 __u64 status; 277 }; 278 union drm_amdgpu_wait_cs { 279 struct drm_amdgpu_wait_cs_in in; 280 struct drm_amdgpu_wait_cs_out out; 281 }; 282 struct drm_amdgpu_fence { 283 __u32 ctx_id; 284 __u32 ip_type; 285 __u32 ip_instance; 286 __u32 ring; 287 __u64 seq_no; 288 }; 289 struct drm_amdgpu_wait_fences_in { 290 291 __u64 fences; 292 __u32 fence_count; 293 __u32 wait_all; 294 __u64 timeout_ns; 295 }; 296 struct drm_amdgpu_wait_fences_out { 297 __u32 status; 298 __u32 first_signaled; 299 }; 300 union drm_amdgpu_wait_fences { 301 struct drm_amdgpu_wait_fences_in in; 302 struct drm_amdgpu_wait_fences_out out; 303 }; 304 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 305 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 306 struct drm_amdgpu_gem_op { 307 308 __u32 handle; 309 310 __u32 op; 311 312 __u64 value; 313 }; 314 #define AMDGPU_VA_OP_MAP 1 315 #define AMDGPU_VA_OP_UNMAP 2 316 #define AMDGPU_VA_OP_CLEAR 3 317 #define AMDGPU_VA_OP_REPLACE 4 318 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 319 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 320 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 321 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 322 #define AMDGPU_VM_PAGE_PRT (1 << 4) 323 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 324 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 325 #define AMDGPU_VM_MTYPE_NC (1 << 5) 326 #define AMDGPU_VM_MTYPE_WC (2 << 5) 327 #define AMDGPU_VM_MTYPE_CC (3 << 5) 328 #define AMDGPU_VM_MTYPE_UC (4 << 5) 329 struct drm_amdgpu_gem_va { 330 331 __u32 handle; 332 __u32 _pad; 333 334 __u32 operation; 335 336 __u32 flags; 337 338 __u64 va_address; 339 340 __u64 offset_in_bo; 341 342 __u64 map_size; 343 }; 344 #define AMDGPU_HW_IP_GFX 0 345 #define AMDGPU_HW_IP_COMPUTE 1 346 #define AMDGPU_HW_IP_DMA 2 347 #define AMDGPU_HW_IP_UVD 3 348 #define AMDGPU_HW_IP_VCE 4 349 #define AMDGPU_HW_IP_UVD_ENC 5 350 #define AMDGPU_HW_IP_VCN_DEC 6 351 #define AMDGPU_HW_IP_VCN_ENC 7 352 #define AMDGPU_HW_IP_VCN_JPEG 8 353 #define AMDGPU_HW_IP_NUM 9 354 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 355 #define AMDGPU_CHUNK_ID_IB 0x01 356 #define AMDGPU_CHUNK_ID_FENCE 0x02 357 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 358 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 359 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 360 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 361 struct drm_amdgpu_cs_chunk { 362 __u32 chunk_id; 363 __u32 length_dw; 364 __u64 chunk_data; 365 }; 366 struct drm_amdgpu_cs_in { 367 368 __u32 ctx_id; 369 370 __u32 bo_list_handle; 371 __u32 num_chunks; 372 __u32 _pad; 373 374 __u64 chunks; 375 }; 376 struct drm_amdgpu_cs_out { 377 __u64 handle; 378 }; 379 union drm_amdgpu_cs { 380 struct drm_amdgpu_cs_in in; 381 struct drm_amdgpu_cs_out out; 382 }; 383 #define AMDGPU_IB_FLAG_CE (1<<0) 384 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 385 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 386 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 387 struct drm_amdgpu_cs_chunk_ib { 388 __u32 _pad; 389 390 __u32 flags; 391 392 __u64 va_start; 393 394 __u32 ib_bytes; 395 396 __u32 ip_type; 397 398 __u32 ip_instance; 399 400 __u32 ring; 401 }; 402 struct drm_amdgpu_cs_chunk_dep { 403 __u32 ip_type; 404 __u32 ip_instance; 405 __u32 ring; 406 __u32 ctx_id; 407 __u64 handle; 408 }; 409 struct drm_amdgpu_cs_chunk_fence { 410 __u32 handle; 411 __u32 offset; 412 }; 413 struct drm_amdgpu_cs_chunk_sem { 414 __u32 handle; 415 }; 416 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 417 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 418 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 419 union drm_amdgpu_fence_to_handle { 420 struct { 421 struct drm_amdgpu_fence fence; 422 __u32 what; 423 __u32 pad; 424 } in; 425 struct { 426 __u32 handle; 427 } out; 428 }; 429 struct drm_amdgpu_cs_chunk_data { 430 union { 431 struct drm_amdgpu_cs_chunk_ib ib_data; 432 struct drm_amdgpu_cs_chunk_fence fence_data; 433 }; 434 }; 435 #define AMDGPU_IDS_FLAGS_FUSION 0x1 436 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 437 #define AMDGPU_INFO_ACCEL_WORKING 0x00 438 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 439 #define AMDGPU_INFO_HW_IP_INFO 0x02 440 #define AMDGPU_INFO_HW_IP_COUNT 0x03 441 #define AMDGPU_INFO_TIMESTAMP 0x05 442 #define AMDGPU_INFO_FW_VERSION 0x0e 443 444 #define AMDGPU_INFO_FW_VCE 0x1 445 446 #define AMDGPU_INFO_FW_UVD 0x2 447 448 #define AMDGPU_INFO_FW_GMC 0x03 449 450 #define AMDGPU_INFO_FW_GFX_ME 0x04 451 452 #define AMDGPU_INFO_FW_GFX_PFP 0x05 453 454 #define AMDGPU_INFO_FW_GFX_CE 0x06 455 456 #define AMDGPU_INFO_FW_GFX_RLC 0x07 457 458 #define AMDGPU_INFO_FW_GFX_MEC 0x08 459 460 #define AMDGPU_INFO_FW_SMC 0x0a 461 462 #define AMDGPU_INFO_FW_SDMA 0x0b 463 464 #define AMDGPU_INFO_FW_SOS 0x0c 465 466 #define AMDGPU_INFO_FW_ASD 0x0d 467 468 #define AMDGPU_INFO_FW_VCN 0x0e 469 470 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 471 472 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 473 474 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 475 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 476 #define AMDGPU_INFO_VRAM_USAGE 0x10 477 #define AMDGPU_INFO_GTT_USAGE 0x11 478 #define AMDGPU_INFO_GDS_CONFIG 0x13 479 #define AMDGPU_INFO_VRAM_GTT 0x14 480 #define AMDGPU_INFO_READ_MMR_REG 0x15 481 #define AMDGPU_INFO_DEV_INFO 0x16 482 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 483 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 484 #define AMDGPU_INFO_MEMORY 0x19 485 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 486 #define AMDGPU_INFO_VBIOS 0x1B 487 488 #define AMDGPU_INFO_VBIOS_SIZE 0x1 489 490 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 491 #define AMDGPU_INFO_NUM_HANDLES 0x1C 492 #define AMDGPU_INFO_SENSOR 0x1D 493 494 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 495 496 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 497 498 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 499 500 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 501 502 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 503 504 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 505 506 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 507 508 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 509 510 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 511 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 512 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 513 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 514 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 515 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 516 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 517 struct drm_amdgpu_query_fw { 518 519 __u32 fw_type; 520 521 __u32 ip_instance; 522 523 __u32 index; 524 __u32 _pad; 525 }; 526 struct drm_amdgpu_info { 527 528 __u64 return_pointer; 529 530 __u32 return_size; 531 532 __u32 query; 533 union { 534 struct { 535 __u32 id; 536 __u32 _pad; 537 } mode_crtc; 538 struct { 539 540 __u32 type; 541 542 __u32 ip_instance; 543 } query_hw_ip; 544 struct { 545 __u32 dword_offset; 546 547 __u32 count; 548 __u32 instance; 549 550 __u32 flags; 551 } read_mmr_reg; 552 struct drm_amdgpu_query_fw query_fw; 553 struct { 554 __u32 type; 555 __u32 offset; 556 } vbios_info; 557 struct { 558 __u32 type; 559 } sensor_info; 560 }; 561 }; 562 struct drm_amdgpu_info_gds { 563 564 __u32 gds_gfx_partition_size; 565 566 __u32 compute_partition_size; 567 568 __u32 gds_total_size; 569 570 __u32 gws_per_gfx_partition; 571 572 __u32 gws_per_compute_partition; 573 574 __u32 oa_per_gfx_partition; 575 576 __u32 oa_per_compute_partition; 577 __u32 _pad; 578 }; 579 struct drm_amdgpu_info_vram_gtt { 580 __u64 vram_size; 581 __u64 vram_cpu_accessible_size; 582 __u64 gtt_size; 583 }; 584 struct drm_amdgpu_heap_info { 585 586 __u64 total_heap_size; 587 588 __u64 usable_heap_size; 589 590 __u64 heap_usage; 591 592 __u64 max_allocation; 593 }; 594 struct drm_amdgpu_memory_info { 595 struct drm_amdgpu_heap_info vram; 596 struct drm_amdgpu_heap_info cpu_accessible_vram; 597 struct drm_amdgpu_heap_info gtt; 598 }; 599 struct drm_amdgpu_info_firmware { 600 __u32 ver; 601 __u32 feature; 602 }; 603 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 604 #define AMDGPU_VRAM_TYPE_GDDR1 1 605 #define AMDGPU_VRAM_TYPE_DDR2 2 606 #define AMDGPU_VRAM_TYPE_GDDR3 3 607 #define AMDGPU_VRAM_TYPE_GDDR4 4 608 #define AMDGPU_VRAM_TYPE_GDDR5 5 609 #define AMDGPU_VRAM_TYPE_HBM 6 610 #define AMDGPU_VRAM_TYPE_DDR3 7 611 #define AMDGPU_VRAM_TYPE_DDR4 8 612 struct drm_amdgpu_info_device { 613 614 __u32 device_id; 615 616 __u32 chip_rev; 617 __u32 external_rev; 618 619 __u32 pci_rev; 620 __u32 family; 621 __u32 num_shader_engines; 622 __u32 num_shader_arrays_per_engine; 623 624 __u32 gpu_counter_freq; 625 __u64 max_engine_clock; 626 __u64 max_memory_clock; 627 628 __u32 cu_active_number; 629 630 __u32 cu_ao_mask; 631 __u32 cu_bitmap[4][4]; 632 633 __u32 enabled_rb_pipes_mask; 634 __u32 num_rb_pipes; 635 __u32 num_hw_gfx_contexts; 636 __u32 _pad; 637 __u64 ids_flags; 638 639 __u64 virtual_address_offset; 640 641 __u64 virtual_address_max; 642 643 __u32 virtual_address_alignment; 644 645 __u32 pte_fragment_size; 646 __u32 gart_page_size; 647 648 __u32 ce_ram_size; 649 650 __u32 vram_type; 651 652 __u32 vram_bit_width; 653 654 __u32 vce_harvest_config; 655 656 __u32 gc_double_offchip_lds_buf; 657 658 __u64 prim_buf_gpu_addr; 659 660 __u64 pos_buf_gpu_addr; 661 662 __u64 cntl_sb_buf_gpu_addr; 663 664 __u64 param_buf_gpu_addr; 665 __u32 prim_buf_size; 666 __u32 pos_buf_size; 667 __u32 cntl_sb_buf_size; 668 __u32 param_buf_size; 669 670 __u32 wave_front_size; 671 672 __u32 num_shader_visible_vgprs; 673 674 __u32 num_cu_per_sh; 675 676 __u32 num_tcc_blocks; 677 678 __u32 gs_vgt_table_depth; 679 680 __u32 gs_prim_buffer_depth; 681 682 __u32 max_gs_waves_per_vgt; 683 __u32 _pad1; 684 685 __u32 cu_ao_bitmap[4][4]; 686 687 __u64 high_va_offset; 688 689 __u64 high_va_max; 690 }; 691 struct drm_amdgpu_info_hw_ip { 692 693 __u32 hw_ip_version_major; 694 __u32 hw_ip_version_minor; 695 696 __u64 capabilities_flags; 697 698 __u32 ib_start_alignment; 699 700 __u32 ib_size_alignment; 701 702 __u32 available_rings; 703 __u32 _pad; 704 }; 705 struct drm_amdgpu_info_num_handles { 706 707 __u32 uvd_max_handles; 708 709 __u32 uvd_used_handles; 710 }; 711 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 712 struct drm_amdgpu_info_vce_clock_table_entry { 713 714 __u32 sclk; 715 716 __u32 mclk; 717 718 __u32 eclk; 719 __u32 pad; 720 }; 721 struct drm_amdgpu_info_vce_clock_table { 722 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 723 __u32 num_valid_entries; 724 __u32 pad; 725 }; 726 #define AMDGPU_FAMILY_UNKNOWN 0 727 #define AMDGPU_FAMILY_SI 110 728 #define AMDGPU_FAMILY_CI 120 729 #define AMDGPU_FAMILY_KV 125 730 #define AMDGPU_FAMILY_VI 130 731 #define AMDGPU_FAMILY_CZ 135 732 #define AMDGPU_FAMILY_AI 141 733 #define AMDGPU_FAMILY_RV 142 734 #if defined(__cplusplus) 735 } 736 #endif 737 #endif 738