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1 /*
2  * This header was generated from the Linux kernel headers by update_headers.py,
3  * to provide necessary information from kernel to userspace, such as constants,
4  * structures, and macros, and thus, contains no copyrightable information.
5  */
6 #ifndef _V3D_DRM_H_
7 #define _V3D_DRM_H_
8 #include "drm.h"
9 #if defined(__cplusplus)
10 extern "C" {
11 #endif
12 #define DRM_V3D_SUBMIT_CL                         0x00
13 #define DRM_V3D_WAIT_BO                           0x01
14 #define DRM_V3D_CREATE_BO                         0x02
15 #define DRM_V3D_MMAP_BO                           0x03
16 #define DRM_V3D_GET_PARAM                         0x04
17 #define DRM_V3D_GET_BO_OFFSET                     0x05
18 #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
19 #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
20 #define DRM_IOCTL_V3D_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
21 #define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
22 #define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
23 #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
24 struct drm_v3d_submit_cl {
25 
26 	__u32 bcl_start;
27 
28 	__u32 bcl_end;
29 
30 	__u32 rcl_start;
31 
32 	__u32 rcl_end;
33 
34 	__u32 in_sync_bcl;
35 
36 	__u32 in_sync_rcl;
37 
38 	__u32 out_sync;
39 
40 	__u32 qma;
41 
42 	__u32 qms;
43 
44 	__u32 qts;
45 
46 	__u64 bo_handles;
47 
48 	__u32 bo_handle_count;
49 
50 	__u32 pad;
51 };
52 struct drm_v3d_wait_bo {
53 	__u32 handle;
54 	__u32 pad;
55 	__u64 timeout_ns;
56 };
57 struct drm_v3d_create_bo {
58 	__u32 size;
59 	__u32 flags;
60 
61 	__u32 handle;
62 
63 	__u32 offset;
64 };
65 struct drm_v3d_mmap_bo {
66 
67 	__u32 handle;
68 	__u32 flags;
69 
70 	__u64 offset;
71 };
72 enum drm_v3d_param {
73 	DRM_V3D_PARAM_V3D_UIFCFG,
74 	DRM_V3D_PARAM_V3D_HUB_IDENT1,
75 	DRM_V3D_PARAM_V3D_HUB_IDENT2,
76 	DRM_V3D_PARAM_V3D_HUB_IDENT3,
77 	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
78 	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
79 	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
80 };
81 struct drm_v3d_get_param {
82 	__u32 param;
83 	__u32 pad;
84 	__u64 value;
85 };
86 struct drm_v3d_get_bo_offset {
87 	__u32 handle;
88 	__u32 offset;
89 };
90 #if defined(__cplusplus)
91 }
92 #endif
93 #endif
94