1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef __VMW_PVRDMA_ABI_H__ 7 #define __VMW_PVRDMA_ABI_H__ 8 #include <linux/types.h> 9 #define PVRDMA_UVERBS_ABI_VERSION 3 10 #define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF 11 #define PVRDMA_UAR_QP_OFFSET 0 12 #define PVRDMA_UAR_QP_SEND (1 << 30) 13 #define PVRDMA_UAR_QP_RECV (1 << 31) 14 #define PVRDMA_UAR_CQ_OFFSET 4 15 #define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) 16 #define PVRDMA_UAR_CQ_ARM (1 << 30) 17 #define PVRDMA_UAR_CQ_POLL (1 << 31) 18 #define PVRDMA_UAR_SRQ_OFFSET 8 19 #define PVRDMA_UAR_SRQ_RECV (1 << 30) 20 enum pvrdma_wr_opcode { 21 PVRDMA_WR_RDMA_WRITE, 22 PVRDMA_WR_RDMA_WRITE_WITH_IMM, 23 PVRDMA_WR_SEND, 24 PVRDMA_WR_SEND_WITH_IMM, 25 PVRDMA_WR_RDMA_READ, 26 PVRDMA_WR_ATOMIC_CMP_AND_SWP, 27 PVRDMA_WR_ATOMIC_FETCH_AND_ADD, 28 PVRDMA_WR_LSO, 29 PVRDMA_WR_SEND_WITH_INV, 30 PVRDMA_WR_RDMA_READ_WITH_INV, 31 PVRDMA_WR_LOCAL_INV, 32 PVRDMA_WR_FAST_REG_MR, 33 PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP, 34 PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD, 35 PVRDMA_WR_BIND_MW, 36 PVRDMA_WR_REG_SIG_MR, 37 PVRDMA_WR_ERROR, 38 }; 39 enum pvrdma_wc_status { 40 PVRDMA_WC_SUCCESS, 41 PVRDMA_WC_LOC_LEN_ERR, 42 PVRDMA_WC_LOC_QP_OP_ERR, 43 PVRDMA_WC_LOC_EEC_OP_ERR, 44 PVRDMA_WC_LOC_PROT_ERR, 45 PVRDMA_WC_WR_FLUSH_ERR, 46 PVRDMA_WC_MW_BIND_ERR, 47 PVRDMA_WC_BAD_RESP_ERR, 48 PVRDMA_WC_LOC_ACCESS_ERR, 49 PVRDMA_WC_REM_INV_REQ_ERR, 50 PVRDMA_WC_REM_ACCESS_ERR, 51 PVRDMA_WC_REM_OP_ERR, 52 PVRDMA_WC_RETRY_EXC_ERR, 53 PVRDMA_WC_RNR_RETRY_EXC_ERR, 54 PVRDMA_WC_LOC_RDD_VIOL_ERR, 55 PVRDMA_WC_REM_INV_RD_REQ_ERR, 56 PVRDMA_WC_REM_ABORT_ERR, 57 PVRDMA_WC_INV_EECN_ERR, 58 PVRDMA_WC_INV_EEC_STATE_ERR, 59 PVRDMA_WC_FATAL_ERR, 60 PVRDMA_WC_RESP_TIMEOUT_ERR, 61 PVRDMA_WC_GENERAL_ERR, 62 }; 63 enum pvrdma_wc_opcode { 64 PVRDMA_WC_SEND, 65 PVRDMA_WC_RDMA_WRITE, 66 PVRDMA_WC_RDMA_READ, 67 PVRDMA_WC_COMP_SWAP, 68 PVRDMA_WC_FETCH_ADD, 69 PVRDMA_WC_BIND_MW, 70 PVRDMA_WC_LSO, 71 PVRDMA_WC_LOCAL_INV, 72 PVRDMA_WC_FAST_REG_MR, 73 PVRDMA_WC_MASKED_COMP_SWAP, 74 PVRDMA_WC_MASKED_FETCH_ADD, 75 PVRDMA_WC_RECV = 1 << 7, 76 PVRDMA_WC_RECV_RDMA_WITH_IMM, 77 }; 78 enum pvrdma_wc_flags { 79 PVRDMA_WC_GRH = 1 << 0, 80 PVRDMA_WC_WITH_IMM = 1 << 1, 81 PVRDMA_WC_WITH_INVALIDATE = 1 << 2, 82 PVRDMA_WC_IP_CSUM_OK = 1 << 3, 83 PVRDMA_WC_WITH_SMAC = 1 << 4, 84 PVRDMA_WC_WITH_VLAN = 1 << 5, 85 PVRDMA_WC_WITH_NETWORK_HDR_TYPE = 1 << 6, 86 PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_NETWORK_HDR_TYPE, 87 }; 88 struct pvrdma_alloc_ucontext_resp { 89 __u32 qp_tab_size; 90 __u32 reserved; 91 }; 92 struct pvrdma_alloc_pd_resp { 93 __u32 pdn; 94 __u32 reserved; 95 }; 96 struct pvrdma_create_cq { 97 __aligned_u64 buf_addr; 98 __u32 buf_size; 99 __u32 reserved; 100 }; 101 struct pvrdma_create_cq_resp { 102 __u32 cqn; 103 __u32 reserved; 104 }; 105 struct pvrdma_resize_cq { 106 __aligned_u64 buf_addr; 107 __u32 buf_size; 108 __u32 reserved; 109 }; 110 struct pvrdma_create_srq { 111 __aligned_u64 buf_addr; 112 __u32 buf_size; 113 __u32 reserved; 114 }; 115 struct pvrdma_create_srq_resp { 116 __u32 srqn; 117 __u32 reserved; 118 }; 119 struct pvrdma_create_qp { 120 __aligned_u64 rbuf_addr; 121 __aligned_u64 sbuf_addr; 122 __u32 rbuf_size; 123 __u32 sbuf_size; 124 __aligned_u64 qp_addr; 125 }; 126 struct pvrdma_ex_cmp_swap { 127 __aligned_u64 swap_val; 128 __aligned_u64 compare_val; 129 __aligned_u64 swap_mask; 130 __aligned_u64 compare_mask; 131 }; 132 struct pvrdma_ex_fetch_add { 133 __aligned_u64 add_val; 134 __aligned_u64 field_boundary; 135 }; 136 struct pvrdma_av { 137 __u32 port_pd; 138 __u32 sl_tclass_flowlabel; 139 __u8 dgid[16]; 140 __u8 src_path_bits; 141 __u8 gid_index; 142 __u8 stat_rate; 143 __u8 hop_limit; 144 __u8 dmac[6]; 145 __u8 reserved[6]; 146 }; 147 struct pvrdma_sge { 148 __aligned_u64 addr; 149 __u32 length; 150 __u32 lkey; 151 }; 152 struct pvrdma_rq_wqe_hdr { 153 __aligned_u64 wr_id; 154 __u32 num_sge; 155 __u32 total_len; 156 }; 157 struct pvrdma_sq_wqe_hdr { 158 __aligned_u64 wr_id; 159 __u32 num_sge; 160 __u32 total_len; 161 __u32 opcode; 162 __u32 send_flags; 163 union { 164 __be32 imm_data; 165 __u32 invalidate_rkey; 166 } ex; 167 __u32 reserved; 168 union { 169 struct { 170 __aligned_u64 remote_addr; 171 __u32 rkey; 172 __u8 reserved[4]; 173 } rdma; 174 struct { 175 __aligned_u64 remote_addr; 176 __aligned_u64 compare_add; 177 __aligned_u64 swap; 178 __u32 rkey; 179 __u32 reserved; 180 } atomic; 181 struct { 182 __aligned_u64 remote_addr; 183 __u32 log_arg_sz; 184 __u32 rkey; 185 union { 186 struct pvrdma_ex_cmp_swap cmp_swap; 187 struct pvrdma_ex_fetch_add fetch_add; 188 } wr_data; 189 } masked_atomics; 190 struct { 191 __aligned_u64 iova_start; 192 __aligned_u64 pl_pdir_dma; 193 __u32 page_shift; 194 __u32 page_list_len; 195 __u32 length; 196 __u32 access_flags; 197 __u32 rkey; 198 __u32 reserved; 199 } fast_reg; 200 struct { 201 __u32 remote_qpn; 202 __u32 remote_qkey; 203 struct pvrdma_av av; 204 } ud; 205 } wr; 206 }; 207 struct pvrdma_cqe { 208 __aligned_u64 wr_id; 209 __aligned_u64 qp; 210 __u32 opcode; 211 __u32 status; 212 __u32 byte_len; 213 __be32 imm_data; 214 __u32 src_qp; 215 __u32 wc_flags; 216 __u32 vendor_err; 217 __u16 pkey_index; 218 __u16 slid; 219 __u8 sl; 220 __u8 dlid_path_bits; 221 __u8 port_num; 222 __u8 smac[6]; 223 __u8 network_hdr_type; 224 __u8 reserved2[6]; 225 }; 226 #endif 227