1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef __HDA_TPLG_INTERFACE_H__ 7 #define __HDA_TPLG_INTERFACE_H__ 8 #include <linux/types.h> 9 #define SKL_CONTROL_TYPE_BYTE_TLV 0x100 10 #define SKL_CONTROL_TYPE_MIC_SELECT 0x102 11 #define HDA_SST_CFG_MAX 900 12 #define MAX_IN_QUEUE 8 13 #define MAX_OUT_QUEUE 8 14 #define SKL_UUID_STR_SZ 40 15 enum skl_event_types { 16 SKL_EVENT_NONE = 0, 17 SKL_MIXER_EVENT, 18 SKL_MUX_EVENT, 19 SKL_VMIXER_EVENT, 20 SKL_PGA_EVENT 21 }; 22 enum skl_ch_cfg { 23 SKL_CH_CFG_MONO = 0, 24 SKL_CH_CFG_STEREO = 1, 25 SKL_CH_CFG_2_1 = 2, 26 SKL_CH_CFG_3_0 = 3, 27 SKL_CH_CFG_3_1 = 4, 28 SKL_CH_CFG_QUATRO = 5, 29 SKL_CH_CFG_4_0 = 6, 30 SKL_CH_CFG_5_0 = 7, 31 SKL_CH_CFG_5_1 = 8, 32 SKL_CH_CFG_DUAL_MONO = 9, 33 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10, 34 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11, 35 SKL_CH_CFG_4_CHANNEL = 12, 36 SKL_CH_CFG_INVALID 37 }; 38 enum skl_module_type { 39 SKL_MODULE_TYPE_MIXER = 0, 40 SKL_MODULE_TYPE_COPIER, 41 SKL_MODULE_TYPE_UPDWMIX, 42 SKL_MODULE_TYPE_SRCINT, 43 SKL_MODULE_TYPE_ALGO, 44 SKL_MODULE_TYPE_BASE_OUTFMT, 45 SKL_MODULE_TYPE_KPB, 46 SKL_MODULE_TYPE_MIC_SELECT, 47 }; 48 enum skl_core_affinity { 49 SKL_AFFINITY_CORE_0 = 0, 50 SKL_AFFINITY_CORE_1, 51 SKL_AFFINITY_CORE_MAX 52 }; 53 enum skl_pipe_conn_type { 54 SKL_PIPE_CONN_TYPE_NONE = 0, 55 SKL_PIPE_CONN_TYPE_FE, 56 SKL_PIPE_CONN_TYPE_BE 57 }; 58 enum skl_hw_conn_type { 59 SKL_CONN_NONE = 0, 60 SKL_CONN_SOURCE = 1, 61 SKL_CONN_SINK = 2 62 }; 63 enum skl_dev_type { 64 SKL_DEVICE_BT = 0x0, 65 SKL_DEVICE_DMIC = 0x1, 66 SKL_DEVICE_I2S = 0x2, 67 SKL_DEVICE_SLIMBUS = 0x3, 68 SKL_DEVICE_HDALINK = 0x4, 69 SKL_DEVICE_HDAHOST = 0x5, 70 SKL_DEVICE_NONE 71 }; 72 enum skl_interleaving { 73 SKL_INTERLEAVING_PER_CHANNEL = 0, 74 SKL_INTERLEAVING_PER_SAMPLE = 1, 75 }; 76 enum skl_sample_type { 77 SKL_SAMPLE_TYPE_INT_MSB = 0, 78 SKL_SAMPLE_TYPE_INT_LSB = 1, 79 SKL_SAMPLE_TYPE_INT_SIGNED = 2, 80 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3, 81 SKL_SAMPLE_TYPE_FLOAT = 4 82 }; 83 enum module_pin_type { 84 85 SKL_PIN_TYPE_HOMOGENEOUS, 86 87 SKL_PIN_TYPE_HETEROGENEOUS, 88 }; 89 enum skl_module_param_type { 90 SKL_PARAM_DEFAULT = 0, 91 SKL_PARAM_INIT, 92 SKL_PARAM_SET, 93 SKL_PARAM_BIND 94 }; 95 struct skl_dfw_algo_data { 96 __u32 set_params:2; 97 __u32 rsvd:30; 98 __u32 param_id; 99 __u32 max; 100 char params[0]; 101 } __packed; 102 enum skl_tkn_dir { 103 SKL_DIR_IN, 104 SKL_DIR_OUT 105 }; 106 enum skl_tuple_type { 107 SKL_TYPE_TUPLE, 108 SKL_TYPE_DATA 109 }; 110 struct skl_dfw_v4_module_pin { 111 __u16 module_id; 112 __u16 instance_id; 113 } __packed; 114 struct skl_dfw_v4_module_fmt { 115 __u32 channels; 116 __u32 freq; 117 __u32 bit_depth; 118 __u32 valid_bit_depth; 119 __u32 ch_cfg; 120 __u32 interleaving_style; 121 __u32 sample_type; 122 __u32 ch_map; 123 } __packed; 124 struct skl_dfw_v4_module_caps { 125 __u32 set_params:2; 126 __u32 rsvd:30; 127 __u32 param_id; 128 __u32 caps_size; 129 __u32 caps[HDA_SST_CFG_MAX]; 130 } __packed; 131 struct skl_dfw_v4_pipe { 132 __u8 pipe_id; 133 __u8 pipe_priority; 134 __u16 conn_type:4; 135 __u16 rsvd:4; 136 __u16 memory_pages:8; 137 } __packed; 138 struct skl_dfw_v4_module { 139 char uuid[SKL_UUID_STR_SZ]; 140 __u16 module_id; 141 __u16 instance_id; 142 __u32 max_mcps; 143 __u32 mem_pages; 144 __u32 obs; 145 __u32 ibs; 146 __u32 vbus_id; 147 __u32 max_in_queue:8; 148 __u32 max_out_queue:8; 149 __u32 time_slot:8; 150 __u32 core_id:4; 151 __u32 rsvd1:4; 152 __u32 module_type:8; 153 __u32 conn_type:4; 154 __u32 dev_type:4; 155 __u32 hw_conn_type:4; 156 __u32 rsvd2:12; 157 __u32 params_fixup:8; 158 __u32 converter:8; 159 __u32 input_pin_type:1; 160 __u32 output_pin_type:1; 161 __u32 is_dynamic_in_pin:1; 162 __u32 is_dynamic_out_pin:1; 163 __u32 is_loadable:1; 164 __u32 rsvd3:11; 165 struct skl_dfw_v4_pipe pipe; 166 struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE]; 167 struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE]; 168 struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE]; 169 struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE]; 170 struct skl_dfw_v4_module_caps caps; 171 } __packed; 172 #endif 173