1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <stdarg.h>
33 #include "securec.h"
34 #include "los_context.h"
35 #include "los_arch_interrupt.h"
36 #include "los_hook.h"
37 #include "los_task.h"
38 #include "los_sched.h"
39 #include "los_memory.h"
40 #include "los_membox.h"
41 #if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
42 #include "los_cpup.h"
43 #endif
44
45 /* ****************************************************************************
46 Function : HwiNumGet
47 Description : Get an interrupt number
48 Input : None
49 Output : None
50 Return : Interrupt Indexes number
51 **************************************************************************** */
HwiNumGet(VOID)52 STATIC UINT32 HwiNumGet(VOID)
53 {
54 return __get_IPSR();
55 }
56
HwiUnmask(HWI_HANDLE_T hwiNum)57 STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
58 {
59 NVIC_EnableIRQ((IRQn_Type)hwiNum);
60 return LOS_OK;
61 }
62
HwiMask(HWI_HANDLE_T hwiNum)63 STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
64 {
65 NVIC_DisableIRQ((IRQn_Type)hwiNum);
66 return LOS_OK;
67 }
68
HwiSetPriority(HWI_HANDLE_T hwiNum,UINT8 priority)69 STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
70 {
71 NVIC_SetPriority((IRQn_Type)hwiNum, priority);
72 return LOS_OK;
73 }
74
HwiPending(HWI_HANDLE_T hwiNum)75 STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
76 {
77 NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
78 return LOS_OK;
79 }
80
HwiClear(HWI_HANDLE_T hwiNum)81 STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
82 {
83 NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
84 return LOS_OK;
85 }
86
HwiCreate(HWI_HANDLE_T hwiNum,HWI_PRIOR_T hwiPrio)87 STATIC UINT32 HwiCreate(HWI_HANDLE_T hwiNum, HWI_PRIOR_T hwiPrio)
88 {
89 HwiSetPriority(hwiNum, hwiPrio);
90 HwiUnmask(hwiNum);
91 return LOS_OK;
92 }
93
94 STATIC HwiControllerOps g_archHwiOps = {
95 .enableIrq = HwiUnmask,
96 .disableIrq = HwiMask,
97 .setIrqPriority = HwiSetPriority,
98 .getCurIrqNum = HwiNumGet,
99 .triggerIrq = HwiPending,
100 .clearIrq = HwiClear,
101 .createIrq = HwiCreate,
102 };
103
ArchIntOpsGet(VOID)104 HwiControllerOps *ArchIntOpsGet(VOID)
105 {
106 return &g_archHwiOps;
107 }
108
109 /* ****************************************************************************
110 Function : HalInterrupt
111 Description : Hardware interrupt entry function
112 Input : None
113 Output : None
114 Return : None
115 **************************************************************************** */
HalInterrupt(VOID)116 LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
117 {
118 UINT32 hwiIndex;
119 UINT32 intSave;
120
121 #if (LOSCFG_KERNEL_RUNSTOP == 1)
122 SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
123 #endif
124
125 intSave = LOS_IntLock();
126 g_intCount++;
127 LOS_IntRestore(intSave);
128
129 hwiIndex = HwiNumGet();
130
131 OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
132 #if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
133 OsCpupIrqStart(hwiIndex);
134 #endif
135
136 HalPreInterruptHandler(hwiIndex);
137
138 #if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
139 if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
140 g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
141 }
142 #else
143 if (g_hwiHandlerForm[hwiIndex] != 0) {
144 g_hwiHandlerForm[hwiIndex]();
145 }
146 #endif
147
148 #if (LOSCFG_DEBUG_TOOLS == 1)
149 ++g_hwiFormCnt[hwiIndex];
150 #endif
151
152 HalAftInterruptHandler(hwiIndex);
153
154 #if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
155 OsCpupIrqEnd(hwiIndex);
156 #endif
157
158 OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
159
160 intSave = LOS_IntLock();
161 g_intCount--;
162 LOS_IntRestore(intSave);
163 }
164
165 #define FAULT_STATUS_REG_BIT 32
166 #define USGFAULT (1 << 18)
167 #define BUSFAULT (1 << 17)
168 #define MEMFAULT (1 << 16)
169 #define DIV0FAULT (1 << 4)
170 #define UNALIGNFAULT (1 << 3)
171 #define HARDFAULT_IRQN (-13)
172
173 ExcInfo g_excInfo = {0};
174
175 UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
176 0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
177 0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
178 0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
179 0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
180 };
181
182 #if (LOSCFG_KERNEL_PRINTF != 0)
OsExcNvicDump(VOID)183 STATIC VOID OsExcNvicDump(VOID)
184 {
185 #define OS_NR_NVIC_EXC_DUMP_TYPES 7
186 UINT32 *base = NULL;
187 UINT32 len, i, j;
188 UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
189 OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
190 OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
191 };
192 UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
193 OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
194 OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
195 OS_NVIC_INT_CTRL_SIZE
196 };
197 CHAR strRgEnable[] = "enable";
198 CHAR strRgPending[] = "pending";
199 CHAR strRgActive[] = "active";
200 CHAR strRgPriority[] = "priority";
201 CHAR strRgException[] = "exception";
202 CHAR strRgShcsr[] = "shcsr";
203 CHAR strRgIntCtrl[] = "control";
204 CHAR *strRgs[] = {
205 strRgEnable, strRgPending, strRgActive, strRgPriority,
206 strRgException, strRgShcsr, strRgIntCtrl
207 };
208
209 PRINTK("\r\nOS exception NVIC dump:\n");
210 for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
211 base = (UINT32 *)rgNvicBases[i];
212 len = rgNvicLens[i];
213 PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
214 len = (len >> 2); /* 2: Gets the next register offset */
215 for (j = 0; j < len; j++) {
216 PRINTK("0x%x ", *(base + j));
217 if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
218 PRINTK("\n");
219 }
220 }
221 PRINTK("\n");
222 }
223 }
224
OsExcTypeInfo(const ExcInfo * excInfo)225 STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
226 {
227 CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
228
229 PRINTK("Type = %d\n", excInfo->type);
230 PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
231 PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
232 PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
233 }
234
OsExcCurTaskInfo(const ExcInfo * excInfo)235 STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
236 {
237 PRINTK("Current task info:\n");
238 if (excInfo->phase == OS_EXC_IN_TASK) {
239 LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
240 PRINTK("Task name = %s\n", taskCB->taskName);
241 PRINTK("Task ID = %d\n", taskCB->taskID);
242 PRINTK("Task SP = %p\n", taskCB->stackPointer);
243 PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
244 PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
245 } else if (excInfo->phase == OS_EXC_IN_HWI) {
246 PRINTK("Exception occur in interrupt phase!\n");
247 } else {
248 PRINTK("Exception occur in system init phase!\n");
249 }
250 }
251
OsExcRegInfo(const ExcInfo * excInfo)252 STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
253 {
254 PRINTK("Exception reg dump:\n");
255 PRINTK("PC = 0x%x\n", excInfo->context->uwPC);
256 PRINTK("LR = 0x%x\n", excInfo->context->uwLR);
257 PRINTK("SP = 0x%x\n", excInfo->context->uwSP);
258 PRINTK("R0 = 0x%x\n", excInfo->context->uwR0);
259 PRINTK("R1 = 0x%x\n", excInfo->context->uwR1);
260 PRINTK("R2 = 0x%x\n", excInfo->context->uwR2);
261 PRINTK("R3 = 0x%x\n", excInfo->context->uwR3);
262 PRINTK("R4 = 0x%x\n", excInfo->context->uwR4);
263 PRINTK("R5 = 0x%x\n", excInfo->context->uwR5);
264 PRINTK("R6 = 0x%x\n", excInfo->context->uwR6);
265 PRINTK("R7 = 0x%x\n", excInfo->context->uwR7);
266 PRINTK("R8 = 0x%x\n", excInfo->context->uwR8);
267 PRINTK("R9 = 0x%x\n", excInfo->context->uwR9);
268 PRINTK("R10 = 0x%x\n", excInfo->context->uwR10);
269 PRINTK("R11 = 0x%x\n", excInfo->context->uwR11);
270 PRINTK("R12 = 0x%x\n", excInfo->context->uwR12);
271 PRINTK("PriMask = 0x%x\n", excInfo->context->uwPriMask);
272 PRINTK("xPSR = 0x%x\n", excInfo->context->uwxPSR);
273 }
274
275 #if (LOSCFG_KERNEL_BACKTRACE == 1)
OsExcBackTraceInfo(const ExcInfo * excInfo)276 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
277 {
278 UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
279 UINT32 index;
280
281 OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
282
283 PRINTK("----- backtrace start -----\n");
284 for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
285 if (LR[index] == 0) {
286 break;
287 }
288 PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
289 }
290 PRINTK("----- backtrace end -----\n");
291 }
292 #endif
293
OsExcMemPoolCheckInfo(VOID)294 STATIC VOID OsExcMemPoolCheckInfo(VOID)
295 {
296 PRINTK("\r\nmemory pools check:\n");
297 #if (LOSCFG_PLATFORM_EXC == 1)
298 MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
299 UINT32 errCnt;
300 UINT32 i;
301
302 (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
303
304 errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
305 if (errCnt < OS_SYS_MEM_NUM) {
306 errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
307 }
308
309 if (errCnt == 0) {
310 PRINTK("all memory pool check passed!\n");
311 return;
312 }
313
314 for (i = 0; i < errCnt; i++) {
315 PRINTK("pool num = %d\n", i);
316 PRINTK("pool type = %d\n", memExcInfo[i].type);
317 PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
318 PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
319 PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
320 PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
321 PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
322 PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
323 PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
324 }
325 #endif
326 UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
327 if (ret == LOS_OK) {
328 PRINTK("system heap memcheck over, all passed!\n");
329 }
330
331 PRINTK("memory pool check end!\n");
332 }
333 #endif
334
OsExcInfoDisplay(const ExcInfo * excInfo)335 STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
336 {
337 #if (LOSCFG_KERNEL_PRINTF != 0)
338 PRINTK("*************Exception Information**************\n");
339 OsExcTypeInfo(excInfo);
340 OsExcCurTaskInfo(excInfo);
341 OsExcRegInfo(excInfo);
342 #if (LOSCFG_KERNEL_BACKTRACE == 1)
343 OsExcBackTraceInfo(excInfo);
344 #endif
345 OsGetAllTskInfo();
346 OsExcNvicDump();
347 OsExcMemPoolCheckInfo();
348 #endif
349 }
350
HalExcHandleEntry(UINT32 excType,UINT32 faultAddr,UINT32 pid,EXC_CONTEXT_S * excBufAddr)351 LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
352 {
353 UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
354 g_intCount++;
355 g_excInfo.nestCnt++;
356
357 g_excInfo.type = excType & OS_NULL_SHORT;
358
359 if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
360 g_excInfo.faultAddr = faultAddr;
361 } else {
362 g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
363 }
364 if (g_losTask.runTask != NULL) {
365 if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
366 g_excInfo.phase = OS_EXC_IN_HWI;
367 g_excInfo.thrdPid = pid;
368 } else {
369 g_excInfo.phase = OS_EXC_IN_TASK;
370 g_excInfo.thrdPid = g_losTask.runTask->taskID;
371 }
372 } else {
373 g_excInfo.phase = OS_EXC_IN_INIT;
374 g_excInfo.thrdPid = OS_NULL_INT;
375 }
376 if (excType & OS_EXC_FLAG_NO_FLOAT) {
377 g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
378 } else {
379 g_excInfo.context = excBufAddr;
380 }
381
382 OsDoExcHook(EXC_INTERRUPT);
383 OsExcInfoDisplay(&g_excInfo);
384 ArchSysExit();
385 }
386
387 /* stack protector */
388 WEAK UINT32 __stack_chk_guard = 0xd00a0dff;
389
__stack_chk_fail(VOID)390 WEAK VOID __stack_chk_fail(VOID)
391 {
392 /* __builtin_return_address is a builtin function, building in gcc */
393 LOS_Panic("stack-protector: Kernel stack is corrupted in: %p\n",
394 __builtin_return_address(0));
395 }
396
SysTick_Handler(VOID)397 WEAK VOID SysTick_Handler(VOID)
398 {
399 return;
400 }
401
402 /* ****************************************************************************
403 Function : HalHwiInit
404 Description : initialization of the hardware interrupt
405 Input : None
406 Output : None
407 Return : None
408 **************************************************************************** */
HalHwiInit(VOID)409 LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
410 {
411 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
412 UINT32 index;
413 HWI_PROC_FUNC *hwiForm = (HWI_PROC_FUNC *)ArchGetHwiFrom();
414 hwiForm[0] = 0; /* [0] Top of Stack */
415 hwiForm[1] = (HWI_PROC_FUNC)Reset_Handler; /* [1] reset */
416 for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
417 hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
418 }
419 /* Exception handler register */
420 hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcNMI;
421 hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcHardFault;
422 hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault;
423 hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcBusFault;
424 hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcUsageFault;
425 hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcSvcCall;
426 hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalPendSV;
427 hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)SysTick_Handler;
428
429 /* Interrupt vector table location */
430 SCB->VTOR = (UINT32)(UINTPTR)hwiForm;
431 #endif
432 #if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
433 NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
434 #endif
435
436 /* Enable USGFAULT, BUSFAULT, MEMFAULT */
437 *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
438
439 /* Enable DIV 0 and unaligned exception */
440 #ifdef LOSCFG_ARCH_UNALIGNED_EXC
441 *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
442 #else
443 *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
444 #endif
445
446 return;
447 }
448