1/* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include "los_arch_regs.h" 33#include "los_arch_macro.h" 34 35.extern HalInterrupt 36.extern UserException 37 38.section .iram,"ax" 39.literal_position 40.type HandleEntry,@function 41.align 4 42HandleEntry: 43 44 mov a0, sp 45 addi sp, sp, -CONTEXT_SIZE 46 47 PUSH_ALL_REG a1 48 s32i a0, sp, CONTEXT_OFF_A1 49 rsr a0, EPC1 50 s32i a0, sp, CONTEXT_OFF_PC 51 rsr a0, EXCSAVE1 52 s32i a0, sp, CONTEXT_OFF_A0 53 54 wsr a1, EXCSAVE1 55 l32i a1, a1, CONTEXT_OFF_A1 56 call0 SpillWindow 57 rsr a1, EXCSAVE1 58 rsr a0, EXCCAUSE 59 s32i a0, sp, CONTEXT_OFF_EXCCAUSE 60 rsr a0, EXCVADDR 61 s32i a0, sp, CONTEXT_OFF_EXCVADDR 62 movi a0, INT_MASK | USER_VECTOR_MODE | WOE_ENABLE 63 wsr a0, PS 64 65 rsr a6, EPC1 66 mov a7, sp 67 rsr a8, EXCCAUSE 68 call4 HalExcHandleEntry 691: 70 j 1b 71 72.begin literal_prefix .DebugExceptionHandler 73.section .DebugExceptionHandler.text, "ax" 74.global DebugExceptionHandler 75.align 4 76.literal_position 77DebugExceptionHandler: 78 79 call0 UserException 80 81.end literal_prefix 82 83.begin literal_prefix .NMIExceptionHandler 84.section .NMIExceptionHandler.text, "ax" 85.global NMIExceptionHandler 86.align 4 87.literal_position 88NMIExceptionHandler: 89 90 call0 UserException 91 92.end literal_prefix 93 94.begin literal_prefix .DoubleExceptionHandler 95.section .DoubleExceptionHandler.text, "ax" 96.global DoubleExceptionHandler 97.align 4 98.literal_position 99DoubleExceptionHandler: 100 101 call0 UserException 102 103.end literal_prefix 104 105.begin literal_prefix .KernelExceptionHandler 106.section .KernelExceptionHandler.text, "ax" 107.global KernelExceptionHandler 108.align 4 109.literal_position 110KernelExceptionHandler: 111 112 wsr a0, EXCSAVE1 113 call0 KernelException 114 115.end literal_prefix 116 117.section .iram,"ax" 118.align 4 119KernelException: 120 121 movi a0,5 122 wsr a0,EXCCAUSE 123 call0 UserException 124 rfe 125 126.begin literal_prefix .UserExceptionHandler 127.section .UserExceptionHandler.text, "ax" 128.global UserExceptionHandler 129.type UserExceptionHandler,@function 130.align 4 131.literal_position 132UserExceptionHandler: 133 134 wsr a0, EXCSAVE1 135 call0 UserException 136 137.end literal_prefix 138 139.section .iram,"ax" 140.type UserException,@function 141.align 4 142UserException: 143 144 rsr a0, EXCCAUSE 145 beqi a0, LEVEL1_TINRERRUPT_CAUSE, InterruptEntry1 146 beqi a0, ALLOC_CAUSE, AllocHandel 147 call0 HandleEntry 1481: 149 j 1b 150 151.section .iram,"ax" 152.type AllocHandel,@function 153.align 4 154AllocHandel: 155 call0 AllocHandelEntry 156 157.section .iram,"ax" 158.type InterruptEntry1,@function 159.align 4 160InterruptEntry1: 161 162 mov a0, sp 163 addi sp, sp, -CONTEXT_SIZE 164 165 PUSH_ALL_REG a1 166 167 s32i a0, sp, CONTEXT_OFF_A1 168 rsr a0, EPC1 169 s32i a0, sp, CONTEXT_OFF_PC 170 rsr a0, EXCSAVE1 171 s32i a0, sp, CONTEXT_OFF_A0 172 173 wsr a1, EXCSAVE1 174 l32i a1, a1, CONTEXT_OFF_A1 175 call0 SpillWindow 176 rsr a1, EXCSAVE1 177 178 movi a0, LEVEL1_INT_MASK | USER_VECTOR_MODE | WOE_ENABLE 179 wsr a0, PS 180 rsync 181 182 call4 HalInterrupt 183 mov a2, a1 184 POP_ALL_REG a2 EPC1 PS 185 rfe 186 187.begin literal_prefix .InterruptEntry2 188.section .InterruptEntry2.text, "ax" 189.global InterruptEntry2 190.type InterruptEntry2,@function 191.align 4 192.literal_position 193InterruptEntry2: 194 195 wsr a0, EXCSAVE2 196 movi a4, LEVEL2 197 call0 HandleEntry 198 199.end literal_prefix 200 201.begin literal_prefix .InterruptEntry3 202.section .InterruptEntry3.text, "ax" 203.global InterruptEntry3 204.type InterruptEntry3,@function 205.align 4 206.literal_position 207InterruptEntry3: 208 209 wsr a0, EXCSAVE3 210 movi a4, LEVEL3 211 call0 HandleEntry 212 213.end literal_prefix 214 215.begin literal_prefix .InterruptEntry4 216.section .InterruptEntry4.text, "ax" 217.global InterruptEntry4 218.type InterruptEntry4,@function 219.align 4 220.literal_position 221InterruptEntry4: 222 223 wsr a0, EXCSAVE4 224 movi a4, LEVEL4 225 call0 HandleEntry 226 227.end literal_prefix 228 229.begin literal_prefix .InterruptEntry5 230.section .InterruptEntry5.text, "ax" 231.global InterruptEntry5 232.type InterruptEntry5,@function 233.align 4 234.literal_position 235InterruptEntry5: 236 237 wsr a0, EXCSAVE5 238 movi a4, LEVEL5 239 call0 HandleEntry 240 241.end literal_prefix 242 243.section .WindowVectors.text, "ax" 244 245.org 0x0 246.global OverFlowGroup1 247OverFlowGroup1: 248 249 addi a5, a5, -16 250 s32i a3, a5, 12 251 s32i a2, a5, 8 252 s32i a1, a5, 4 253 s32i a0, a5, 0 254 addi a5, a5, 16 255 rfwo 256 257.org 0x40 258.global UnderFlowGroup1 259UnderFlowGroup1: 260 261 addi a5, a5, -16 262 l32i a3, a5, 12 263 l32i a2, a5, 8 264 l32i a1, a5, 4 265 l32i a0, a5, 0 266 addi a5, a5, 16 267 rfwu 268 269.org 0x80 270.global OverFlowGroup2 271OverFlowGroup2: 272 273 addi a9, a9, -16 274 s32i a3, a9, 12 275 s32i a2, a9, 8 276 s32i a1, a9, 4 277 s32i a0, a9, 0 278 addi a9, a9, 16 279 280 addi a1, a1, -12 281 l32i a0, a1, 0 282 addi a1, a1, 12 283 284 addi a0, a0, -32 285 286 s32i a7, a0, 12 287 s32i a6, a0, 8 288 s32i a5, a0, 4 289 s32i a4, a0, 0 290 291 rfwo 292 293.org 0xC0 294.global UnderFlowGroup2 295UnderFlowGroup2: 296 297 addi a9, a9, -16 298 l32i a3, a9, 12 299 l32i a2, a9, 8 300 l32i a1, a9, 4 301 l32i a0, a9, 0 302 addi a9, a9, 16 303 304 addi a1, a1, -12 305 l32i a4, a1, 0 306 addi a1, a1, 12 307 308 addi a4, a4, -32 309 l32i a7, a4, 12 310 l32i a6, a4, 8 311 l32i a5, a4, 4 312 l32i a4, a4, 0 313 rfwu 314 315.org 0x100 316.global OverFlowGroup3 317OverFlowGroup3: 318 319 addi a13, a13, -16 320 s32i a3, a13, 12 321 s32i a2, a13, 8 322 s32i a1, a13, 4 323 s32i a0, a13, 0 324 addi a13, a13, 16 325 326 addi a1, a1, -12 327 l32i a0, a1, 0 328 addi a1, a1, 12 329 330 addi a0, a0, -48 331 332 s32i a11, a0, 28 333 s32i a10, a0, 24 334 s32i a9, a0, 20 335 s32i a8, a0, 16 336 s32i a7, a0, 12 337 s32i a6, a0, 8 338 s32i a5, a0, 4 339 s32i a4, a0, 0 340 rfwo 341 342.org 0x140 343.global UnderFlowGroup3 344UnderFlowGroup3: 345 346 addi a13, a13, -16 347 l32i a3, a13, 12 348 l32i a2, a13, 8 349 l32i a1, a13, 4 350 l32i a0, a13, 0 351 addi a13, a13, 16 352 353 addi a1, a1, -12 354 l32i a4, a1, 0 355 addi a1, a1, 12 356 357 addi a4, a4, -48 358 l32i a11, a0, 28 359 l32i a10, a0, 24 360 l32i a9, a0, 20 361 l32i a8, a0, 16 362 l32i a7, a4, 12 363 l32i a6, a4, 8 364 l32i a5, a4, 4 365 l32i a4, a4, 0 366 rfwu 367 368.section .userVector,"ax" 369.type AllocHandelEntry,@function 370.align 4 371AllocHandelEntry: 372 373 addi a1, a1, -(CONTEXT_OFF_A4 - CONTEXT_OFF_A0) 374 s32i a2, a1, (CONTEXT_OFF_A2 - CONTEXT_OFF_A0) 375 s32i a3, a1, (CONTEXT_OFF_A3 - CONTEXT_OFF_A0) 376 377 rsr a0, PS 378 rsr a2, WINDOWBASE 379 extui a3, a0, PS_OWB_SHIFT, WINDOWBASEBITS 380 xor a3, a3, a2 381 slli a3, a3, PS_OWB_SHIFT 382 xor a0, a0, a3 383 wsr a0, PS 384 rsr a0, EXCSAVE1 385 386 l32i a2, a1, (CONTEXT_OFF_A2 - CONTEXT_OFF_A0) 387 l32i a3, a1, (CONTEXT_OFF_A3 - CONTEXT_OFF_A0) 388 addi a1, a1, (CONTEXT_OFF_A4 - CONTEXT_OFF_A0) 389 rsync 390 391 rotw -1 392 bbci a4, HIGHBIT_CALLNMODE, UnderFlowGroup1 393 rotw -1 394 bbci a8, LOWBIT_CALLNMODE, UnderFlowGroup2 395 rotw -1 396 j UnderFlowGroup3 397 398.global EnableExceptionInterface 399.section .iram,"ax" 400.type EnableExceptionInterface,@function 401.align 4 402EnableExceptionInterface: 403 entry a1,16 404 retw 405