1 /* 2 * Copyright © 2021 Google 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef RADV_RT_COMMON_H 25 #define RADV_RT_COMMON_H 26 27 #include "nir/nir.h" 28 #include "nir/nir_builder.h" 29 #include "nir/nir_vulkan.h" 30 31 #include "compiler/spirv/spirv.h" 32 33 #include "radv_private.h" 34 35 void nir_sort_hit_pair(nir_builder *b, nir_variable *var_distances, nir_variable *var_indices, 36 uint32_t chan_1, uint32_t chan_2); 37 38 nir_ssa_def *intersect_ray_amd_software_box(struct radv_device *device, nir_builder *b, 39 nir_ssa_def *bvh_node, nir_ssa_def *ray_tmax, 40 nir_ssa_def *origin, nir_ssa_def *dir, 41 nir_ssa_def *inv_dir); 42 43 nir_ssa_def *intersect_ray_amd_software_tri(struct radv_device *device, nir_builder *b, 44 nir_ssa_def *bvh_node, nir_ssa_def *ray_tmax, 45 nir_ssa_def *origin, nir_ssa_def *dir, 46 nir_ssa_def *inv_dir); 47 48 nir_ssa_def *build_addr_to_node(nir_builder *b, nir_ssa_def *addr); 49 50 nir_ssa_def *build_node_to_addr(struct radv_device *device, nir_builder *b, nir_ssa_def *node); 51 52 nir_ssa_def *nir_build_vec3_mat_mult(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *matrix[], 53 bool translation); 54 55 nir_ssa_def *nir_build_vec3_mat_mult_pre(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *matrix[]); 56 57 void nir_build_wto_matrix_load(nir_builder *b, nir_ssa_def *instance_addr, nir_ssa_def **out); 58 59 nir_ssa_def *hit_is_opaque(nir_builder *b, nir_ssa_def *sbt_offset_and_flags, nir_ssa_def *flags, 60 nir_ssa_def *geometry_id_and_flags); 61 62 nir_ssa_def *create_bvh_descriptor(nir_builder *b); 63 64 /* 65 * A top-level AS can contain 2^24 children and a bottom-level AS can contain 2^24 66 * triangles. At a branching factor of 4, that means we may need up to 24 levels of box 67 * nodes + 1 triangle node 68 * + 1 instance node. Furthermore, when processing a box node, worst case we actually 69 * push all 4 children and remove one, so the DFS stack depth is box nodes * 3 + 2. 70 */ 71 #define MAX_STACK_ENTRY_COUNT 76 72 73 #endif 74