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1root {
2    platform {
3        template dai_controller {
4            match_attr = "";
5            serviceName = "";
6        }
7        controller_0x120c1020 :: dai_controller {
8            match_attr = "hdf_dai_driver";
9            serviceName = "dai_service";
10
11            idInfo {
12                    chipName = "rk3568";
13                    chipIdRegister = 0xfe410000;
14                    chipIdSize = 0x1000;
15                }
16
17            regConfig {
18
19                 /*  reg: register address
20                     rreg: register address
21                     shift: shift bits
22                     rshift: rshift bits
23                     min: min value
24                     max: max value
25                     mask: mask of value
26                     invert: enum InvertVal 0-uninvert 1-invert
27                     value: value
28
29                     reg, rreg, shift, rshift, min, max, mask, invert value
30                 */
31                 ctrlParamsSeqConfig = [
32                    0x10,    0x10,    8,     8,     0x0,    0x1,    0x1,    0,    0,    // rk817 codec enable
33                    0x10,    0x10,    0,     0,     0x0,    0x1,    0x1,    0,    0    // rk809 codec enable
34                 ];
35
36                 controlsConfig = [
37                     /*
38                         "External Codec Enable",
39                         "Internally Codec Enable",
40                     */
41                     /*array index, iface, enable*/
42                     6,  4,  1,
43                     7,  4,  0
44                 ];
45
46                 daiStartupSeqConfig = [
47                     0x00,    0x00,     0,    0,    0,    0xFFFFFFFF,   0xFFFFFFFF,    0,   0x7200000f,   //Transmit Operation Init
48                     0x04,    0x04,     0,    0,    0,    0xFFFFFFFF,   0xFFFFFFFF,    0,   0x01c8000f,   //Receive Operation Init
49                     0x08,    0x08,     0,    0,    0,    0xFFFFFFFF,   0xFFFFFFFF,    0,   0x00001f1f,   //Clock Generation Init
50                     0x10,    0x10,     0,    0,    0,    0xFFFFFFFF,   0xFFFFFFFF,    0,   0x001f0000,   //DMA Control Init
51                     0x14,    0x14,     0,    0,    0,    0xFFFFFFFF,   0xFFFFFFFF,    0,   0x01f00000,   //Interrupt Control Init
52                     0x1C,    0x1C,     0,    0,    0,    0x3,          0x3,           0,            0,   //XFER Init
53                     0x30,    0x30,     0,    0,    0,    0xFFFFFFFF,   0xFFFFFFFF,    0,   0x00003eff,   //TDM Transmit Init
54                     0x34,    0x34,     0,    0,    0,    0xFFFFFFFF,   0xFFFFFFFF,    0,   0x00003eff,   //TDM Receive Init
55                     0x38,    0x38,     0,    0,    0,    0xFFFFFFFF,   0xFFFFFFFF,    0,   0x00000707    //Clock Divider Init
56                 ];
57
58                 daiParamsSeqConfig = [
59                     0x08,    0x08,    8,    8,    0x1F,    0xFF,   0xFF,    0,    0x0,   // I2S_CKR_RSD
60                     0x08,    0x08,    0,    0,    0x1F,    0xFF,   0xFF,    0,    0x0,   // I2S_CKR_TSD
61                     0x38,    0x38,    8,    8,    0x00,    0xFF,   0xFF,    0,    0x0,   // I2S_CLKDIV_RX_MDIV
62                     0x38,    0x38,    0,    0,    0x00,    0xFF,   0xFF,    0,    0x0,   // I2S_CLKDIV_TX_MDIV
63                     0x08,    0x08,    27,   27,   0x0,     0x1,    0x1,     0,    0x0,   // I2S_CKR_MSS
64                     0x08,    0x08,    26,   26,   0x0,     0x1,    0x1,     0,    0x0,   // I2S_CKR_CKP
65                     0x08,    0x08,    25,   25,   0x0,     0x1,    0x1,     0,    0x0,   // I2S_CKR_RLP
66                     0x08,    0x08,    24,   24,   0x0,     0x1,    0x1,     0,    0x0,   // I2S_CKR_TLP
67                 ];
68
69                 daiTriggerSeqConfig = [
70                     0x10,    0x10,    24,   24,   0x0,     0x1,    0x1,     0,    0x1,   // I2S_DMACR_RDE
71                     0x10,    0x10,    8,    8,    0x0,     0x1,    0x1,     0,    0x1,   // I2S_DMACR_TDE
72                     0x14,    0x14,    17,   17,   0x0,     0x1,    0x1,     0,    0x0,   // I2S_INTCR_RXOIE
73                     0x14,    0x14,    16,   16,   0x0,     0x1,    0x1,     0,    0x0,   // I2S_INTCR_RXFIE
74                     0x14,    0x14,    1,    1,    0x0,     0x1,    0x1,     0,    0x0,   // I2S_INTCR_TXUIE
75                     0x14,    0x14,    0,    0,    0x0,     0x1,    0x1,     0,    0x0    // I2S_INTCR_TXEIE
76                 ];
77              }
78        }
79    }
80}
81