Lines Matching +full:mmu +full:- +full:500
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
48 compatible = "arm,armv7-timer";
54 interrupt-parent = <&gic>;
57 gic: interrupt-controller@48211000 {
58 compatible = "arm,cortex-a15-gic";
59 interrupt-controller;
60 #interrupt-cells = <3>;
66 interrupt-parent = <&gic>;
69 wakeupgen: interrupt-controller@48281000 {
70 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
71 interrupt-controller;
72 #interrupt-cells = <3>;
74 interrupt-parent = <&gic>;
78 #address-cells = <1>;
79 #size-cells = <0>;
83 compatible = "arm,cortex-a15";
86 operating-points-v2 = <&cpu0_opp_table>;
89 clock-names = "cpu";
91 clock-latency = <300000>; /* From omap-cpufreq driver */
94 #cooling-cells = <2>; /* min followed by max */
96 vbb-supply = <&abb_mpu>;
100 cpu0_opp_table: opp-table {
101 compatible = "operating-points-v2-ti-cpu";
104 opp_nom-1000000000 {
105 opp-hz = /bits/ 64 <1000000000>;
106 opp-microvolt = <1060000 850000 1150000>,
108 opp-supported-hw = <0xFF 0x01>;
109 opp-suspend;
112 opp_od-1176000000 {
113 opp-hz = /bits/ 64 <1176000000>;
114 opp-microvolt = <1160000 885000 1160000>,
117 opp-supported-hw = <0xFF 0x02>;
121 opp-hz = /bits/ 64 <1500000000>;
122 opp-microvolt = <1210000 950000 1250000>,
124 opp-supported-hw = <0xFF 0x04>;
133 compatible = "ti,omap-infra";
135 compatible = "ti,omap5-mpu";
148 compatible = "ti,dra7-l3-noc", "simple-bus";
149 #address-cells = <1>;
150 #size-cells = <1>;
152 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
156 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
171 compatible = "simple-bus";
172 #size-cells = <1>;
173 #address-cells = <1>;
176 dma-ranges;
183 reg-names = "rc_dbics", "ti_conf", "config";
185 #address-cells = <3>;
186 #size-cells = <2>;
190 bus-range = <0x00 0xff>;
191 #interrupt-cells = <1>;
192 num-lanes = <1>;
193 linux,pci-domain = <0>;
196 phy-names = "pcie-phy0";
197 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
198 interrupt-map-mask = <0 0 0 7>;
199 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
203 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
205 pcie1_intc: interrupt-controller {
206 interrupt-controller;
207 #address-cells = <0>;
208 #interrupt-cells = <1>;
214 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
216 num-lanes = <1>;
217 num-ib-windows = <4>;
218 num-ob-windows = <16>;
221 phy-names = "pcie-phy0";
222 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
223 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
229 compatible = "simple-bus";
230 #size-cells = <1>;
231 #address-cells = <1>;
234 dma-ranges;
238 reg-names = "rc_dbics", "ti_conf", "config";
240 #address-cells = <3>;
241 #size-cells = <2>;
245 bus-range = <0x00 0xff>;
246 #interrupt-cells = <1>;
247 num-lanes = <1>;
248 linux,pci-domain = <1>;
251 phy-names = "pcie-phy0";
252 interrupt-map-mask = <0 0 0 7>;
253 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
257 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
258 pcie2_intc: interrupt-controller {
259 interrupt-controller;
260 #address-cells = <0>;
261 #interrupt-cells = <1>;
267 compatible = "mmio-sram";
270 #address-cells = <1>;
271 #size-cells = <1>;
283 sram-hs@0 {
284 compatible = "ti,secure-ram";
297 compatible = "mmio-sram";
300 #address-cells = <1>;
301 #size-cells = <1>;
306 compatible = "mmio-sram";
309 #address-cells = <1>;
310 #size-cells = <1>;
320 compatible = "ti,dra752-bandgap";
322 #thermal-sensor-cells = <1>;
331 compatible = "ti,dra7-iodelay";
333 #address-cells = <1>;
334 #size-cells = <0>;
335 #pinctrl-cells = <2>;
338 target-module@43300000 {
339 compatible = "ti,sysc-omap4", "ti,sysc";
341 reg-names = "rev";
343 clock-names = "fck";
344 #address-cells = <1>;
345 #size-cells = <1>;
349 compatible = "ti,edma3-tpcc";
351 reg-names = "edma3_cc";
355 interrupt-names = "edma3_ccint", "edma3_mperr",
357 dma-requests = <64>;
358 #dma-cells = <2>;
364 * ti,edma-memcpy-channels = <20 21>;
371 target-module@43400000 {
372 compatible = "ti,sysc-omap4", "ti,sysc";
374 reg-names = "rev";
376 clock-names = "fck";
377 #address-cells = <1>;
378 #size-cells = <1>;
382 compatible = "ti,edma3-tptc";
385 interrupt-names = "edma3_tcerrint";
389 target-module@43500000 {
390 compatible = "ti,sysc-omap4", "ti,sysc";
392 reg-names = "rev";
394 clock-names = "fck";
395 #address-cells = <1>;
396 #size-cells = <1>;
400 compatible = "ti,edma3-tptc";
403 interrupt-names = "edma3_tcerrint";
408 compatible = "ti,omap5-dmm";
415 compatible = "ti,dra7-ipu";
417 reg-names = "l2ram";
422 firmware-name = "dra7-ipu1-fw.xem4";
426 compatible = "ti,dra7-ipu";
428 reg-names = "l2ram";
433 firmware-name = "dra7-ipu2-fw.xem4";
437 compatible = "ti,dra7-dsp";
441 reg-names = "l2ram", "l1pram", "l1dram";
447 firmware-name = "dra7-dsp1-fw.xe66";
450 target-module@40d01000 {
451 compatible = "ti,sysc-omap2", "ti,sysc";
455 reg-names = "rev", "sysc", "syss";
456 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
459 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
463 clock-names = "fck";
465 reset-names = "rstctrl";
467 #size-cells = <1>;
468 #address-cells = <1>;
470 mmu0_dsp1: mmu@0 {
471 compatible = "ti,dra7-dsp-iommu";
474 #iommu-cells = <0>;
475 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
479 target-module@40d02000 {
480 compatible = "ti,sysc-omap2", "ti,sysc";
484 reg-names = "rev", "sysc", "syss";
485 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
488 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
492 clock-names = "fck";
494 reset-names = "rstctrl";
496 #size-cells = <1>;
497 #address-cells = <1>;
499 mmu1_dsp1: mmu@0 {
500 compatible = "ti,dra7-dsp-iommu";
503 #iommu-cells = <0>;
504 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
508 target-module@58882000 {
509 compatible = "ti,sysc-omap2", "ti,sysc";
513 reg-names = "rev", "sysc", "syss";
514 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
517 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
521 clock-names = "fck";
523 reset-names = "rstctrl";
524 #address-cells = <1>;
525 #size-cells = <1>;
528 mmu_ipu1: mmu@0 {
529 compatible = "ti,dra7-iommu";
532 #iommu-cells = <0>;
533 ti,iommu-bus-err-back;
537 target-module@55082000 {
538 compatible = "ti,sysc-omap2", "ti,sysc";
542 reg-names = "rev", "sysc", "syss";
543 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
546 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
550 clock-names = "fck";
552 reset-names = "rstctrl";
553 #address-cells = <1>;
554 #size-cells = <1>;
557 mmu_ipu2: mmu@0 {
558 compatible = "ti,dra7-iommu";
561 #iommu-cells = <0>;
562 ti,iommu-bus-err-back;
566 abb_mpu: regulator-abb-mpu {
567 compatible = "ti,abb-v3";
568 regulator-name = "abb_mpu";
569 #address-cells = <0>;
570 #size-cells = <0>;
572 ti,settling-time = <50>;
573 ti,clock-cycles = <16>;
578 reg-names = "setup-address", "control-address",
579 "int-address", "efuse-address",
580 "ldo-address";
581 ti,tranxdone-status-mask = <0x80>;
583 ti,ldovbb-override-mask = <0x400>;
585 ti,ldovbb-vset-mask = <0x1F>;
599 abb_ivahd: regulator-abb-ivahd {
600 compatible = "ti,abb-v3";
601 regulator-name = "abb_ivahd";
602 #address-cells = <0>;
603 #size-cells = <0>;
605 ti,settling-time = <50>;
606 ti,clock-cycles = <16>;
611 reg-names = "setup-address", "control-address",
612 "int-address", "efuse-address",
613 "ldo-address";
614 ti,tranxdone-status-mask = <0x40000000>;
616 ti,ldovbb-override-mask = <0x400>;
618 ti,ldovbb-vset-mask = <0x1F>;
632 abb_dspeve: regulator-abb-dspeve {
633 compatible = "ti,abb-v3";
634 regulator-name = "abb_dspeve";
635 #address-cells = <0>;
636 #size-cells = <0>;
638 ti,settling-time = <50>;
639 ti,clock-cycles = <16>;
644 reg-names = "setup-address", "control-address",
645 "int-address", "efuse-address",
646 "ldo-address";
647 ti,tranxdone-status-mask = <0x20000000>;
649 ti,ldovbb-override-mask = <0x400>;
651 ti,ldovbb-vset-mask = <0x1F>;
665 abb_gpu: regulator-abb-gpu {
666 compatible = "ti,abb-v3";
667 regulator-name = "abb_gpu";
668 #address-cells = <0>;
669 #size-cells = <0>;
671 ti,settling-time = <50>;
672 ti,clock-cycles = <16>;
677 reg-names = "setup-address", "control-address",
678 "int-address", "efuse-address",
679 "ldo-address";
680 ti,tranxdone-status-mask = <0x10000000>;
682 ti,ldovbb-override-mask = <0x400>;
684 ti,ldovbb-vset-mask = <0x1F>;
699 compatible = "ti,dra7xxx-qspi";
702 reg-names = "qspi_base", "qspi_mmap";
703 syscon-chipselects = <&scm_conf 0x558>;
704 #address-cells = <1>;
705 #size-cells = <0>;
708 clock-names = "fck";
709 num-cs = <4>;
716 compatible = "snps,dwc-ahci";
720 phy-names = "sata-phy";
723 ports-implemented = <0x1>;
729 compatible = "ti,am3352-gpmc";
734 dma-names = "rxtx";
735 gpmc,num-cs = <8>;
736 gpmc,num-waitpins = <2>;
737 #address-cells = <2>;
738 #size-cells = <1>;
739 interrupt-controller;
740 #interrupt-cells = <2>;
741 gpio-controller;
742 #gpio-cells = <2>;
746 target-module@56000000 {
747 compatible = "ti,sysc-omap4", "ti,sysc";
750 reg-names = "rev", "sysc";
751 ti,sysc-midle = <SYSC_IDLE_FORCE>,
754 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
758 clock-names = "fck";
759 #address-cells = <1>;
760 #size-cells = <1>;
765 compatible = "ti,irq-crossbar";
767 interrupt-controller;
768 interrupt-parent = <&wakeupgen>;
769 #interrupt-cells = <3>;
770 ti,max-irqs = <160>;
771 ti,max-crossbar-sources = <MAX_SOURCES>;
772 ti,reg-size = <2>;
773 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
774 ti,irqs-skip = <10 133 139 140>;
775 ti,irqs-safe-map = <0>;
778 target-module@58000000 {
779 compatible = "ti,sysc-omap2", "ti,sysc";
782 reg-names = "rev", "syss";
783 ti,syss-mask = <1>;
788 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
789 #address-cells = <1>;
790 #size-cells = <1>;
794 compatible = "ti,dra7-dss";
799 syscon-pll-ctrl = <&scm_conf 0x538>;
800 #address-cells = <1>;
801 #size-cells = <1>;
804 target-module@1000 {
805 compatible = "ti,sysc-omap2", "ti,sysc";
809 reg-names = "rev", "sysc", "syss";
810 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
813 ti,sysc-midle = <SYSC_IDLE_FORCE>,
816 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
820 ti,syss-mask = <1>;
822 clock-names = "fck";
823 #address-cells = <1>;
824 #size-cells = <1>;
828 compatible = "ti,dra7-dispc";
832 clock-names = "fck";
834 syscon-pol = <&scm_conf 0x534>;
838 target-module@40000 {
839 compatible = "ti,sysc-omap4", "ti,sysc";
842 reg-names = "rev", "sysc";
843 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
847 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
850 clock-names = "fck", "dss_clk";
851 #address-cells = <1>;
852 #size-cells = <1>;
856 compatible = "ti,dra7-hdmi";
861 reg-names = "wp", "pll", "phy", "core";
866 clock-names = "fck", "sys_clk";
868 dma-names = "audio_tx";
874 aes1_target: target-module@4b500000 {
875 compatible = "ti,sysc-omap2", "ti,sysc";
879 reg-names = "rev", "sysc", "syss";
880 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
882 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
886 ti,syss-mask = <1>;
889 clock-names = "fck";
890 #address-cells = <1>;
891 #size-cells = <1>;
895 compatible = "ti,omap4-aes";
899 dma-names = "tx", "rx";
901 clock-names = "fck";
905 aes2_target: target-module@4b700000 {
906 compatible = "ti,sysc-omap2", "ti,sysc";
910 reg-names = "rev", "sysc", "syss";
911 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
913 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
917 ti,syss-mask = <1>;
920 clock-names = "fck";
921 #address-cells = <1>;
922 #size-cells = <1>;
926 compatible = "ti,omap4-aes";
930 dma-names = "tx", "rx";
932 clock-names = "fck";
936 sham_target: target-module@4b101000 {
937 compatible = "ti,sysc-omap3-sham", "ti,sysc";
941 reg-names = "rev", "sysc", "syss";
942 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
944 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
947 ti,syss-mask = <1>;
950 clock-names = "fck";
951 #address-cells = <1>;
952 #size-cells = <1>;
956 compatible = "ti,omap5-sham";
960 dma-names = "rx";
962 clock-names = "fck";
966 opp_supply_mpu: opp-supply@4a003b20 {
967 compatible = "ti,omap5-opp-supply";
969 ti,efuse-settings = <
975 ti,absolute-max-voltage-uv = <1500000>;
980 thermal_zones: thermal-zones {
981 #include "omap4-cpu-thermal.dtsi"
982 #include "omap5-gpu-thermal.dtsi"
983 #include "omap5-core-thermal.dtsi"
984 #include "dra7-dspeve-thermal.dtsi"
985 #include "dra7-iva-thermal.dtsi"
991 polling-delay = <500>; /* milliseconds */
1031 #include "dra7-l4.dtsi"
1032 #include "dra7xx-clocks.dtsi"
1036 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1038 #reset-cells = <1>;
1041 prm_ipu: prm@500 {
1042 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1044 #reset-cells = <1>;
1048 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1050 #reset-cells = <1>;
1054 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1059 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1061 #reset-cells = <1>;
1065 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1070 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1075 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1080 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1085 /* Preferred always-on timer for clockevent */
1087 ti,no-reset-on-init;
1088 ti,no-idle;
1090 assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
1091 assigned-clock-parents = <&sys_32k_ck>;
1097 ti,no-reset-on-init;
1098 ti,no-idle;
1100 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
1101 assigned-clock-parents = <&timer_sys_clk_div>;
1106 ti,no-reset-on-init;
1107 ti,no-idle;
1109 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
1110 assigned-clock-parents = <&timer_sys_clk_div>;