1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Based on "omap4.dtsi" 6 */ 7 8#include <dt-bindings/bus/ti-sysc.h> 9#include <dt-bindings/clock/dra7.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/dra.h> 12#include <dt-bindings/clock/dra7.h> 13 14#define MAX_SOURCES 400 15 16/ { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 compatible = "ti,dra7xx"; 21 interrupt-parent = <&crossbar_mpu>; 22 chosen { }; 23 24 aliases { 25 i2c0 = &i2c1; 26 i2c1 = &i2c2; 27 i2c2 = &i2c3; 28 i2c3 = &i2c4; 29 i2c4 = &i2c5; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 ethernet0 = &cpsw_port1; 41 ethernet1 = &cpsw_port2; 42 d_can0 = &dcan1; 43 d_can1 = &dcan2; 44 spi0 = &qspi; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 status = "disabled"; /* See ARM architected timer wrap erratum i940 */ 50 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 53 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 54 interrupt-parent = <&gic>; 55 }; 56 57 gic: interrupt-controller@48211000 { 58 compatible = "arm,cortex-a15-gic"; 59 interrupt-controller; 60 #interrupt-cells = <3>; 61 reg = <0x0 0x48211000 0x0 0x1000>, 62 <0x0 0x48212000 0x0 0x2000>, 63 <0x0 0x48214000 0x0 0x2000>, 64 <0x0 0x48216000 0x0 0x2000>; 65 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 66 interrupt-parent = <&gic>; 67 }; 68 69 wakeupgen: interrupt-controller@48281000 { 70 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 71 interrupt-controller; 72 #interrupt-cells = <3>; 73 reg = <0x0 0x48281000 0x0 0x1000>; 74 interrupt-parent = <&gic>; 75 }; 76 77 cpus { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a15"; 84 reg = <0>; 85 86 operating-points-v2 = <&cpu0_opp_table>; 87 88 clocks = <&dpll_mpu_ck>; 89 clock-names = "cpu"; 90 91 clock-latency = <300000>; /* From omap-cpufreq driver */ 92 93 /* cooling options */ 94 #cooling-cells = <2>; /* min followed by max */ 95 96 vbb-supply = <&abb_mpu>; 97 }; 98 }; 99 100 cpu0_opp_table: opp-table { 101 compatible = "operating-points-v2-ti-cpu"; 102 syscon = <&scm_wkup>; 103 104 opp_nom-1000000000 { 105 opp-hz = /bits/ 64 <1000000000>; 106 opp-microvolt = <1060000 850000 1150000>, 107 <1060000 850000 1150000>; 108 opp-supported-hw = <0xFF 0x01>; 109 opp-suspend; 110 }; 111 112 opp_od-1176000000 { 113 opp-hz = /bits/ 64 <1176000000>; 114 opp-microvolt = <1160000 885000 1160000>, 115 <1160000 885000 1160000>; 116 117 opp-supported-hw = <0xFF 0x02>; 118 }; 119 120 opp_high@1500000000 { 121 opp-hz = /bits/ 64 <1500000000>; 122 opp-microvolt = <1210000 950000 1250000>, 123 <1210000 950000 1250000>; 124 opp-supported-hw = <0xFF 0x04>; 125 }; 126 }; 127 128 /* 129 * The soc node represents the soc top level view. It is used for IPs 130 * that are not memory mapped in the MPU view or for the MPU itself. 131 */ 132 soc { 133 compatible = "ti,omap-infra"; 134 mpu { 135 compatible = "ti,omap5-mpu"; 136 ti,hwmods = "mpu"; 137 }; 138 }; 139 140 /* 141 * XXX: Use a flat representation of the SOC interconnect. 142 * The real OMAP interconnect network is quite complex. 143 * Since it will not bring real advantage to represent that in DT for 144 * the moment, just use a fake OCP bus entry to represent the whole bus 145 * hierarchy. 146 */ 147 ocp: ocp { 148 compatible = "ti,dra7-l3-noc", "simple-bus"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges = <0x0 0x0 0x0 0xc0000000>; 152 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 153 ti,hwmods = "l3_main_1", "l3_main_2"; 154 reg = <0x0 0x44000000 0x0 0x1000000>, 155 <0x0 0x45000000 0x0 0x1000>; 156 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 157 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 158 159 l4_cfg: interconnect@4a000000 { 160 }; 161 l4_wkup: interconnect@4ae00000 { 162 }; 163 l4_per1: interconnect@48000000 { 164 }; 165 l4_per2: interconnect@48400000 { 166 }; 167 l4_per3: interconnect@48800000 { 168 }; 169 170 axi@0 { 171 compatible = "simple-bus"; 172 #size-cells = <1>; 173 #address-cells = <1>; 174 ranges = <0x51000000 0x51000000 0x3000 175 0x0 0x20000000 0x10000000>; 176 dma-ranges; 177 /** 178 * To enable PCI endpoint mode, disable the pcie1_rc 179 * node and enable pcie1_ep mode. 180 */ 181 pcie1_rc: pcie@51000000 { 182 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 183 reg-names = "rc_dbics", "ti_conf", "config"; 184 interrupts = <0 232 0x4>, <0 233 0x4>; 185 #address-cells = <3>; 186 #size-cells = <2>; 187 device_type = "pci"; 188 ranges = <0x81000000 0 0 0x03000 0 0x00010000 189 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 190 bus-range = <0x00 0xff>; 191 #interrupt-cells = <1>; 192 num-lanes = <1>; 193 linux,pci-domain = <0>; 194 ti,hwmods = "pcie1"; 195 phys = <&pcie1_phy>; 196 phy-names = "pcie-phy0"; 197 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; 198 interrupt-map-mask = <0 0 0 7>; 199 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 200 <0 0 0 2 &pcie1_intc 2>, 201 <0 0 0 3 &pcie1_intc 3>, 202 <0 0 0 4 &pcie1_intc 4>; 203 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 204 status = "disabled"; 205 pcie1_intc: interrupt-controller { 206 interrupt-controller; 207 #address-cells = <0>; 208 #interrupt-cells = <1>; 209 }; 210 }; 211 212 pcie1_ep: pcie_ep@51000000 { 213 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; 214 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; 215 interrupts = <0 232 0x4>; 216 num-lanes = <1>; 217 num-ib-windows = <4>; 218 num-ob-windows = <16>; 219 ti,hwmods = "pcie1"; 220 phys = <&pcie1_phy>; 221 phy-names = "pcie-phy0"; 222 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 223 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; 224 status = "disabled"; 225 }; 226 }; 227 228 axi@1 { 229 compatible = "simple-bus"; 230 #size-cells = <1>; 231 #address-cells = <1>; 232 ranges = <0x51800000 0x51800000 0x3000 233 0x0 0x30000000 0x10000000>; 234 dma-ranges; 235 status = "disabled"; 236 pcie2_rc: pcie@51800000 { 237 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 238 reg-names = "rc_dbics", "ti_conf", "config"; 239 interrupts = <0 355 0x4>, <0 356 0x4>; 240 #address-cells = <3>; 241 #size-cells = <2>; 242 device_type = "pci"; 243 ranges = <0x81000000 0 0 0x03000 0 0x00010000 244 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 245 bus-range = <0x00 0xff>; 246 #interrupt-cells = <1>; 247 num-lanes = <1>; 248 linux,pci-domain = <1>; 249 ti,hwmods = "pcie2"; 250 phys = <&pcie2_phy>; 251 phy-names = "pcie-phy0"; 252 interrupt-map-mask = <0 0 0 7>; 253 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 254 <0 0 0 2 &pcie2_intc 2>, 255 <0 0 0 3 &pcie2_intc 3>, 256 <0 0 0 4 &pcie2_intc 4>; 257 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; 258 pcie2_intc: interrupt-controller { 259 interrupt-controller; 260 #address-cells = <0>; 261 #interrupt-cells = <1>; 262 }; 263 }; 264 }; 265 266 ocmcram1: ocmcram@40300000 { 267 compatible = "mmio-sram"; 268 reg = <0x40300000 0x80000>; 269 ranges = <0x0 0x40300000 0x80000>; 270 #address-cells = <1>; 271 #size-cells = <1>; 272 /* 273 * This is a placeholder for an optional reserved 274 * region for use by secure software. The size 275 * of this region is not known until runtime so it 276 * is set as zero to either be updated to reserve 277 * space or left unchanged to leave all SRAM for use. 278 * On HS parts that that require the reserved region 279 * either the bootloader can update the size to 280 * the required amount or the node can be overridden 281 * from the board dts file for the secure platform. 282 */ 283 sram-hs@0 { 284 compatible = "ti,secure-ram"; 285 reg = <0x0 0x0>; 286 }; 287 }; 288 289 /* 290 * NOTE: ocmcram2 and ocmcram3 are not available on all 291 * DRA7xx and AM57xx variants. Confirm availability in 292 * the data manual for the exact part number in use 293 * before enabling these nodes in the board dts file. 294 */ 295 ocmcram2: ocmcram@40400000 { 296 status = "disabled"; 297 compatible = "mmio-sram"; 298 reg = <0x40400000 0x100000>; 299 ranges = <0x0 0x40400000 0x100000>; 300 #address-cells = <1>; 301 #size-cells = <1>; 302 }; 303 304 ocmcram3: ocmcram@40500000 { 305 status = "disabled"; 306 compatible = "mmio-sram"; 307 reg = <0x40500000 0x100000>; 308 ranges = <0x0 0x40500000 0x100000>; 309 #address-cells = <1>; 310 #size-cells = <1>; 311 }; 312 313 bandgap: bandgap@4a0021e0 { 314 reg = <0x4a0021e0 0xc 315 0x4a00232c 0xc 316 0x4a002380 0x2c 317 0x4a0023C0 0x3c 318 0x4a002564 0x8 319 0x4a002574 0x50>; 320 compatible = "ti,dra752-bandgap"; 321 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 322 #thermal-sensor-cells = <1>; 323 }; 324 325 dsp1_system: dsp_system@40d00000 { 326 compatible = "syscon"; 327 reg = <0x40d00000 0x100>; 328 }; 329 330 dra7_iodelay_core: padconf@4844a000 { 331 compatible = "ti,dra7-iodelay"; 332 reg = <0x4844a000 0x0d1c>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 #pinctrl-cells = <2>; 336 }; 337 338 target-module@43300000 { 339 compatible = "ti,sysc-omap4", "ti,sysc"; 340 reg = <0x43300000 0x4>; 341 reg-names = "rev"; 342 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; 343 clock-names = "fck"; 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges = <0x0 0x43300000 0x100000>; 347 348 edma: dma@0 { 349 compatible = "ti,edma3-tpcc"; 350 reg = <0 0x100000>; 351 reg-names = "edma3_cc"; 352 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-names = "edma3_ccint", "edma3_mperr", 356 "edma3_ccerrint"; 357 dma-requests = <64>; 358 #dma-cells = <2>; 359 360 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; 361 362 /* 363 * memcpy is disabled, can be enabled with: 364 * ti,edma-memcpy-channels = <20 21>; 365 * for example. Note that these channels need to be 366 * masked in the xbar as well. 367 */ 368 }; 369 }; 370 371 target-module@43400000 { 372 compatible = "ti,sysc-omap4", "ti,sysc"; 373 reg = <0x43400000 0x4>; 374 reg-names = "rev"; 375 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; 376 clock-names = "fck"; 377 #address-cells = <1>; 378 #size-cells = <1>; 379 ranges = <0x0 0x43400000 0x100000>; 380 381 edma_tptc0: dma@0 { 382 compatible = "ti,edma3-tptc"; 383 reg = <0 0x100000>; 384 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 385 interrupt-names = "edma3_tcerrint"; 386 }; 387 }; 388 389 target-module@43500000 { 390 compatible = "ti,sysc-omap4", "ti,sysc"; 391 reg = <0x43500000 0x4>; 392 reg-names = "rev"; 393 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; 394 clock-names = "fck"; 395 #address-cells = <1>; 396 #size-cells = <1>; 397 ranges = <0x0 0x43500000 0x100000>; 398 399 edma_tptc1: dma@0 { 400 compatible = "ti,edma3-tptc"; 401 reg = <0 0x100000>; 402 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-names = "edma3_tcerrint"; 404 }; 405 }; 406 407 dmm@4e000000 { 408 compatible = "ti,omap5-dmm"; 409 reg = <0x4e000000 0x800>; 410 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 411 ti,hwmods = "dmm"; 412 }; 413 414 ipu1: ipu@58820000 { 415 compatible = "ti,dra7-ipu"; 416 reg = <0x58820000 0x10000>; 417 reg-names = "l2ram"; 418 iommus = <&mmu_ipu1>; 419 status = "disabled"; 420 resets = <&prm_ipu 0>, <&prm_ipu 1>; 421 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; 422 firmware-name = "dra7-ipu1-fw.xem4"; 423 }; 424 425 ipu2: ipu@55020000 { 426 compatible = "ti,dra7-ipu"; 427 reg = <0x55020000 0x10000>; 428 reg-names = "l2ram"; 429 iommus = <&mmu_ipu2>; 430 status = "disabled"; 431 resets = <&prm_core 0>, <&prm_core 1>; 432 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; 433 firmware-name = "dra7-ipu2-fw.xem4"; 434 }; 435 436 dsp1: dsp@40800000 { 437 compatible = "ti,dra7-dsp"; 438 reg = <0x40800000 0x48000>, 439 <0x40e00000 0x8000>, 440 <0x40f00000 0x8000>; 441 reg-names = "l2ram", "l1pram", "l1dram"; 442 ti,bootreg = <&scm_conf 0x55c 10>; 443 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; 444 status = "disabled"; 445 resets = <&prm_dsp1 0>; 446 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 447 firmware-name = "dra7-dsp1-fw.xe66"; 448 }; 449 450 target-module@40d01000 { 451 compatible = "ti,sysc-omap2", "ti,sysc"; 452 reg = <0x40d01000 0x4>, 453 <0x40d01010 0x4>, 454 <0x40d01014 0x4>; 455 reg-names = "rev", "sysc", "syss"; 456 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 457 <SYSC_IDLE_NO>, 458 <SYSC_IDLE_SMART>; 459 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 460 SYSC_OMAP2_SOFTRESET | 461 SYSC_OMAP2_AUTOIDLE)>; 462 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 463 clock-names = "fck"; 464 resets = <&prm_dsp1 1>; 465 reset-names = "rstctrl"; 466 ranges = <0x0 0x40d01000 0x1000>; 467 #size-cells = <1>; 468 #address-cells = <1>; 469 470 mmu0_dsp1: mmu@0 { 471 compatible = "ti,dra7-dsp-iommu"; 472 reg = <0x0 0x100>; 473 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 474 #iommu-cells = <0>; 475 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 476 }; 477 }; 478 479 target-module@40d02000 { 480 compatible = "ti,sysc-omap2", "ti,sysc"; 481 reg = <0x40d02000 0x4>, 482 <0x40d02010 0x4>, 483 <0x40d02014 0x4>; 484 reg-names = "rev", "sysc", "syss"; 485 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 486 <SYSC_IDLE_NO>, 487 <SYSC_IDLE_SMART>; 488 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 489 SYSC_OMAP2_SOFTRESET | 490 SYSC_OMAP2_AUTOIDLE)>; 491 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 492 clock-names = "fck"; 493 resets = <&prm_dsp1 1>; 494 reset-names = "rstctrl"; 495 ranges = <0x0 0x40d02000 0x1000>; 496 #size-cells = <1>; 497 #address-cells = <1>; 498 499 mmu1_dsp1: mmu@0 { 500 compatible = "ti,dra7-dsp-iommu"; 501 reg = <0x0 0x100>; 502 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 503 #iommu-cells = <0>; 504 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 505 }; 506 }; 507 508 target-module@58882000 { 509 compatible = "ti,sysc-omap2", "ti,sysc"; 510 reg = <0x58882000 0x4>, 511 <0x58882010 0x4>, 512 <0x58882014 0x4>; 513 reg-names = "rev", "sysc", "syss"; 514 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 515 <SYSC_IDLE_NO>, 516 <SYSC_IDLE_SMART>; 517 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 518 SYSC_OMAP2_SOFTRESET | 519 SYSC_OMAP2_AUTOIDLE)>; 520 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; 521 clock-names = "fck"; 522 resets = <&prm_ipu 2>; 523 reset-names = "rstctrl"; 524 #address-cells = <1>; 525 #size-cells = <1>; 526 ranges = <0x0 0x58882000 0x100>; 527 528 mmu_ipu1: mmu@0 { 529 compatible = "ti,dra7-iommu"; 530 reg = <0x0 0x100>; 531 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 532 #iommu-cells = <0>; 533 ti,iommu-bus-err-back; 534 }; 535 }; 536 537 target-module@55082000 { 538 compatible = "ti,sysc-omap2", "ti,sysc"; 539 reg = <0x55082000 0x4>, 540 <0x55082010 0x4>, 541 <0x55082014 0x4>; 542 reg-names = "rev", "sysc", "syss"; 543 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 544 <SYSC_IDLE_NO>, 545 <SYSC_IDLE_SMART>; 546 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 547 SYSC_OMAP2_SOFTRESET | 548 SYSC_OMAP2_AUTOIDLE)>; 549 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; 550 clock-names = "fck"; 551 resets = <&prm_core 2>; 552 reset-names = "rstctrl"; 553 #address-cells = <1>; 554 #size-cells = <1>; 555 ranges = <0x0 0x55082000 0x100>; 556 557 mmu_ipu2: mmu@0 { 558 compatible = "ti,dra7-iommu"; 559 reg = <0x0 0x100>; 560 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 561 #iommu-cells = <0>; 562 ti,iommu-bus-err-back; 563 }; 564 }; 565 566 abb_mpu: regulator-abb-mpu { 567 compatible = "ti,abb-v3"; 568 regulator-name = "abb_mpu"; 569 #address-cells = <0>; 570 #size-cells = <0>; 571 clocks = <&sys_clkin1>; 572 ti,settling-time = <50>; 573 ti,clock-cycles = <16>; 574 575 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 576 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 577 <0x4ae0c158 0x4>; 578 reg-names = "setup-address", "control-address", 579 "int-address", "efuse-address", 580 "ldo-address"; 581 ti,tranxdone-status-mask = <0x80>; 582 /* LDOVBBMPU_FBB_MUX_CTRL */ 583 ti,ldovbb-override-mask = <0x400>; 584 /* LDOVBBMPU_FBB_VSET_OUT */ 585 ti,ldovbb-vset-mask = <0x1F>; 586 587 /* 588 * NOTE: only FBB mode used but actual vset will 589 * determine final biasing 590 */ 591 ti,abb_info = < 592 /*uV ABB efuse rbb_m fbb_m vset_m*/ 593 1060000 0 0x0 0 0x02000000 0x01F00000 594 1160000 0 0x4 0 0x02000000 0x01F00000 595 1210000 0 0x8 0 0x02000000 0x01F00000 596 >; 597 }; 598 599 abb_ivahd: regulator-abb-ivahd { 600 compatible = "ti,abb-v3"; 601 regulator-name = "abb_ivahd"; 602 #address-cells = <0>; 603 #size-cells = <0>; 604 clocks = <&sys_clkin1>; 605 ti,settling-time = <50>; 606 ti,clock-cycles = <16>; 607 608 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 609 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 610 <0x4a002470 0x4>; 611 reg-names = "setup-address", "control-address", 612 "int-address", "efuse-address", 613 "ldo-address"; 614 ti,tranxdone-status-mask = <0x40000000>; 615 /* LDOVBBIVA_FBB_MUX_CTRL */ 616 ti,ldovbb-override-mask = <0x400>; 617 /* LDOVBBIVA_FBB_VSET_OUT */ 618 ti,ldovbb-vset-mask = <0x1F>; 619 620 /* 621 * NOTE: only FBB mode used but actual vset will 622 * determine final biasing 623 */ 624 ti,abb_info = < 625 /*uV ABB efuse rbb_m fbb_m vset_m*/ 626 1055000 0 0x0 0 0x02000000 0x01F00000 627 1150000 0 0x4 0 0x02000000 0x01F00000 628 1250000 0 0x8 0 0x02000000 0x01F00000 629 >; 630 }; 631 632 abb_dspeve: regulator-abb-dspeve { 633 compatible = "ti,abb-v3"; 634 regulator-name = "abb_dspeve"; 635 #address-cells = <0>; 636 #size-cells = <0>; 637 clocks = <&sys_clkin1>; 638 ti,settling-time = <50>; 639 ti,clock-cycles = <16>; 640 641 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 642 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 643 <0x4a00246c 0x4>; 644 reg-names = "setup-address", "control-address", 645 "int-address", "efuse-address", 646 "ldo-address"; 647 ti,tranxdone-status-mask = <0x20000000>; 648 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 649 ti,ldovbb-override-mask = <0x400>; 650 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 651 ti,ldovbb-vset-mask = <0x1F>; 652 653 /* 654 * NOTE: only FBB mode used but actual vset will 655 * determine final biasing 656 */ 657 ti,abb_info = < 658 /*uV ABB efuse rbb_m fbb_m vset_m*/ 659 1055000 0 0x0 0 0x02000000 0x01F00000 660 1150000 0 0x4 0 0x02000000 0x01F00000 661 1250000 0 0x8 0 0x02000000 0x01F00000 662 >; 663 }; 664 665 abb_gpu: regulator-abb-gpu { 666 compatible = "ti,abb-v3"; 667 regulator-name = "abb_gpu"; 668 #address-cells = <0>; 669 #size-cells = <0>; 670 clocks = <&sys_clkin1>; 671 ti,settling-time = <50>; 672 ti,clock-cycles = <16>; 673 674 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 675 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 676 <0x4ae0c154 0x4>; 677 reg-names = "setup-address", "control-address", 678 "int-address", "efuse-address", 679 "ldo-address"; 680 ti,tranxdone-status-mask = <0x10000000>; 681 /* LDOVBBGPU_FBB_MUX_CTRL */ 682 ti,ldovbb-override-mask = <0x400>; 683 /* LDOVBBGPU_FBB_VSET_OUT */ 684 ti,ldovbb-vset-mask = <0x1F>; 685 686 /* 687 * NOTE: only FBB mode used but actual vset will 688 * determine final biasing 689 */ 690 ti,abb_info = < 691 /*uV ABB efuse rbb_m fbb_m vset_m*/ 692 1090000 0 0x0 0 0x02000000 0x01F00000 693 1210000 0 0x4 0 0x02000000 0x01F00000 694 1280000 0 0x8 0 0x02000000 0x01F00000 695 >; 696 }; 697 698 qspi: spi@4b300000 { 699 compatible = "ti,dra7xxx-qspi"; 700 reg = <0x4b300000 0x100>, 701 <0x5c000000 0x4000000>; 702 reg-names = "qspi_base", "qspi_mmap"; 703 syscon-chipselects = <&scm_conf 0x558>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 ti,hwmods = "qspi"; 707 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; 708 clock-names = "fck"; 709 num-cs = <4>; 710 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 711 status = "disabled"; 712 }; 713 714 /* OCP2SCP3 */ 715 sata: sata@4a141100 { 716 compatible = "snps,dwc-ahci"; 717 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 718 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 719 phys = <&sata_phy>; 720 phy-names = "sata-phy"; 721 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; 722 ti,hwmods = "sata"; 723 ports-implemented = <0x1>; 724 }; 725 726 /* OCP2SCP1 */ 727 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 728 gpmc: gpmc@50000000 { 729 compatible = "ti,am3352-gpmc"; 730 ti,hwmods = "gpmc"; 731 reg = <0x50000000 0x37c>; /* device IO registers */ 732 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 733 dmas = <&edma_xbar 4 0>; 734 dma-names = "rxtx"; 735 gpmc,num-cs = <8>; 736 gpmc,num-waitpins = <2>; 737 #address-cells = <2>; 738 #size-cells = <1>; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 gpio-controller; 742 #gpio-cells = <2>; 743 status = "disabled"; 744 }; 745 746 target-module@56000000 { 747 compatible = "ti,sysc-omap4", "ti,sysc"; 748 reg = <0x5600fe00 0x4>, 749 <0x5600fe10 0x4>; 750 reg-names = "rev", "sysc"; 751 ti,sysc-midle = <SYSC_IDLE_FORCE>, 752 <SYSC_IDLE_NO>, 753 <SYSC_IDLE_SMART>; 754 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 755 <SYSC_IDLE_NO>, 756 <SYSC_IDLE_SMART>; 757 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; 758 clock-names = "fck"; 759 #address-cells = <1>; 760 #size-cells = <1>; 761 ranges = <0 0x56000000 0x2000000>; 762 }; 763 764 crossbar_mpu: crossbar@4a002a48 { 765 compatible = "ti,irq-crossbar"; 766 reg = <0x4a002a48 0x130>; 767 interrupt-controller; 768 interrupt-parent = <&wakeupgen>; 769 #interrupt-cells = <3>; 770 ti,max-irqs = <160>; 771 ti,max-crossbar-sources = <MAX_SOURCES>; 772 ti,reg-size = <2>; 773 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 774 ti,irqs-skip = <10 133 139 140>; 775 ti,irqs-safe-map = <0>; 776 }; 777 778 target-module@58000000 { 779 compatible = "ti,sysc-omap2", "ti,sysc"; 780 reg = <0x58000000 4>, 781 <0x58000014 4>; 782 reg-names = "rev", "syss"; 783 ti,syss-mask = <1>; 784 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>, 785 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, 786 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>, 787 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>; 788 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; 789 #address-cells = <1>; 790 #size-cells = <1>; 791 ranges = <0 0x58000000 0x800000>; 792 793 dss: dss@0 { 794 compatible = "ti,dra7-dss"; 795 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 796 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 797 status = "disabled"; 798 /* CTRL_CORE_DSS_PLL_CONTROL */ 799 syscon-pll-ctrl = <&scm_conf 0x538>; 800 #address-cells = <1>; 801 #size-cells = <1>; 802 ranges = <0 0 0x800000>; 803 804 target-module@1000 { 805 compatible = "ti,sysc-omap2", "ti,sysc"; 806 reg = <0x1000 0x4>, 807 <0x1010 0x4>, 808 <0x1014 0x4>; 809 reg-names = "rev", "sysc", "syss"; 810 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 811 <SYSC_IDLE_NO>, 812 <SYSC_IDLE_SMART>; 813 ti,sysc-midle = <SYSC_IDLE_FORCE>, 814 <SYSC_IDLE_NO>, 815 <SYSC_IDLE_SMART>; 816 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 817 SYSC_OMAP2_ENAWAKEUP | 818 SYSC_OMAP2_SOFTRESET | 819 SYSC_OMAP2_AUTOIDLE)>; 820 ti,syss-mask = <1>; 821 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; 822 clock-names = "fck"; 823 #address-cells = <1>; 824 #size-cells = <1>; 825 ranges = <0 0x1000 0x1000>; 826 827 dispc@0 { 828 compatible = "ti,dra7-dispc"; 829 reg = <0 0x1000>; 830 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 832 clock-names = "fck"; 833 /* CTRL_CORE_SMA_SW_1 */ 834 syscon-pol = <&scm_conf 0x534>; 835 }; 836 }; 837 838 target-module@40000 { 839 compatible = "ti,sysc-omap4", "ti,sysc"; 840 reg = <0x40000 0x4>, 841 <0x40010 0x4>; 842 reg-names = "rev", "sysc"; 843 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 844 <SYSC_IDLE_NO>, 845 <SYSC_IDLE_SMART>, 846 <SYSC_IDLE_SMART_WKUP>; 847 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; 848 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, 849 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; 850 clock-names = "fck", "dss_clk"; 851 #address-cells = <1>; 852 #size-cells = <1>; 853 ranges = <0 0x40000 0x40000>; 854 855 hdmi: encoder@0 { 856 compatible = "ti,dra7-hdmi"; 857 reg = <0 0x200>, 858 <0x200 0x80>, 859 <0x300 0x80>, 860 <0x20000 0x19000>; 861 reg-names = "wp", "pll", "phy", "core"; 862 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 863 status = "disabled"; 864 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 865 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; 866 clock-names = "fck", "sys_clk"; 867 dmas = <&sdma_xbar 76>; 868 dma-names = "audio_tx"; 869 }; 870 }; 871 }; 872 }; 873 874 aes1_target: target-module@4b500000 { 875 compatible = "ti,sysc-omap2", "ti,sysc"; 876 reg = <0x4b500080 0x4>, 877 <0x4b500084 0x4>, 878 <0x4b500088 0x4>; 879 reg-names = "rev", "sysc", "syss"; 880 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 881 SYSC_OMAP2_AUTOIDLE)>; 882 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 883 <SYSC_IDLE_NO>, 884 <SYSC_IDLE_SMART>, 885 <SYSC_IDLE_SMART_WKUP>; 886 ti,syss-mask = <1>; 887 /* Domains (P, C): per_pwrdm, l4sec_clkdm */ 888 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>; 889 clock-names = "fck"; 890 #address-cells = <1>; 891 #size-cells = <1>; 892 ranges = <0x0 0x4b500000 0x1000>; 893 894 aes1: aes@0 { 895 compatible = "ti,omap4-aes"; 896 reg = <0 0xa0>; 897 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 898 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; 899 dma-names = "tx", "rx"; 900 clocks = <&l3_iclk_div>; 901 clock-names = "fck"; 902 }; 903 }; 904 905 aes2_target: target-module@4b700000 { 906 compatible = "ti,sysc-omap2", "ti,sysc"; 907 reg = <0x4b700080 0x4>, 908 <0x4b700084 0x4>, 909 <0x4b700088 0x4>; 910 reg-names = "rev", "sysc", "syss"; 911 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 912 SYSC_OMAP2_AUTOIDLE)>; 913 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 914 <SYSC_IDLE_NO>, 915 <SYSC_IDLE_SMART>, 916 <SYSC_IDLE_SMART_WKUP>; 917 ti,syss-mask = <1>; 918 /* Domains (P, C): per_pwrdm, l4sec_clkdm */ 919 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>; 920 clock-names = "fck"; 921 #address-cells = <1>; 922 #size-cells = <1>; 923 ranges = <0x0 0x4b700000 0x1000>; 924 925 aes2: aes@0 { 926 compatible = "ti,omap4-aes"; 927 reg = <0 0xa0>; 928 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 929 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; 930 dma-names = "tx", "rx"; 931 clocks = <&l3_iclk_div>; 932 clock-names = "fck"; 933 }; 934 }; 935 936 sham_target: target-module@4b101000 { 937 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 938 reg = <0x4b101100 0x4>, 939 <0x4b101110 0x4>, 940 <0x4b101114 0x4>; 941 reg-names = "rev", "sysc", "syss"; 942 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 943 SYSC_OMAP2_AUTOIDLE)>; 944 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 945 <SYSC_IDLE_NO>, 946 <SYSC_IDLE_SMART>; 947 ti,syss-mask = <1>; 948 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 949 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; 950 clock-names = "fck"; 951 #address-cells = <1>; 952 #size-cells = <1>; 953 ranges = <0x0 0x4b101000 0x1000>; 954 955 sham: sham@0 { 956 compatible = "ti,omap5-sham"; 957 reg = <0 0x300>; 958 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 959 dmas = <&edma_xbar 119 0>; 960 dma-names = "rx"; 961 clocks = <&l3_iclk_div>; 962 clock-names = "fck"; 963 }; 964 }; 965 966 opp_supply_mpu: opp-supply@4a003b20 { 967 compatible = "ti,omap5-opp-supply"; 968 reg = <0x4a003b20 0xc>; 969 ti,efuse-settings = < 970 /* uV offset */ 971 1060000 0x0 972 1160000 0x4 973 1210000 0x8 974 >; 975 ti,absolute-max-voltage-uv = <1500000>; 976 }; 977 978 }; 979 980 thermal_zones: thermal-zones { 981 #include "omap4-cpu-thermal.dtsi" 982 #include "omap5-gpu-thermal.dtsi" 983 #include "omap5-core-thermal.dtsi" 984 #include "dra7-dspeve-thermal.dtsi" 985 #include "dra7-iva-thermal.dtsi" 986 }; 987 988}; 989 990&cpu_thermal { 991 polling-delay = <500>; /* milliseconds */ 992 coefficients = <0 2000>; 993}; 994 995&gpu_thermal { 996 coefficients = <0 2000>; 997}; 998 999&core_thermal { 1000 coefficients = <0 2000>; 1001}; 1002 1003&dspeve_thermal { 1004 coefficients = <0 2000>; 1005}; 1006 1007&iva_thermal { 1008 coefficients = <0 2000>; 1009}; 1010 1011&cpu_crit { 1012 temperature = <120000>; /* milli Celsius */ 1013}; 1014 1015&core_crit { 1016 temperature = <120000>; /* milli Celsius */ 1017}; 1018 1019&gpu_crit { 1020 temperature = <120000>; /* milli Celsius */ 1021}; 1022 1023&dspeve_crit { 1024 temperature = <120000>; /* milli Celsius */ 1025}; 1026 1027&iva_crit { 1028 temperature = <120000>; /* milli Celsius */ 1029}; 1030 1031#include "dra7-l4.dtsi" 1032#include "dra7xx-clocks.dtsi" 1033 1034&prm { 1035 prm_dsp1: prm@400 { 1036 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1037 reg = <0x400 0x100>; 1038 #reset-cells = <1>; 1039 }; 1040 1041 prm_ipu: prm@500 { 1042 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1043 reg = <0x500 0x100>; 1044 #reset-cells = <1>; 1045 }; 1046 1047 prm_core: prm@700 { 1048 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1049 reg = <0x700 0x100>; 1050 #reset-cells = <1>; 1051 }; 1052 1053 prm_iva: prm@f00 { 1054 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1055 reg = <0xf00 0x100>; 1056 }; 1057 1058 prm_dsp2: prm@1b00 { 1059 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1060 reg = <0x1b00 0x40>; 1061 #reset-cells = <1>; 1062 }; 1063 1064 prm_eve1: prm@1b40 { 1065 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1066 reg = <0x1b40 0x40>; 1067 }; 1068 1069 prm_eve2: prm@1b80 { 1070 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1071 reg = <0x1b80 0x40>; 1072 }; 1073 1074 prm_eve3: prm@1bc0 { 1075 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1076 reg = <0x1bc0 0x40>; 1077 }; 1078 1079 prm_eve4: prm@1c00 { 1080 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1081 reg = <0x1c00 0x60>; 1082 }; 1083}; 1084 1085/* Preferred always-on timer for clockevent */ 1086&timer1_target { 1087 ti,no-reset-on-init; 1088 ti,no-idle; 1089 timer@0 { 1090 assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; 1091 assigned-clock-parents = <&sys_32k_ck>; 1092 }; 1093}; 1094 1095/* Local timers, see ARM architected timer wrap erratum i940 */ 1096&timer15_target { 1097 ti,no-reset-on-init; 1098 ti,no-idle; 1099 timer@0 { 1100 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; 1101 assigned-clock-parents = <&timer_sys_clk_div>; 1102 }; 1103}; 1104 1105&timer16_target { 1106 ti,no-reset-on-init; 1107 ti,no-idle; 1108 timer@0 { 1109 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; 1110 assigned-clock-parents = <&timer_sys_clk_div>; 1111 }; 1112}; 1113