Lines Matching +full:0 +full:x80000
12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
17 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
23 pcie0: pcie@1,0 {
25 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
26 reg = <0x0800 0 0 0 0>;
30 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
31 0x81000000 0 0 0x81000000 0x1 0 1 0>;
32 bus-range = <0x00 0xff>;
33 interrupt-map-mask = <0 0 0 0>;
34 interrupt-map = <0 0 0 0 &intc 9>;
35 marvell,pcie-port = <0>;
36 marvell,pcie-lane = <0>;
41 pcie1: pcie@2,0 {
43 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
44 reg = <0x1000 0 0 0 0>;
48 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
49 0x81000000 0 0 0x81000000 0x2 0 1 0>;
50 bus-range = <0x00 0xff>;
51 interrupt-map-mask = <0 0 0 0>;
52 interrupt-map = <0 0 0 0 &intc 10>;
54 marvell,pcie-lane = <0>;
92 reg = <0x10078 0x4>;
98 reg = <0x10300 0x20>;
105 reg = <0x11100 0x20>;
107 #size-cells = <0>;
111 pinctrl-0 = <&pmx_twsi1>;
118 reg = <0x80000 0x5000>;
121 clock-names = "0", "1";
129 reg = <0x90000 0x200>;
132 pinctrl-0 = <&pmx_sdio>;