1// SPDX-License-Identifier: GPL-2.0 2/ { 3 mbus@f1000000 { 4 pciec: pcie@82000000 { 5 compatible = "marvell,kirkwood-pcie"; 6 status = "disabled"; 7 device_type = "pci"; 8 9 #address-cells = <3>; 10 #size-cells = <2>; 11 12 bus-range = <0x00 0xff>; 13 14 ranges = 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 17 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; 22 23 pcie0: pcie@1,0 { 24 device_type = "pci"; 25 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 26 reg = <0x0800 0 0 0 0>; 27 #address-cells = <3>; 28 #size-cells = <2>; 29 #interrupt-cells = <1>; 30 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 31 0x81000000 0 0 0x81000000 0x1 0 1 0>; 32 bus-range = <0x00 0xff>; 33 interrupt-map-mask = <0 0 0 0>; 34 interrupt-map = <0 0 0 0 &intc 9>; 35 marvell,pcie-port = <0>; 36 marvell,pcie-lane = <0>; 37 clocks = <&gate_clk 2>; 38 status = "disabled"; 39 }; 40 41 pcie1: pcie@2,0 { 42 device_type = "pci"; 43 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; 44 reg = <0x1000 0 0 0 0>; 45 #address-cells = <3>; 46 #size-cells = <2>; 47 #interrupt-cells = <1>; 48 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 49 0x81000000 0 0 0x81000000 0x2 0 1 0>; 50 bus-range = <0x00 0xff>; 51 interrupt-map-mask = <0 0 0 0>; 52 interrupt-map = <0 0 0 0 &intc 10>; 53 marvell,pcie-port = <1>; 54 marvell,pcie-lane = <0>; 55 clocks = <&gate_clk 18>; 56 status = "disabled"; 57 }; 58 }; 59 }; 60 ocp@f1000000 { 61 62 pinctrl: pin-controller@10000 { 63 compatible = "marvell,88f6282-pinctrl"; 64 65 pmx_sata0: pmx-sata0 { 66 marvell,pins = "mpp5", "mpp21", "mpp23"; 67 marvell,function = "sata0"; 68 }; 69 pmx_sata1: pmx-sata1 { 70 marvell,pins = "mpp4", "mpp20", "mpp22"; 71 marvell,function = "sata1"; 72 }; 73 74 /* 75 * Default I2C1 pinctrl setting on mpp36/mpp37, 76 * overwrite marvell,pins on board level if required. 77 */ 78 pmx_twsi1: pmx-twsi1 { 79 marvell,pins = "mpp36", "mpp37"; 80 marvell,function = "twsi1"; 81 }; 82 83 pmx_sdio: pmx-sdio { 84 marvell,pins = "mpp12", "mpp13", "mpp14", 85 "mpp15", "mpp16", "mpp17"; 86 marvell,function = "sdio"; 87 }; 88 }; 89 90 thermal: thermal@10078 { 91 compatible = "marvell,kirkwood-thermal"; 92 reg = <0x10078 0x4>; 93 status = "okay"; 94 }; 95 96 rtc: rtc@10300 { 97 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; 98 reg = <0x10300 0x20>; 99 interrupts = <53>; 100 clocks = <&gate_clk 7>; 101 }; 102 103 i2c1: i2c@11100 { 104 compatible = "marvell,mv64xxx-i2c"; 105 reg = <0x11100 0x20>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 interrupts = <32>; 109 clock-frequency = <100000>; 110 clocks = <&gate_clk 7>; 111 pinctrl-0 = <&pmx_twsi1>; 112 pinctrl-names = "default"; 113 status = "disabled"; 114 }; 115 116 sata: sata@80000 { 117 compatible = "marvell,orion-sata"; 118 reg = <0x80000 0x5000>; 119 interrupts = <21>; 120 clocks = <&gate_clk 14>, <&gate_clk 15>; 121 clock-names = "0", "1"; 122 phys = <&sata_phy0>, <&sata_phy1>; 123 phy-names = "port0", "port1"; 124 status = "disabled"; 125 }; 126 127 sdio: mvsdio@90000 { 128 compatible = "marvell,orion-sdio"; 129 reg = <0x90000 0x200>; 130 interrupts = <28>; 131 clocks = <&gate_clk 4>; 132 pinctrl-0 = <&pmx_sdio>; 133 pinctrl-names = "default"; 134 bus-width = <4>; 135 cap-sdio-irq; 136 cap-sd-highspeed; 137 cap-mmc-highspeed; 138 status = "disabled"; 139 }; 140 }; 141}; 142