Searched +full:- +full:clint (Results 1 – 7 of 7) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Palmer Dabbelt <palmer@dabbelt.com>11 - Anup Patel <anup.patel@wdc.com>14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor16 interrupts. It directly connects to the timer and inter-processor interrupt17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a6 * CLINT MMIO timer device.9 #define pr_fmt(fmt) "clint: " fmt18 #include <linux/io-64-nonatomic-lo-hi.h>25 #include <asm/clint.h>32 /* CLINT manages IPI and Timer for RISC-V M-mode */123 ce->cpumask = cpumask_of(cpu); in clint_timer_starting_cpu()142 evdev->event_handler(evdev); in clint_timer_interrupt()155 * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or in clint_timer_init_dt()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only165 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,188 32-bit free running decrementing counters.242 bool "Integrator-AP timer driver" if COMPILE_TEST245 Enables support for the Integrator-AP timer.278 available on many OMAP-like platforms.287 It has a 64-bit counter with update rate up to 1000MHz.288 This counter is accessed via couple of 32-bit memory-mapped registers.307 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST311 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_TIMER_OF) += timer-of.o3 obj-$(CONFIG_TIMER_PROBE) += timer-probe.o4 obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o5 obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o6 obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o7 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o8 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o9 obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o10 obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */14 * This lives in the CLINT driver, but is accessed directly by timex.h to avoid17 * The ISA defines mtime as a 64-bit memory-mapped register that increments at21 * like "riscv_mtime", to signify that these non-ISA assumptions must hold.
1 /* SPDX-License-Identifier: GPL-2.0-only */15 #include <asm/clint.h>
1 // SPDX-License-Identifier: GPL-2.0+6 #include <dt-bindings/clock/k210-clk.h>10 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits13 #address-cells = <1>;14 #size-cells = <1>;23 * Since this is a non-ratified draft specification, the kernel does not28 #address-cells = <1>;29 #size-cells = <0>;30 timebase-frequency = <7800000>;36 mmu-type = "none";[all …]