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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-am654.yaml75 ti,otap-del-sel-sdr25:
76 description: Output tap delay for SD UHS SDR25 timing
145 ti,itap-del-sel-sdr25:
146 description: Input tap delay for SD UHS SDR25 timing
Dcdns,sdhci.yaml55 cdns,phy-input-delay-sd-uhs-sdr25:
56 description: Value of the delay in the input path for SD UHS SDR25 timing
Dsdhci-omap.txt14 - pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50",
Dsocionext,uniphier-sd.yaml99 sd-uhs-sdr25;
Dk3-dw-mshc.txt60 sd-uhs-sdr25;
Dmmc-controller.yaml136 sd-uhs-sdr25:
139 SD UHS SDR25 speed is supported.
Dmarvell,xenon-sdhci.txt84 always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a-clearfog-itx.dtsi30 sd-uhs-sdr25;
Dfsl-ls1012a-rdb.dts24 sd-uhs-sdr25;
Dfsl-lx2160a-rdb.dts69 sd-uhs-sdr25;
Dfsl-ls1046a-rdb.dts42 sd-uhs-sdr25;
Dfsl-ls1028a-rdb.dts89 sd-uhs-sdr25;
Dfsl-ls1028a-kontron-sl28.dts96 sd-uhs-sdr25;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx6qdl-colibri-v1_1-uhs.dtsi41 sd-uhs-sdr25;
Drk3288-veyron-sdmmc.dtsi84 sd-uhs-sdr25;
Ddra7-evm.dts389 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
420 …mes = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
Ddra72-evm.dts94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
Dimx6ull-colibri-eval-v3.dtsi174 sd-uhs-sdr25;
Ddra72-evm-revc.dts124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
Dam335x-shc.dts224 sd-uhs-sdr25;
235 sd-uhs-sdr25;
Drk3288-phycore-rdk.dts232 sd-uhs-sdr25;
/kernel/linux/linux-5.10/drivers/mmc/host/
Ddw_mmc-k3.c81 {6, 0, 2, 2,}, /* 4: SDR25 */
93 {6, 0, 0, 0,}, /* 4: SDR25 */
Dsdhci-acpi.c669 * a) The clock divisor for SDR12, SDR25, and SDR50 is too small. in sdhci_acpi_emmc_amd_probe_slot()
671 * acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 = in sdhci_acpi_emmc_amd_probe_slot()
682 * SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and in sdhci_acpi_emmc_amd_probe_slot()
/kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3308-roc-cc.dts175 sd-uhs-sdr25;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-p20x.dtsi197 sd-uhs-sdr25;

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