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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun4i-a10-ccu.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
22 - allwinner,sun4i-a10-ccu
23 - allwinner,sun5i-a10s-ccu
24 - allwinner,sun5i-a13-ccu
25 - allwinner,sun6i-a31-ccu
26 - allwinner,sun7i-a20-ccu
27 - allwinner,sun8i-a23-ccu
28 - allwinner,sun8i-a33-ccu
29 - allwinner,sun8i-a83t-ccu
30 - allwinner,sun8i-a83t-r-ccu
[all …]
Dbaikal,bt1-ccu-div.yaml5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
15 responsible for the chip subsystems clocking and resetting. The CCU is
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
24 in general can provide any frequency supported by the CCU PLLs).
32 | Baikal-T1 CCU |
50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
51 then passed over CCU dividers to create signals required for the target clock
66 where CLKIN is the reference clock coming either from CCU PLLs or from an
77 devices, are united into a single clocks provider called System Devices CCU.
[all …]
Dbrcm,kona-ccu.txt4 clock control units (CCUs). A CCU is a clock provider that manages
5 a set of clock signals. Each CCU is represented by a node in the
13 Shall have a value of the form "brcm,<model>-<which>-ccu",
15 the name of a defined CCU. For example:
16 "brcm,bcm11351-root-ccu"
27 the clocks provided by the CCU.
32 compatible = "brcm,bcm11351-slave-ccu";
58 CCU compatible string values for SoCs in the BCM281XX family are:
59 "brcm,bcm11351-root-ccu"
60 "brcm,bcm11351-aon-ccu"
[all …]
Dlpc1850-ccu.txt1 * NXP LPC1850 Clock Control Unit (CCU)
14 Should be "nxp,lpc1850-ccu"
23 from the CGU to the specific CCU. See mapping of base clocks
24 and CCU in table below.
27 from the CGU to the specific CCU. Valid CCU clock names:
35 Which branch clocks that are available on the CCU depends on the
38 A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
44 compatible = "nxp,lpc1850-ccu";
58 compatible = "nxp,lpc1850-ccu";
71 /* A user of CCU brach clocks */
/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-kona.c24 * CCU. (I believe these polices are named "Deep Sleep", "Economy",
127 /* CCU access */
129 /* Read a 32-bit register value from a CCU's address space. */
130 static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset) in __ccu_read() argument
132 return readl(ccu->base + reg_offset); in __ccu_read()
135 /* Write a 32-bit register value into a CCU's address space. */
137 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
139 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
142 static inline unsigned long ccu_lock(struct ccu_data *ccu) in ccu_lock() argument
146 spin_lock_irqsave(&ccu->lock, flags); in ccu_lock()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsunxi-h3-h5.dtsi44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
45 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
49 #include <dt-bindings/reset/sun8i-r-ccu.h>
66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
75 <&ccu CLK_TVE>;
118 clocks = <&ccu CLK_BUS_DE>,
119 <&ccu CLK_DE>;
122 resets = <&ccu RST_BUS_DE>;
154 clocks = <&ccu CLK_BUS_DMA>;
[all …]
Dsun6i-a31.dtsi48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
106 clocks = <&ccu CLK_CPU>;
[all …]
Dsun4i-a10.dtsi46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
[all …]
Dsun8i-r40.dtsi46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
140 clocks = <&ccu CLK_BUS_DE>,
141 <&ccu CLK_DE>;
144 resets = <&ccu RST_BUS_DE>;
229 clocks = <&ccu CLK_BUS_DMA>;
232 resets = <&ccu RST_BUS_DMA>;
241 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
243 resets = <&ccu RST_BUS_SPI0>;
254 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
[all …]
Dsun8i-v3s.dtsi44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
63 <&ccu CLK_TCON0>;
76 clocks = <&ccu CLK_CPU>;
125 clocks = <&ccu CLK_BUS_DE>,
126 <&ccu CLK_DE>;
129 resets = <&ccu RST_BUS_DE>;
170 clocks = <&ccu CLK_BUS_TCON0>,
171 <&ccu CLK_TCON0>;
176 resets = <&ccu RST_BUS_TCON0>;
[all …]
Dsun5i.dtsi45 #include <dt-bindings/clock/sun5i-ccu.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
62 clocks = <&ccu CLK_CPU>;
75 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
76 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
84 clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
85 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
86 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
188 clocks = <&ccu CLK_MBUS>;
199 clocks = <&ccu CLK_AHB_DMA>;
[all …]
Dsun7i-a20.dtsi48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
70 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
71 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
72 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
73 <&ccu CLK_HDMI>;
81 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
82 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
83 <&ccu CLK_DRAM_DE_BE0>;
91 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
[all …]
Dsun8i-a23-a33.dtsi47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
159 clocks = <&ccu CLK_BUS_DMA>;
160 resets = <&ccu RST_BUS_DMA>;
168 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
170 resets = <&ccu RST_BUS_NAND>;
186 clocks = <&ccu CLK_BUS_LCD>,
[all …]
Dsun8i-h3.dtsi78 clocks = <&ccu CLK_CPUX>;
88 clocks = <&ccu CLK_CPUX>;
98 clocks = <&ccu CLK_CPUX>;
108 clocks = <&ccu CLK_CPUX>;
156 clocks = <&ccu CLK_BUS_DEINTERLACE>,
157 <&ccu CLK_DEINTERLACE>,
158 <&ccu CLK_DRAM_DEINTERLACE>;
160 resets = <&ccu RST_BUS_DEINTERLACE>;
191 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
192 <&ccu CLK_DRAM_VE>;
[all …]
Dsun8i-a83t.dtsi47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
67 clocks = <&ccu CLK_C0CPUX>;
78 clocks = <&ccu CLK_C0CPUX>;
89 clocks = <&ccu CLK_C0CPUX>;
100 clocks = <&ccu CLK_C0CPUX>;
111 clocks = <&ccu CLK_C1CPUX>;
122 clocks = <&ccu CLK_C1CPUX>;
[all …]
Dsun8i-a33.dtsi128 clocks = <&ccu CLK_CPUX>;
135 clocks = <&ccu CLK_CPUX>;
145 clocks = <&ccu CLK_CPUX>;
155 clocks = <&ccu CLK_CPUX>;
209 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
210 <&ccu CLK_DRAM_VE>;
212 resets = <&ccu RST_BUS_VE>;
221 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
223 resets = <&ccu RST_BUS_SS>;
232 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h6.dtsi5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
28 clocks = <&ccu CLK_CPUX>;
38 clocks = <&ccu CLK_CPUX>;
48 clocks = <&ccu CLK_CPUX>;
58 clocks = <&ccu CLK_CPUX>;
122 clocks = <&ccu CLK_DE>,
123 <&ccu CLK_BUS_DE>;
[all …]
Dsun50i-a64.dtsi6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
29 clocks = <&ccu CLK_TCON0>,
39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
54 clocks = <&ccu CLK_CPUX>;
65 clocks = <&ccu CLK_CPUX>;
76 clocks = <&ccu CLK_CPUX>;
87 clocks = <&ccu CLK_CPUX>;
[all …]
Dsun50i-h5.dtsi18 clocks = <&ccu CLK_CPUX>;
28 clocks = <&ccu CLK_CPUX>;
38 clocks = <&ccu CLK_CPUX>;
48 clocks = <&ccu CLK_CPUX>;
107 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
108 <&ccu CLK_DRAM_VE>;
110 resets = <&ccu RST_BUS_VE>;
119 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
121 resets = <&ccu RST_BUS_CE>;
155 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
[all …]
Dsun50i-a100.dtsi7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
95 ccu: clock@3001000 { label
96 compatible = "allwinner,sun50i-a100-ccu";
136 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
155 clocks = <&ccu CLK_BUS_UART0>;
156 resets = <&ccu RST_BUS_UART0>;
166 clocks = <&ccu CLK_BUS_UART1>;
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
DMakefile24 obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
25 obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
26 obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
27 obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
28 obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
29 obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
30 obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
31 obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
32 obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
33 obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
[all …]
DKconfig11 bool "Support for the Allwinner newer F1C100s CCU"
16 bool "Support for the Allwinner A64 CCU"
21 bool "Support for the Allwinner A100 CCU"
26 bool "Support for the Allwinner A100 PRCM CCU"
31 bool "Support for the Allwinner H6 CCU"
36 bool "Support for the Allwinner H6 PRCM CCU"
41 bool "Support for the Allwinner A10/A20 CCU"
52 bool "Support for the Allwinner A31/A31s CCU"
57 bool "Support for the Allwinner A23 CCU"
62 bool "Support for the Allwinner A33 CCU"
[all …]
Dccu_reset.c16 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_assert() local
17 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_assert()
21 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_assert()
23 reg = readl(ccu->base + map->reg); in ccu_reset_assert()
24 writel(reg & ~map->bit, ccu->base + map->reg); in ccu_reset_assert()
26 spin_unlock_irqrestore(ccu->lock, flags); in ccu_reset_assert()
34 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_deassert() local
35 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_deassert()
39 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_deassert()
41 reg = readl(ccu->base + map->reg); in ccu_reset_deassert()
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dbcm281xx.h24 * These are the bcm281xx CCU device tree "compatible" strings.
29 #define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
30 #define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
31 #define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
32 #define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
33 #define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
35 /* root CCU clock ids */
40 /* aon CCU clock ids */
47 /* hub CCU clock ids */
52 /* master CCU clock ids */
[all …]
/kernel/linux/linux-5.10/drivers/clk/baikal-t1/
Dccu-div.h5 * Baikal-T1 CCU Dividers interface driver
17 * CCU Divider private clock IDs
18 * @CCU_SYS_SATA_CLK: CCU SATA internal clock
19 * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
25 * CCU Divider private flags
39 * enum ccu_div_type - CCU Divider types
53 * struct ccu_div_init_data - CCU Divider initialization data
59 * @np: Pointer to the node describing the CCU Dividers.
60 * @type: CCU divider type (variable, fixed with and without gate).
63 * @flags: CCU Divider clock flags.
[all …]

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