1/* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46 47#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> 48#include <dt-bindings/reset/sun8i-a23-a33-ccu.h> 49 50/ { 51 interrupt-parent = <&gic>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 chosen { 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges; 59 60 simplefb_lcd: framebuffer-lcd0 { 61 compatible = "allwinner,simple-framebuffer", 62 "simple-framebuffer"; 63 allwinner,pipeline = "de_be0-lcd0"; 64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, 65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, 66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; 67 status = "disabled"; 68 }; 69 }; 70 71 de: display-engine { 72 /* compatible gets set in SoC specific dtsi file */ 73 allwinner,pipelines = <&fe0>; 74 status = "disabled"; 75 }; 76 77 timer { 78 compatible = "arm,armv7-timer"; 79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 80 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 82 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 83 clock-frequency = <24000000>; 84 arm,cpu-registers-not-fw-configured; 85 }; 86 87 cpus { 88 enable-method = "allwinner,sun8i-a23"; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 92 cpu0: cpu@0 { 93 compatible = "arm,cortex-a7"; 94 device_type = "cpu"; 95 reg = <0>; 96 }; 97 98 cpu@1 { 99 compatible = "arm,cortex-a7"; 100 device_type = "cpu"; 101 reg = <1>; 102 }; 103 }; 104 105 clocks { 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 osc24M: osc24M_clk { 111 #clock-cells = <0>; 112 compatible = "fixed-clock"; 113 clock-frequency = <24000000>; 114 clock-accuracy = <50000>; 115 clock-output-names = "osc24M"; 116 }; 117 118 ext_osc32k: ext_osc32k_clk { 119 #clock-cells = <0>; 120 compatible = "fixed-clock"; 121 clock-frequency = <32768>; 122 clock-accuracy = <50000>; 123 clock-output-names = "ext-osc32k"; 124 }; 125 }; 126 127 soc { 128 compatible = "simple-bus"; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 system-control@1c00000 { 134 compatible = "allwinner,sun8i-a23-system-control"; 135 reg = <0x01c00000 0x30>; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 ranges; 139 140 sram_c: sram@1d00000 { 141 compatible = "mmio-sram"; 142 reg = <0x01d00000 0x80000>; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges = <0 0x01d00000 0x80000>; 146 147 ve_sram: sram-section@0 { 148 compatible = "allwinner,sun8i-a23-sram-c1", 149 "allwinner,sun4i-a10-sram-c1"; 150 reg = <0x000000 0x80000>; 151 }; 152 }; 153 }; 154 155 dma: dma-controller@1c02000 { 156 compatible = "allwinner,sun8i-a23-dma"; 157 reg = <0x01c02000 0x1000>; 158 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&ccu CLK_BUS_DMA>; 160 resets = <&ccu RST_BUS_DMA>; 161 #dma-cells = <1>; 162 }; 163 164 nfc: nand-controller@1c03000 { 165 compatible = "allwinner,sun8i-a23-nand-controller"; 166 reg = <0x01c03000 0x1000>; 167 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; 169 clock-names = "ahb", "mod"; 170 resets = <&ccu RST_BUS_NAND>; 171 reset-names = "ahb"; 172 dmas = <&dma 5>; 173 dma-names = "rxtx"; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; 176 status = "disabled"; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 }; 180 181 tcon0: lcd-controller@1c0c000 { 182 /* compatible gets set in SoC specific dtsi file */ 183 reg = <0x01c0c000 0x1000>; 184 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 185 dmas = <&dma 12>; 186 clocks = <&ccu CLK_BUS_LCD>, 187 <&ccu CLK_LCD_CH0>, 188 <&ccu 13>; 189 clock-names = "ahb", 190 "tcon-ch0", 191 "lvds-alt"; 192 clock-output-names = "tcon-pixel-clock"; 193 #clock-cells = <0>; 194 resets = <&ccu RST_BUS_LCD>, 195 <&ccu RST_BUS_LVDS>; 196 reset-names = "lcd", 197 "lvds"; 198 status = "disabled"; 199 200 ports { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 204 tcon0_in: port@0 { 205 reg = <0>; 206 207 tcon0_in_drc0: endpoint { 208 remote-endpoint = <&drc0_out_tcon0>; 209 }; 210 }; 211 212 tcon0_out: port@1 { 213 reg = <1>; 214 }; 215 }; 216 }; 217 218 mmc0: mmc@1c0f000 { 219 compatible = "allwinner,sun7i-a20-mmc"; 220 reg = <0x01c0f000 0x1000>; 221 clocks = <&ccu CLK_BUS_MMC0>, 222 <&ccu CLK_MMC0>, 223 <&ccu CLK_MMC0_OUTPUT>, 224 <&ccu CLK_MMC0_SAMPLE>; 225 clock-names = "ahb", 226 "mmc", 227 "output", 228 "sample"; 229 resets = <&ccu RST_BUS_MMC0>; 230 reset-names = "ahb"; 231 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&mmc0_pins>; 234 status = "disabled"; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 }; 238 239 mmc1: mmc@1c10000 { 240 compatible = "allwinner,sun7i-a20-mmc"; 241 reg = <0x01c10000 0x1000>; 242 clocks = <&ccu CLK_BUS_MMC1>, 243 <&ccu CLK_MMC1>, 244 <&ccu CLK_MMC1_OUTPUT>, 245 <&ccu CLK_MMC1_SAMPLE>; 246 clock-names = "ahb", 247 "mmc", 248 "output", 249 "sample"; 250 resets = <&ccu RST_BUS_MMC1>; 251 reset-names = "ahb"; 252 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 253 status = "disabled"; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 }; 257 258 mmc2: mmc@1c11000 { 259 compatible = "allwinner,sun7i-a20-mmc"; 260 reg = <0x01c11000 0x1000>; 261 clocks = <&ccu CLK_BUS_MMC2>, 262 <&ccu CLK_MMC2>, 263 <&ccu CLK_MMC2_OUTPUT>, 264 <&ccu CLK_MMC2_SAMPLE>; 265 clock-names = "ahb", 266 "mmc", 267 "output", 268 "sample"; 269 resets = <&ccu RST_BUS_MMC2>; 270 reset-names = "ahb"; 271 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 272 status = "disabled"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 277 usb_otg: usb@1c19000 { 278 /* compatible gets set in SoC specific dtsi file */ 279 reg = <0x01c19000 0x0400>; 280 clocks = <&ccu CLK_BUS_OTG>; 281 resets = <&ccu RST_BUS_OTG>; 282 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-names = "mc"; 284 phys = <&usbphy 0>; 285 phy-names = "usb"; 286 extcon = <&usbphy 0>; 287 dr_mode = "otg"; 288 status = "disabled"; 289 }; 290 291 usbphy: phy@1c19400 { 292 /* 293 * compatible and address regions get set in 294 * SoC specific dtsi file 295 */ 296 clocks = <&ccu CLK_USB_PHY0>, 297 <&ccu CLK_USB_PHY1>; 298 clock-names = "usb0_phy", 299 "usb1_phy"; 300 resets = <&ccu RST_USB_PHY0>, 301 <&ccu RST_USB_PHY1>; 302 reset-names = "usb0_reset", 303 "usb1_reset"; 304 status = "disabled"; 305 #phy-cells = <1>; 306 }; 307 308 ehci0: usb@1c1a000 { 309 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; 310 reg = <0x01c1a000 0x100>; 311 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&ccu CLK_BUS_EHCI>; 313 resets = <&ccu RST_BUS_EHCI>; 314 phys = <&usbphy 1>; 315 phy-names = "usb"; 316 status = "disabled"; 317 }; 318 319 ohci0: usb@1c1a400 { 320 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; 321 reg = <0x01c1a400 0x100>; 322 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; 324 resets = <&ccu RST_BUS_OHCI>; 325 phys = <&usbphy 1>; 326 phy-names = "usb"; 327 status = "disabled"; 328 }; 329 330 ccu: clock@1c20000 { 331 reg = <0x01c20000 0x400>; 332 clocks = <&osc24M>, <&rtc 0>; 333 clock-names = "hosc", "losc"; 334 #clock-cells = <1>; 335 #reset-cells = <1>; 336 }; 337 338 pio: pinctrl@1c20800 { 339 /* compatible gets set in SoC specific dtsi file */ 340 reg = <0x01c20800 0x400>; 341 /* interrupts get set in SoC specific dtsi file */ 342 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 343 clock-names = "apb", "hosc", "losc"; 344 gpio-controller; 345 interrupt-controller; 346 #interrupt-cells = <3>; 347 #gpio-cells = <3>; 348 349 i2c0_pins: i2c0-pins { 350 pins = "PH2", "PH3"; 351 function = "i2c0"; 352 }; 353 354 i2c1_pins: i2c1-pins { 355 pins = "PH4", "PH5"; 356 function = "i2c1"; 357 }; 358 359 i2c2_pins: i2c2-pins { 360 pins = "PE12", "PE13"; 361 function = "i2c2"; 362 }; 363 364 lcd_rgb666_pins: lcd-rgb666-pins { 365 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 366 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 367 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", 368 "PD24", "PD25", "PD26", "PD27"; 369 function = "lcd0"; 370 }; 371 372 mmc0_pins: mmc0-pins { 373 pins = "PF0", "PF1", "PF2", 374 "PF3", "PF4", "PF5"; 375 function = "mmc0"; 376 drive-strength = <30>; 377 bias-pull-up; 378 }; 379 380 mmc1_pg_pins: mmc1-pg-pins { 381 pins = "PG0", "PG1", "PG2", 382 "PG3", "PG4", "PG5"; 383 function = "mmc1"; 384 drive-strength = <30>; 385 bias-pull-up; 386 }; 387 388 mmc2_8bit_pins: mmc2-8bit-pins { 389 pins = "PC5", "PC6", "PC8", 390 "PC9", "PC10", "PC11", 391 "PC12", "PC13", "PC14", 392 "PC15", "PC16"; 393 function = "mmc2"; 394 drive-strength = <30>; 395 bias-pull-up; 396 }; 397 398 nand_pins: nand-pins { 399 pins = "PC0", "PC1", "PC2", "PC5", 400 "PC8", "PC9", "PC10", "PC11", 401 "PC12", "PC13", "PC14", "PC15"; 402 function = "nand0"; 403 }; 404 405 nand_cs0_pin: nand-cs0-pin { 406 pins = "PC4"; 407 function = "nand0"; 408 bias-pull-up; 409 }; 410 411 nand_cs1_pin: nand-cs1-pin { 412 pins = "PC3"; 413 function = "nand0"; 414 bias-pull-up; 415 }; 416 417 nand_rb0_pin: nand-rb0-pin { 418 pins = "PC6"; 419 function = "nand0"; 420 bias-pull-up; 421 }; 422 423 nand_rb1_pin: nand-rb1-pin { 424 pins = "PC7"; 425 function = "nand0"; 426 bias-pull-up; 427 }; 428 429 pwm0_pin: pwm0-pin { 430 pins = "PH0"; 431 function = "pwm0"; 432 }; 433 434 uart0_pf_pins: uart0-pf-pins { 435 pins = "PF2", "PF4"; 436 function = "uart0"; 437 }; 438 439 uart1_pg_pins: uart1-pg-pins { 440 pins = "PG6", "PG7"; 441 function = "uart1"; 442 }; 443 444 uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins { 445 pins = "PG8", "PG9"; 446 function = "uart1"; 447 }; 448 }; 449 450 timer@1c20c00 { 451 compatible = "allwinner,sun8i-a23-timer"; 452 reg = <0x01c20c00 0xa0>; 453 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&osc24M>; 456 }; 457 458 wdt0: watchdog@1c20ca0 { 459 compatible = "allwinner,sun6i-a31-wdt"; 460 reg = <0x01c20ca0 0x20>; 461 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&osc24M>; 463 }; 464 465 pwm: pwm@1c21400 { 466 compatible = "allwinner,sun7i-a20-pwm"; 467 reg = <0x01c21400 0xc>; 468 clocks = <&osc24M>; 469 #pwm-cells = <3>; 470 status = "disabled"; 471 }; 472 473 lradc: lradc@1c22800 { 474 compatible = "allwinner,sun4i-a10-lradc-keys"; 475 reg = <0x01c22800 0x100>; 476 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 477 status = "disabled"; 478 }; 479 480 uart0: serial@1c28000 { 481 compatible = "snps,dw-apb-uart"; 482 reg = <0x01c28000 0x400>; 483 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 484 reg-shift = <2>; 485 reg-io-width = <4>; 486 clocks = <&ccu CLK_BUS_UART0>; 487 resets = <&ccu RST_BUS_UART0>; 488 dmas = <&dma 6>, <&dma 6>; 489 dma-names = "rx", "tx"; 490 status = "disabled"; 491 }; 492 493 uart1: serial@1c28400 { 494 compatible = "snps,dw-apb-uart"; 495 reg = <0x01c28400 0x400>; 496 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 497 reg-shift = <2>; 498 reg-io-width = <4>; 499 clocks = <&ccu CLK_BUS_UART1>; 500 resets = <&ccu RST_BUS_UART1>; 501 dmas = <&dma 7>, <&dma 7>; 502 dma-names = "rx", "tx"; 503 status = "disabled"; 504 }; 505 506 uart2: serial@1c28800 { 507 compatible = "snps,dw-apb-uart"; 508 reg = <0x01c28800 0x400>; 509 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 510 reg-shift = <2>; 511 reg-io-width = <4>; 512 clocks = <&ccu CLK_BUS_UART2>; 513 resets = <&ccu RST_BUS_UART2>; 514 dmas = <&dma 8>, <&dma 8>; 515 dma-names = "rx", "tx"; 516 status = "disabled"; 517 }; 518 519 uart3: serial@1c28c00 { 520 compatible = "snps,dw-apb-uart"; 521 reg = <0x01c28c00 0x400>; 522 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 523 reg-shift = <2>; 524 reg-io-width = <4>; 525 clocks = <&ccu CLK_BUS_UART3>; 526 resets = <&ccu RST_BUS_UART3>; 527 dmas = <&dma 9>, <&dma 9>; 528 dma-names = "rx", "tx"; 529 status = "disabled"; 530 }; 531 532 uart4: serial@1c29000 { 533 compatible = "snps,dw-apb-uart"; 534 reg = <0x01c29000 0x400>; 535 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 536 reg-shift = <2>; 537 reg-io-width = <4>; 538 clocks = <&ccu CLK_BUS_UART4>; 539 resets = <&ccu RST_BUS_UART4>; 540 dmas = <&dma 10>, <&dma 10>; 541 dma-names = "rx", "tx"; 542 status = "disabled"; 543 }; 544 545 i2c0: i2c@1c2ac00 { 546 compatible = "allwinner,sun6i-a31-i2c"; 547 reg = <0x01c2ac00 0x400>; 548 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&ccu CLK_BUS_I2C0>; 550 resets = <&ccu RST_BUS_I2C0>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&i2c0_pins>; 553 status = "disabled"; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 }; 557 558 i2c1: i2c@1c2b000 { 559 compatible = "allwinner,sun6i-a31-i2c"; 560 reg = <0x01c2b000 0x400>; 561 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&ccu CLK_BUS_I2C1>; 563 resets = <&ccu RST_BUS_I2C1>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&i2c1_pins>; 566 status = "disabled"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 }; 570 571 i2c2: i2c@1c2b400 { 572 compatible = "allwinner,sun6i-a31-i2c"; 573 reg = <0x01c2b400 0x400>; 574 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&ccu CLK_BUS_I2C2>; 576 resets = <&ccu RST_BUS_I2C2>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&i2c2_pins>; 579 status = "disabled"; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 }; 583 584 mali: gpu@1c40000 { 585 compatible = "allwinner,sun8i-a23-mali", 586 "allwinner,sun7i-a20-mali", "arm,mali-400"; 587 reg = <0x01c40000 0x10000>; 588 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 595 interrupt-names = "gp", 596 "gpmmu", 597 "pp0", 598 "ppmmu0", 599 "pp1", 600 "ppmmu1", 601 "pmu"; 602 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 603 clock-names = "bus", "core"; 604 resets = <&ccu RST_BUS_GPU>; 605 #cooling-cells = <2>; 606 607 assigned-clocks = <&ccu CLK_GPU>; 608 assigned-clock-rates = <384000000>; 609 }; 610 611 gic: interrupt-controller@1c81000 { 612 compatible = "arm,gic-400"; 613 reg = <0x01c81000 0x1000>, 614 <0x01c82000 0x2000>, 615 <0x01c84000 0x2000>, 616 <0x01c86000 0x2000>; 617 interrupt-controller; 618 #interrupt-cells = <3>; 619 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 620 }; 621 622 fe0: display-frontend@1e00000 { 623 /* compatible gets set in SoC specific dtsi file */ 624 reg = <0x01e00000 0x20000>; 625 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, 627 <&ccu CLK_DRAM_DE_FE>; 628 clock-names = "ahb", "mod", 629 "ram"; 630 resets = <&ccu RST_BUS_DE_FE>; 631 632 ports { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 636 fe0_out: port@1 { 637 reg = <1>; 638 639 fe0_out_be0: endpoint { 640 remote-endpoint = <&be0_in_fe0>; 641 }; 642 }; 643 }; 644 }; 645 646 be0: display-backend@1e60000 { 647 /* compatible gets set in SoC specific dtsi file */ 648 reg = <0x01e60000 0x10000>; 649 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, 651 <&ccu CLK_DRAM_DE_BE>; 652 clock-names = "ahb", "mod", 653 "ram"; 654 resets = <&ccu RST_BUS_DE_BE>; 655 656 ports { 657 #address-cells = <1>; 658 #size-cells = <0>; 659 660 be0_in: port@0 { 661 reg = <0>; 662 663 be0_in_fe0: endpoint { 664 remote-endpoint = <&fe0_out_be0>; 665 }; 666 }; 667 668 be0_out: port@1 { 669 reg = <1>; 670 671 be0_out_drc0: endpoint { 672 remote-endpoint = <&drc0_in_be0>; 673 }; 674 }; 675 }; 676 }; 677 678 drc0: drc@1e70000 { 679 /* compatible gets set in SoC specific dtsi file */ 680 reg = <0x01e70000 0x10000>; 681 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, 683 <&ccu CLK_DRAM_DRC>; 684 clock-names = "ahb", "mod", "ram"; 685 resets = <&ccu RST_BUS_DRC>; 686 687 ports { 688 #address-cells = <1>; 689 #size-cells = <0>; 690 691 drc0_in: port@0 { 692 reg = <0>; 693 694 drc0_in_be0: endpoint { 695 remote-endpoint = <&be0_out_drc0>; 696 }; 697 }; 698 699 drc0_out: port@1 { 700 reg = <1>; 701 702 drc0_out_tcon0: endpoint { 703 remote-endpoint = <&tcon0_in_drc0>; 704 }; 705 }; 706 }; 707 }; 708 709 rtc: rtc@1f00000 { 710 compatible = "allwinner,sun8i-a23-rtc"; 711 reg = <0x01f00000 0x400>; 712 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 714 clock-output-names = "osc32k", "osc32k-out"; 715 clocks = <&ext_osc32k>; 716 #clock-cells = <1>; 717 }; 718 719 nmi_intc: interrupt-controller@1f00c00 { 720 compatible = "allwinner,sun6i-a31-r-intc"; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 reg = <0x01f00c00 0x400>; 724 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 725 }; 726 727 prcm@1f01400 { 728 compatible = "allwinner,sun8i-a23-prcm"; 729 reg = <0x01f01400 0x200>; 730 731 ar100: ar100_clk { 732 compatible = "fixed-factor-clock"; 733 #clock-cells = <0>; 734 clock-div = <1>; 735 clock-mult = <1>; 736 clocks = <&osc24M>; 737 clock-output-names = "ar100"; 738 }; 739 740 ahb0: ahb0_clk { 741 compatible = "fixed-factor-clock"; 742 #clock-cells = <0>; 743 clock-div = <1>; 744 clock-mult = <1>; 745 clocks = <&ar100>; 746 clock-output-names = "ahb0"; 747 }; 748 749 apb0: apb0_clk { 750 compatible = "allwinner,sun8i-a23-apb0-clk"; 751 #clock-cells = <0>; 752 clocks = <&ahb0>; 753 clock-output-names = "apb0"; 754 }; 755 756 apb0_gates: apb0_gates_clk { 757 compatible = "allwinner,sun8i-a23-apb0-gates-clk"; 758 #clock-cells = <1>; 759 clocks = <&apb0>; 760 clock-output-names = "apb0_pio", "apb0_timer", 761 "apb0_rsb", "apb0_uart", 762 "apb0_i2c"; 763 }; 764 765 apb0_rst: apb0_rst { 766 compatible = "allwinner,sun6i-a31-clock-reset"; 767 #reset-cells = <1>; 768 }; 769 770 codec_analog: codec-analog { 771 compatible = "allwinner,sun8i-a23-codec-analog"; 772 }; 773 }; 774 775 cpucfg@1f01c00 { 776 compatible = "allwinner,sun8i-a23-cpuconfig"; 777 reg = <0x01f01c00 0x300>; 778 }; 779 780 r_uart: serial@1f02800 { 781 compatible = "snps,dw-apb-uart"; 782 reg = <0x01f02800 0x400>; 783 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 784 reg-shift = <2>; 785 reg-io-width = <4>; 786 clocks = <&apb0_gates 4>; 787 resets = <&apb0_rst 4>; 788 status = "disabled"; 789 }; 790 791 r_i2c: i2c@1f02400 { 792 compatible = "allwinner,sun8i-a23-i2c", 793 "allwinner,sun6i-a31-i2c"; 794 reg = <0x01f02400 0x400>; 795 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 796 pinctrl-names = "default"; 797 pinctrl-0 = <&r_i2c_pins>; 798 clocks = <&apb0_gates 6>; 799 resets = <&apb0_rst 6>; 800 status = "disabled"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 }; 804 805 r_pio: pinctrl@1f02c00 { 806 compatible = "allwinner,sun8i-a23-r-pinctrl"; 807 reg = <0x01f02c00 0x400>; 808 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; 810 clock-names = "apb", "hosc", "losc"; 811 resets = <&apb0_rst 0>; 812 gpio-controller; 813 interrupt-controller; 814 #interrupt-cells = <3>; 815 #gpio-cells = <3>; 816 817 r_i2c_pins: r-i2c-pins { 818 pins = "PL0", "PL1"; 819 function = "s_i2c"; 820 bias-pull-up; 821 }; 822 823 r_rsb_pins: r-rsb-pins { 824 pins = "PL0", "PL1"; 825 function = "s_rsb"; 826 drive-strength = <20>; 827 bias-pull-up; 828 }; 829 830 r_uart_pins_a: r-uart-pins { 831 pins = "PL2", "PL3"; 832 function = "s_uart"; 833 }; 834 }; 835 836 r_rsb: rsb@1f03400 { 837 compatible = "allwinner,sun8i-a23-rsb"; 838 reg = <0x01f03400 0x400>; 839 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&apb0_gates 3>; 841 clock-frequency = <3000000>; 842 resets = <&apb0_rst 3>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&r_rsb_pins>; 845 status = "disabled"; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 }; 849 }; 850}; 851