Searched +full:clock +full:- +full:latency +full:- +full:ns (Results 1 – 25 of 154) sorted by relevance
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/kernel/linux/linux-5.10/arch/arm/boot/dts/ |
D | tegra30-cpu-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 compatible = "operating-points-v2"; 6 opp-shared; 9 clock-latency-ns = <100000>; 10 opp-supported-hw = <0x1F 0x31FE>; 11 opp-hz = /bits/ 64 <51000000>; 15 clock-latency-ns = <100000>; 16 opp-supported-hw = <0x1F 0x0C01>; 17 opp-hz = /bits/ 64 <51000000>; 21 clock-latency-ns = <100000>; [all …]
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D | tegra20-cpu-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 compatible = "operating-points-v2"; 6 opp-shared; 9 clock-latency-ns = <400000>; 10 opp-supported-hw = <0x0F 0x0003>; 11 opp-hz = /bits/ 64 <216000000>; 15 clock-latency-ns = <400000>; 16 opp-supported-hw = <0x0F 0x0004>; 17 opp-hz = /bits/ 64 <216000000>; 21 clock-latency-ns = <400000>; [all …]
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D | exynos5800.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 19 &clock { 20 compatible = "samsung,exynos5800-clock", "syscon"; 24 opp-2000000000 { 25 opp-hz = /bits/ 64 <2000000000>; 26 opp-microvolt = <1312500 1312500 1500000>; 27 clock-latency-ns = <140000>; 29 opp-1900000000 { 30 opp-hz = /bits/ 64 <1900000000>; 31 opp-microvolt = <1262500 1262500 1500000>; [all …]
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D | pxa27x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 #include "dt-bindings/clock/pxa-clock.h" 11 pdma: dma-controller@40000000 { 12 compatible = "marvell,pdma-1.0"; 15 #dma-channels = <32>; 16 #dma-cells = <2>; 17 #dma-requests = <75>; 21 pxairq: interrupt-controller@40d00000 { 22 marvell,intc-priority; 23 marvell,intc-nr-irqs = <34>; [all …]
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D | sun8i-a33.dtsi | 2 * Copyright 2014 Chen-Yu Tsai 4 * Chen-Yu Tsai <wens@csie.org> 6 * This file is dual-licensed: you can use it either under the terms 45 #include "sun8i-a23-a33.dtsi" 46 #include <dt-bindings/thermal/thermal.h> 49 cpu0_opp_table: opp-table-cpu { 50 compatible = "operating-points-v2"; 51 opp-shared; 53 opp-120000000 { 54 opp-hz = /bits/ 64 <120000000>; [all …]
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D | exynos4412.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 19 #include "exynos4-cpu-thermal.dtsi" 29 fimc-lite0 = &fimc_lite_0; 30 fimc-lite1 = &fimc_lite_1; 35 #address-cells = <1>; 36 #size-cells = <0>; 40 compatible = "arm,cortex-a9"; 42 clocks = <&clock CLK_ARM_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu0_opp_table>; [all …]
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D | uniphier-pro5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 9 compatible = "socionext,uniphier-pro5"; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 #address-cells = <1>; 15 #size-cells = <0>; 19 compatible = "arm,cortex-a9"; 22 enable-method = "psci"; 23 next-level-cache = <&l2>; [all …]
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D | pxa25x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include "dt-bindings/clock/pxa-clock.h" 14 * The muxing of external clocks/internal dividers for osc* clock 17 #address-cells = <1>; 18 #size-cells = <1>; 22 compatible = "marvell,pxa250-core-clocks"; 23 #clock-cells = <1>; 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <3686400>; [all …]
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D | exynos5420.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 14 #include <dt-bindings/clock/exynos5420.h> 15 #include <dt-bindings/clock/exynos-audss-clk.h> 16 #include <dt-bindings/interrupt-controller/arm-gic.h> 42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. 46 compatible = "operating-points-v2"; 47 opp-shared; 49 opp-1800000000 { 50 opp-hz = /bits/ 64 <1800000000>; 51 opp-microvolt = <1250000 1250000 1500000>; [all …]
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D | exynos5250.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 17 #include <dt-bindings/clock/exynos5250.h> 19 #include "exynos4-cpu-thermal.dtsi" 20 #include <dt-bindings/clock/exynos-audss-clk.h> 50 #address-cells = <1>; 51 #size-cells = <0>; 55 compatible = "arm,cortex-a15"; 57 clocks = <&clock CLK_ARM_CLK>; 58 clock-names = "cpu"; 59 operating-points-v2 = <&cpu0_opp_table>; [all …]
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D | sun8i-a83t.dtsi | 6 * This file is dual-licensed: you can use it either under the terms 45 #include <dt-bindings/interrupt-controller/arm-gic.h> 47 #include <dt-bindings/clock/sun8i-a83t-ccu.h> 48 #include <dt-bindings/clock/sun8i-de2.h> 49 #include <dt-bindings/clock/sun8i-r-ccu.h> 50 #include <dt-bindings/reset/sun8i-a83t-ccu.h> 51 #include <dt-bindings/reset/sun8i-de2.h> 52 #include <dt-bindings/reset/sun8i-r-ccu.h> 53 #include <dt-bindings/thermal/thermal.h> 56 interrupt-parent = <&gic>; [all …]
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D | exynos4412-prime.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 11 * non-Prime version. Therefore we need to update OPPs table and 16 /delete-property/turbo-mode; 20 opp-1600000000 { 21 opp-hz = /bits/ 64 <1600000000>; 22 opp-microvolt = <1350000>; 23 clock-latency-ns = <200000>; 25 opp-1704000000 { 26 opp-hz = /bits/ 64 <1704000000>; 27 opp-microvolt = <1350000>; [all …]
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D | uniphier-pxs2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 #include <dt-bindings/thermal/thermal.h> 12 compatible = "socionext,uniphier-pxs2"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 22 compatible = "arm,cortex-a9"; [all …]
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D | qcom-ipq4019.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 6 /dts-v1/; 8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 13 #address-cells = <1>; 14 #size-cells = <1>; 18 interrupt-parent = <&intc>; 20 reserved-memory { 21 #address-cells = <0x1>; [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/opp/ |
D | qcom-nvmem-cpufreq.txt | 8 defines the voltage and frequency value based on the msm-id in SMEM 10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC 13 operating-points-v2 table when it is parsed by the OPP framework. 16 -------------------- 18 - operating-points-v2: Phandle to the operating-points-v2 table to use. 20 In 'operating-points-v2' table: 21 - compatible: Should be 22 - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974, 26 -------------------- 28 - power-domains: A phandle pointing to the PM domain specifier which provides [all …]
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D | allwinner,sun50i-h6-operating-points.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to 23 const: allwinner,sun50i-h6-operating-points 25 nvmem-cells: 27 A phandle pointing to a nvmem-cells node representing the efuse [all …]
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D | opp.txt | 2 ---------------------------------------------------- 4 Devices work at voltage-current-frequency combinations and some implementations 13 Binding 1: operating-points 16 This binding only supports voltage-frequency pairs. 19 - operating-points: An array of 2-tuples items, and each item consists 20 of frequency and voltage like <freq-kHz vol-uV>. 21 freq: clock frequency in kHz 27 compatible = "arm,cortex-a9"; 29 next-level-cache = <&L2>; 30 operating-points = < [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/ |
D | sun50i-h5-cpu-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org> 5 cpu_opp_table: opp-table-cpu { 6 compatible = "operating-points-v2"; 7 opp-shared; 9 opp-408000000 { 10 opp-hz = /bits/ 64 <408000000>; 11 opp-microvolt = <1000000 1000000 1310000>; 12 clock-latency-ns = <244144>; /* 8 32k periods */ 15 opp-648000000 { [all …]
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D | sun50i-a64-cpu-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 7 cpu0_opp_table: opp-table-cpu { 8 compatible = "operating-points-v2"; 9 opp-shared; 11 opp-648000000 { 12 opp-hz = /bits/ 64 <648000000>; 13 opp-microvolt = <1040000>; 14 clock-latency-ns = <244144>; /* 8 32k periods */ 17 opp-816000000 { 18 opp-hz = /bits/ 64 <816000000>; [all …]
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D | sun50i-h6-cpu-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 cpu_opp_table: opp-table-cpu { 7 compatible = "allwinner,sun50i-h6-operating-points"; 8 nvmem-cells = <&cpu_speed_grade>; 9 opp-shared; 12 clock-latency-ns = <244144>; /* 8 32k periods */ 13 opp-hz = /bits/ 64 <480000000>; 15 opp-microvolt-speed0 = <880000 880000 1200000>; 16 opp-microvolt-speed1 = <820000 820000 1200000>; 17 opp-microvolt-speed2 = <820000 820000 1200000>; [all …]
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D | sun50i-h5.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 #include <arm/sunxi-h3-h5.dtsi> 6 #include <dt-bindings/thermal/thermal.h> 10 #address-cells = <1>; 11 #size-cells = <0>; 14 compatible = "arm,cortex-a53"; 17 enable-method = "psci"; 19 clock-latency-ns = <244144>; /* 8 32k periods */ 20 #cooling-cells = <2>; 24 compatible = "arm,cortex-a53"; [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/ |
D | uniphier-ld20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/thermal/thermal.h> 13 compatible = "socionext,uniphier-ld20"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 19 #address-cells = <2>; [all …]
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D | uniphier-ld11.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 12 compatible = "socionext,uniphier-ld11"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <0>; 21 cpu-map { [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/ |
D | hi3660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/hi3660-clock.h> 10 #include <dt-bindings/thermal/thermal.h> 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 19 compatible = "arm,psci-0.2"; 24 #address-cells = <2>; 25 #size-cells = <0>; [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
D | ipq6018.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11 #include <dt-bindings/clock/qcom,apss-ipq.h> 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; [all …]
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