1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 model = "Qualcomm Technologies, Inc. IPQ4019"; 17 compatible = "qcom,ipq4019"; 18 interrupt-parent = <&intc>; 19 20 reserved-memory { 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 23 ranges; 24 25 smem_region: smem@87e00000 { 26 reg = <0x87e00000 0x080000>; 27 no-map; 28 }; 29 30 tz@87e80000 { 31 reg = <0x87e80000 0x180000>; 32 no-map; 33 }; 34 }; 35 36 aliases { 37 spi0 = &blsp1_spi1; 38 spi1 = &blsp1_spi2; 39 i2c0 = &blsp1_i2c3; 40 i2c1 = &blsp1_i2c4; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 enable-method = "qcom,kpss-acc-v2"; 50 next-level-cache = <&L2>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 reg = <0x0>; 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 clock-frequency = <0>; 56 clock-latency = <256000>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 }; 59 60 cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 enable-method = "qcom,kpss-acc-v2"; 64 next-level-cache = <&L2>; 65 qcom,acc = <&acc1>; 66 qcom,saw = <&saw1>; 67 reg = <0x1>; 68 clocks = <&gcc GCC_APPS_CLK_SRC>; 69 clock-frequency = <0>; 70 clock-latency = <256000>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 enable-method = "qcom,kpss-acc-v2"; 78 next-level-cache = <&L2>; 79 qcom,acc = <&acc2>; 80 qcom,saw = <&saw2>; 81 reg = <0x2>; 82 clocks = <&gcc GCC_APPS_CLK_SRC>; 83 clock-frequency = <0>; 84 clock-latency = <256000>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 }; 87 88 cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a7"; 91 enable-method = "qcom,kpss-acc-v2"; 92 next-level-cache = <&L2>; 93 qcom,acc = <&acc3>; 94 qcom,saw = <&saw3>; 95 reg = <0x3>; 96 clocks = <&gcc GCC_APPS_CLK_SRC>; 97 clock-frequency = <0>; 98 clock-latency = <256000>; 99 operating-points-v2 = <&cpu0_opp_table>; 100 }; 101 102 L2: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 qcom,saw = <&saw_l2>; 106 }; 107 }; 108 109 cpu0_opp_table: opp_table0 { 110 compatible = "operating-points-v2"; 111 opp-shared; 112 113 opp-48000000 { 114 opp-hz = /bits/ 64 <48000000>; 115 clock-latency-ns = <256000>; 116 }; 117 opp-200000000 { 118 opp-hz = /bits/ 64 <200000000>; 119 clock-latency-ns = <256000>; 120 }; 121 opp-500000000 { 122 opp-hz = /bits/ 64 <500000000>; 123 clock-latency-ns = <256000>; 124 }; 125 opp-716000000 { 126 opp-hz = /bits/ 64 <716000000>; 127 clock-latency-ns = <256000>; 128 }; 129 }; 130 131 memory { 132 device_type = "memory"; 133 reg = <0x0 0x0>; 134 }; 135 136 pmu { 137 compatible = "arm,cortex-a7-pmu"; 138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 139 IRQ_TYPE_LEVEL_HIGH)>; 140 }; 141 142 clocks { 143 sleep_clk: sleep_clk { 144 compatible = "fixed-clock"; 145 clock-frequency = <32000>; 146 clock-output-names = "gcc_sleep_clk_src"; 147 #clock-cells = <0>; 148 }; 149 150 xo: xo { 151 compatible = "fixed-clock"; 152 clock-frequency = <48000000>; 153 #clock-cells = <0>; 154 }; 155 }; 156 157 firmware { 158 scm { 159 compatible = "qcom,scm-ipq4019"; 160 }; 161 }; 162 163 timer { 164 compatible = "arm,armv7-timer"; 165 interrupts = <1 2 0xf08>, 166 <1 3 0xf08>, 167 <1 4 0xf08>, 168 <1 1 0xf08>; 169 clock-frequency = <48000000>; 170 always-on; 171 }; 172 173 soc { 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges; 177 compatible = "simple-bus"; 178 179 intc: interrupt-controller@b000000 { 180 compatible = "qcom,msm-qgic2"; 181 interrupt-controller; 182 #interrupt-cells = <3>; 183 reg = <0x0b000000 0x1000>, 184 <0x0b002000 0x1000>; 185 }; 186 187 gcc: clock-controller@1800000 { 188 compatible = "qcom,gcc-ipq4019"; 189 #clock-cells = <1>; 190 #reset-cells = <1>; 191 reg = <0x1800000 0x60000>; 192 }; 193 194 rng@22000 { 195 compatible = "qcom,prng"; 196 reg = <0x22000 0x140>; 197 clocks = <&gcc GCC_PRNG_AHB_CLK>; 198 clock-names = "core"; 199 status = "disabled"; 200 }; 201 202 tlmm: pinctrl@1000000 { 203 compatible = "qcom,ipq4019-pinctrl"; 204 reg = <0x01000000 0x300000>; 205 gpio-controller; 206 gpio-ranges = <&tlmm 0 0 100>; 207 #gpio-cells = <2>; 208 interrupt-controller; 209 #interrupt-cells = <2>; 210 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 211 }; 212 213 sdhci: sdhci@7824900 { 214 compatible = "qcom,sdhci-msm-v4"; 215 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 216 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 217 interrupt-names = "hc_irq", "pwr_irq"; 218 bus-width = <8>; 219 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, 220 <&gcc GCC_DCD_XO_CLK>; 221 clock-names = "core", "iface", "xo"; 222 status = "disabled"; 223 }; 224 225 blsp_dma: dma@7884000 { 226 compatible = "qcom,bam-v1.7.0"; 227 reg = <0x07884000 0x23000>; 228 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 230 clock-names = "bam_clk"; 231 #dma-cells = <1>; 232 qcom,ee = <0>; 233 status = "disabled"; 234 }; 235 236 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 237 compatible = "qcom,spi-qup-v2.2.1"; 238 reg = <0x78b5000 0x600>; 239 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 241 <&gcc GCC_BLSP1_AHB_CLK>; 242 clock-names = "core", "iface"; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 246 dma-names = "rx", "tx"; 247 status = "disabled"; 248 }; 249 250 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 251 compatible = "qcom,spi-qup-v2.2.1"; 252 reg = <0x78b6000 0x600>; 253 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 255 <&gcc GCC_BLSP1_AHB_CLK>; 256 clock-names = "core", "iface"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 260 dma-names = "rx", "tx"; 261 status = "disabled"; 262 }; 263 264 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 265 compatible = "qcom,i2c-qup-v2.2.1"; 266 reg = <0x78b7000 0x600>; 267 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 269 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 270 clock-names = "iface", "core"; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 274 dma-names = "rx", "tx"; 275 status = "disabled"; 276 }; 277 278 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 279 compatible = "qcom,i2c-qup-v2.2.1"; 280 reg = <0x78b8000 0x600>; 281 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 283 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 284 clock-names = "iface", "core"; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 288 dma-names = "rx", "tx"; 289 status = "disabled"; 290 }; 291 292 cryptobam: dma@8e04000 { 293 compatible = "qcom,bam-v1.7.0"; 294 reg = <0x08e04000 0x20000>; 295 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 297 clock-names = "bam_clk"; 298 #dma-cells = <1>; 299 qcom,ee = <1>; 300 qcom,controlled-remotely; 301 status = "disabled"; 302 }; 303 304 crypto@8e3a000 { 305 compatible = "qcom,crypto-v5.1"; 306 reg = <0x08e3a000 0x6000>; 307 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 308 <&gcc GCC_CRYPTO_AXI_CLK>, 309 <&gcc GCC_CRYPTO_CLK>; 310 clock-names = "iface", "bus", "core"; 311 dmas = <&cryptobam 2>, <&cryptobam 3>; 312 dma-names = "rx", "tx"; 313 status = "disabled"; 314 }; 315 316 acc0: clock-controller@b088000 { 317 compatible = "qcom,kpss-acc-v2"; 318 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 319 }; 320 321 acc1: clock-controller@b098000 { 322 compatible = "qcom,kpss-acc-v2"; 323 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 324 }; 325 326 acc2: clock-controller@b0a8000 { 327 compatible = "qcom,kpss-acc-v2"; 328 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 329 }; 330 331 acc3: clock-controller@b0b8000 { 332 compatible = "qcom,kpss-acc-v2"; 333 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 334 }; 335 336 saw0: regulator@b089000 { 337 compatible = "qcom,saw2"; 338 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; 339 regulator; 340 }; 341 342 saw1: regulator@b099000 { 343 compatible = "qcom,saw2"; 344 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 345 regulator; 346 }; 347 348 saw2: regulator@b0a9000 { 349 compatible = "qcom,saw2"; 350 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 351 regulator; 352 }; 353 354 saw3: regulator@b0b9000 { 355 compatible = "qcom,saw2"; 356 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 357 regulator; 358 }; 359 360 saw_l2: regulator@b012000 { 361 compatible = "qcom,saw2"; 362 reg = <0xb012000 0x1000>; 363 regulator; 364 }; 365 366 blsp1_uart1: serial@78af000 { 367 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 368 reg = <0x78af000 0x200>; 369 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 370 status = "disabled"; 371 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 372 <&gcc GCC_BLSP1_AHB_CLK>; 373 clock-names = "core", "iface"; 374 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 375 dma-names = "rx", "tx"; 376 }; 377 378 blsp1_uart2: serial@78b0000 { 379 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 380 reg = <0x78b0000 0x200>; 381 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 382 status = "disabled"; 383 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 384 <&gcc GCC_BLSP1_AHB_CLK>; 385 clock-names = "core", "iface"; 386 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 387 dma-names = "rx", "tx"; 388 }; 389 390 watchdog@b017000 { 391 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; 392 reg = <0xb017000 0x40>; 393 clocks = <&sleep_clk>; 394 timeout-sec = <10>; 395 status = "disabled"; 396 }; 397 398 restart@4ab000 { 399 compatible = "qcom,pshold"; 400 reg = <0x4ab000 0x4>; 401 }; 402 403 pcie0: pci@40000000 { 404 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; 405 reg = <0x40000000 0xf1d 406 0x40000f20 0xa8 407 0x80000 0x2000 408 0x40100000 0x1000>; 409 reg-names = "dbi", "elbi", "parf", "config"; 410 device_type = "pci"; 411 linux,pci-domain = <0>; 412 bus-range = <0x00 0xff>; 413 num-lanes = <1>; 414 #address-cells = <3>; 415 #size-cells = <2>; 416 417 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, 418 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; 419 420 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 421 interrupt-names = "msi"; 422 #interrupt-cells = <1>; 423 interrupt-map-mask = <0 0 0 0x7>; 424 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 425 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 426 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 427 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 428 clocks = <&gcc GCC_PCIE_AHB_CLK>, 429 <&gcc GCC_PCIE_AXI_M_CLK>, 430 <&gcc GCC_PCIE_AXI_S_CLK>; 431 clock-names = "aux", 432 "master_bus", 433 "slave_bus"; 434 435 resets = <&gcc PCIE_AXI_M_ARES>, 436 <&gcc PCIE_AXI_S_ARES>, 437 <&gcc PCIE_PIPE_ARES>, 438 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 439 <&gcc PCIE_AXI_S_XPU_ARES>, 440 <&gcc PCIE_PARF_XPU_ARES>, 441 <&gcc PCIE_PHY_ARES>, 442 <&gcc PCIE_AXI_M_STICKY_ARES>, 443 <&gcc PCIE_PIPE_STICKY_ARES>, 444 <&gcc PCIE_PWR_ARES>, 445 <&gcc PCIE_AHB_ARES>, 446 <&gcc PCIE_PHY_AHB_ARES>; 447 reset-names = "axi_m", 448 "axi_s", 449 "pipe", 450 "axi_m_vmid", 451 "axi_s_xpu", 452 "parf", 453 "phy", 454 "axi_m_sticky", 455 "pipe_sticky", 456 "pwr", 457 "ahb", 458 "phy_ahb"; 459 460 status = "disabled"; 461 }; 462 463 qpic_bam: dma@7984000 { 464 compatible = "qcom,bam-v1.7.0"; 465 reg = <0x7984000 0x1a000>; 466 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&gcc GCC_QPIC_CLK>; 468 clock-names = "bam_clk"; 469 #dma-cells = <1>; 470 qcom,ee = <0>; 471 status = "disabled"; 472 }; 473 474 nand: qpic-nand@79b0000 { 475 compatible = "qcom,ipq4019-nand"; 476 reg = <0x79b0000 0x1000>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 clocks = <&gcc GCC_QPIC_CLK>, 480 <&gcc GCC_QPIC_AHB_CLK>; 481 clock-names = "core", "aon"; 482 483 dmas = <&qpic_bam 0>, 484 <&qpic_bam 1>, 485 <&qpic_bam 2>; 486 dma-names = "tx", "rx", "cmd"; 487 status = "disabled"; 488 489 nand@0 { 490 reg = <0>; 491 492 nand-ecc-strength = <4>; 493 nand-ecc-step-size = <512>; 494 nand-bus-width = <8>; 495 }; 496 }; 497 498 wifi0: wifi@a000000 { 499 compatible = "qcom,ipq4019-wifi"; 500 reg = <0xa000000 0x200000>; 501 resets = <&gcc WIFI0_CPU_INIT_RESET>, 502 <&gcc WIFI0_RADIO_SRIF_RESET>, 503 <&gcc WIFI0_RADIO_WARM_RESET>, 504 <&gcc WIFI0_RADIO_COLD_RESET>, 505 <&gcc WIFI0_CORE_WARM_RESET>, 506 <&gcc WIFI0_CORE_COLD_RESET>; 507 reset-names = "wifi_cpu_init", "wifi_radio_srif", 508 "wifi_radio_warm", "wifi_radio_cold", 509 "wifi_core_warm", "wifi_core_cold"; 510 clocks = <&gcc GCC_WCSS2G_CLK>, 511 <&gcc GCC_WCSS2G_REF_CLK>, 512 <&gcc GCC_WCSS2G_RTC_CLK>; 513 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 514 "wifi_wcss_rtc"; 515 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 516 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 517 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 518 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 519 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 520 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 521 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 522 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 523 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 524 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 525 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 526 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 527 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 528 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 529 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 530 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 531 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 532 interrupt-names = "msi0", "msi1", "msi2", "msi3", 533 "msi4", "msi5", "msi6", "msi7", 534 "msi8", "msi9", "msi10", "msi11", 535 "msi12", "msi13", "msi14", "msi15", 536 "legacy"; 537 status = "disabled"; 538 }; 539 540 wifi1: wifi@a800000 { 541 compatible = "qcom,ipq4019-wifi"; 542 reg = <0xa800000 0x200000>; 543 resets = <&gcc WIFI1_CPU_INIT_RESET>, 544 <&gcc WIFI1_RADIO_SRIF_RESET>, 545 <&gcc WIFI1_RADIO_WARM_RESET>, 546 <&gcc WIFI1_RADIO_COLD_RESET>, 547 <&gcc WIFI1_CORE_WARM_RESET>, 548 <&gcc WIFI1_CORE_COLD_RESET>; 549 reset-names = "wifi_cpu_init", "wifi_radio_srif", 550 "wifi_radio_warm", "wifi_radio_cold", 551 "wifi_core_warm", "wifi_core_cold"; 552 clocks = <&gcc GCC_WCSS5G_CLK>, 553 <&gcc GCC_WCSS5G_REF_CLK>, 554 <&gcc GCC_WCSS5G_RTC_CLK>; 555 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 556 "wifi_wcss_rtc"; 557 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 558 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 559 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 560 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 561 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 562 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 563 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 564 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 565 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 566 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 567 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 568 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 569 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 570 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 571 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 572 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 573 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "msi0", "msi1", "msi2", "msi3", 575 "msi4", "msi5", "msi6", "msi7", 576 "msi8", "msi9", "msi10", "msi11", 577 "msi12", "msi13", "msi14", "msi15", 578 "legacy"; 579 status = "disabled"; 580 }; 581 582 mdio: mdio@90000 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 compatible = "qcom,ipq4019-mdio"; 586 reg = <0x90000 0x64>; 587 status = "disabled"; 588 589 ethphy0: ethernet-phy@0 { 590 reg = <0>; 591 }; 592 593 ethphy1: ethernet-phy@1 { 594 reg = <1>; 595 }; 596 597 ethphy2: ethernet-phy@2 { 598 reg = <2>; 599 }; 600 601 ethphy3: ethernet-phy@3 { 602 reg = <3>; 603 }; 604 605 ethphy4: ethernet-phy@4 { 606 reg = <4>; 607 }; 608 }; 609 }; 610}; 611