| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | rtsm_ve-aemv8a.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
97 gic: interrupt-controller@2c001000 { label
98 compatible = "arm,gic-400", "arm,cortex-a15-gic";
149 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
152 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
153 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
154 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | vexpress-v2f-1xv7-ca53x2.dts | 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
82 gic: interrupt-controller@2c001000 { label
83 compatible = "arm,gic-400";
161 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
162 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
163 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
164 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
165 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
166 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | fvp-base-revc.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
115 gic: interrupt-controller@2f000000 { label
116 compatible = "arm,gic-v3";
131 compatible = "arm,gic-v3-its";
164 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
165 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
166 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
167 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | foundation-v8.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
131 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
132 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
133 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
134 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
135 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
136 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
137 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
138 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-gic.c | 5 * Interrupt architecture for the GIC:
40 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
113 * The GIC mapping of CPU interfaces does not necessarily match
115 * by the GIC itself.
311 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); in gic_set_type()
320 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
339 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
340 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
355 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
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| D | irq-gic-pm.c | 9 #include <linux/irqchip/arm-gic.h>
28 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_resume() local
41 * want to restore the GIC on the very first resume. So if in gic_runtime_resume()
44 if (!gic) in gic_runtime_resume()
47 gic_dist_restore(gic); in gic_runtime_resume()
48 gic_cpu_restore(gic); in gic_runtime_resume()
56 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_suspend() local
59 gic_dist_save(gic); in gic_runtime_suspend()
60 gic_cpu_save(gic); in gic_runtime_suspend()
117 dev_info(dev, "GIC IRQ controller registered\n"); in gic_probe()
[all …]
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| D | Makefile | 29 obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
30 obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o
31 obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o
32 obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
33 obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o
34 obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o
35 obj-$(CONFIG_ARM_GIC_V3_ITS_PCI) += irq-gic-v3-its-pci-msi.o
36 obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o
71 obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca5s.dts | 19 interrupt-parent = <&gic>;
121 gic: interrupt-controller@2c001000 { label
122 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
223 interrupt-map = <0 0 0 &gic 0 0 4>,
224 <0 0 1 &gic 0 1 4>,
225 <0 0 2 &gic 0 2 4>,
226 <0 0 3 &gic 0 3 4>,
227 <0 0 4 &gic 0 4 4>,
228 <0 0 5 &gic 0 5 4>,
229 <0 0 6 &gic 0 6 4>,
[all …]
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| D | vexpress-v2p-ca15-tc1.dts | 19 interrupt-parent = <&gic>;
94 gic: interrupt-controller@2c001000 { label
95 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
253 interrupt-map = <0 0 0 &gic 0 0 4>,
254 <0 0 1 &gic 0 1 4>,
255 <0 0 2 &gic 0 2 4>,
256 <0 0 3 &gic 0 3 4>,
257 <0 0 4 &gic 0 4 4>,
258 <0 0 5 &gic 0 5 4>,
259 <0 0 6 &gic 0 6 4>,
[all …]
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| D | vexpress-v2p-ca9.dts | 19 interrupt-parent = <&gic>;
155 gic: interrupt-controller@1e001000 { label
156 compatible = "arm,cortex-a9-gic";
311 interrupt-map = <0 0 0 &gic 0 0 4>,
312 <0 0 1 &gic 0 1 4>,
313 <0 0 2 &gic 0 2 4>,
314 <0 0 3 &gic 0 3 4>,
315 <0 0 4 &gic 0 4 4>,
316 <0 0 5 &gic 0 5 4>,
317 <0 0 6 &gic 0 6 4>,
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| D | bcm5301x.dtsi | 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
88 gic: interrupt-controller@21000 { label
89 compatible = "arm,cortex-a9-gic";
171 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
176 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
177 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
178 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | vexpress-v2p-ca15_a7.dts | 19 interrupt-parent = <&gic>;
149 gic: interrupt-controller@2c001000 { label
150 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
625 interrupt-map = <0 0 0 &gic 0 0 4>,
626 <0 0 1 &gic 0 1 4>,
627 <0 0 2 &gic 0 2 4>,
628 <0 0 3 &gic 0 3 4>,
629 <0 0 4 &gic 0 4 4>,
630 <0 0 5 &gic 0 5 4>,
631 <0 0 6 &gic 0 6 4>,
[all …]
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| D | bcm53573.dtsi | 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
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| D | mti,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
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| D | renesas,rza1-irqc.yaml | 14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | arm,gic-v3.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
73 Specifies base physical address(s) and size of the GIC
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
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| D | fsl,ls-extirq.txt | 17 - interrupt-map: Specifies the mapping from external interrupts to GIC
37 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
38 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
39 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
40 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
41 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
42 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
48 interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp.dtsi | 109 interrupt-parent = <&gic>;
129 interrupt-parent = <&gic>;
170 interrupt-parent = <&gic>;
191 gic: interrupt-controller@f9010000 { label
192 compatible = "arm,gic-400";
199 interrupt-parent = <&gic>;
216 interrupt-parent = <&gic>;
228 interrupt-parent = <&gic>;
244 interrupt-parent = <&gic>;
258 interrupt-parent = <&gic>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/cavium/ |
| D | thunder2-99xx.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
58 gic: interrupt-controller@400080000 { label
59 compatible = "arm,gic-v3";
70 gicits: gic-its@40010000 {
71 compatible = "arm,gic-v3-its";
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
121 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
122 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
123 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | mips-gic.h | 8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
16 /* The base address of the GIC registers */
19 /* Offsets from the GIC base address to various control blocks */
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
35 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
39 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
40 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
44 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
45 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
163 /* GIC_SH_CONFIG - Information about the GIC configuration */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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| /kernel/linux/linux-5.10/arch/arm/mach-ux500/ |
| D | pm.c | 11 #include <linux/irqchip/arm-gic.h>
46 /* This function decouple the gic from the prcmu */
58 /* Wait a few cycles for the gic mask completion */ in prcmu_gic_decouple()
64 /* This function recouple the gic with the prcmu */
78 * This function checks if there are pending irq on the gic. It only
79 * makes sense if the gic has been decoupled before with the
128 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
139 * This function copies the gic SPI settings to the prcmu in order to
187 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); in ux500_pm_init()
191 pr_err("could not remap GIC dist base for PM functions\n"); in ux500_pm_init()
[all …]
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/mti/ |
| D | sead3.dts | 8 #include <dt-bindings/interrupt-controller/mips-gic.h>
43 gic: interrupt-controller@1b1c0000 { label
44 compatible = "mti,gic";
51 * Declare the interrupt-parent even though the mti,gic
63 interrupt-parent = <&gic>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
226 interrupt-parent = <&gic>;
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
241 interrupt-parent = <&gic>;
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/ |
| D | r8a779a0.dtsi | 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
65 interrupt-parent = <&gic>;
105 gic: interrupt-controller@f1000000 { label
106 compatible = "arm,gic-v3";
124 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
125 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
126 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
127 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|