1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779a0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779a0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 a76_0: cpu@0 { 22 compatible = "arm,cortex-a76"; 23 reg = <0>; 24 device_type = "cpu"; 25 power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; 26 next-level-cache = <&L3_CA76_0>; 27 }; 28 29 L3_CA76_0: cache-controller-0 { 30 compatible = "cache"; 31 power-domains = <&sysc R8A779A0_PD_A2E0D0>; 32 cache-unified; 33 cache-level = <3>; 34 }; 35 }; 36 37 extal_clk: extal { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 /* This value must be overridden by the board */ 41 clock-frequency = <0>; 42 }; 43 44 extalr_clk: extalr { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 /* This value must be overridden by the board */ 48 clock-frequency = <0>; 49 }; 50 51 pmu_a76 { 52 compatible = "arm,cortex-a76-pmu"; 53 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 54 }; 55 56 /* External SCIF clock - to be overridden by boards that provide it */ 57 scif_clk: scif { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <0>; 61 }; 62 63 soc: soc { 64 compatible = "simple-bus"; 65 interrupt-parent = <&gic>; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 ranges; 69 70 cpg: clock-controller@e6150000 { 71 compatible = "renesas,r8a779a0-cpg-mssr"; 72 reg = <0 0xe6150000 0 0x4000>; 73 clocks = <&extal_clk>, <&extalr_clk>; 74 clock-names = "extal", "extalr"; 75 #clock-cells = <2>; 76 #power-domain-cells = <0>; 77 #reset-cells = <1>; 78 }; 79 80 rst: reset-controller@e6160000 { 81 compatible = "renesas,r8a779a0-rst"; 82 reg = <0 0xe6160000 0 0x4000>; 83 }; 84 85 sysc: system-controller@e6180000 { 86 compatible = "renesas,r8a779a0-sysc"; 87 reg = <0 0xe6180000 0 0x4000>; 88 #power-domain-cells = <1>; 89 }; 90 91 scif0: serial@e6e60000 { 92 compatible = "renesas,scif-r8a779a0", 93 "renesas,rcar-gen3-scif", "renesas,scif"; 94 reg = <0 0xe6e60000 0 64>; 95 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 96 clocks = <&cpg CPG_MOD 702>, 97 <&cpg CPG_CORE R8A779A0_CLK_S1D2>, 98 <&scif_clk>; 99 clock-names = "fck", "brg_int", "scif_clk"; 100 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 101 resets = <&cpg 702>; 102 status = "disabled"; 103 }; 104 105 gic: interrupt-controller@f1000000 { 106 compatible = "arm,gic-v3"; 107 #interrupt-cells = <3>; 108 #address-cells = <0>; 109 interrupt-controller; 110 reg = <0x0 0xf1000000 0 0x20000>, 111 <0x0 0xf1060000 0 0x110000>; 112 interrupts = <GIC_PPI 9 113 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 114 }; 115 116 prr: chipid@fff00044 { 117 compatible = "renesas,prr"; 118 reg = <0 0xfff00044 0 4>; 119 }; 120 }; 121 122 timer { 123 compatible = "arm,armv8-timer"; 124 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 125 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 126 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 127 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 128 }; 129}; 130