| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-pruss-intc.c | 3 * PRU-ICSS INTC IRQChip driver for various TI SoCs
26 * INTC instance
85 * @num_system_events: number of input system events handled by the PRUSS INTC
87 * channels) supported by the PRUSS INTC
99 * @base: base virtual address of INTC register space
101 * @soc_config: cached PRUSS INTC IP configuration data
102 * @dev: PRUSS INTC device pointer
113 struct mutex lock; /* PRUSS INTC lock */
118 * @intc: PRUSS interrupt controller pointer
122 struct pruss_intc *intc; member
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| D | irq-bcm7038-l1.c | 83 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
86 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
89 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
92 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
95 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
98 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
101 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
104 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
125 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
131 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
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| D | irq-bcm6345-l1.c | 90 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, in reg_enable() argument
94 return (1 * intc->n_words - word - 1) * sizeof(u32); in reg_enable()
96 return (0 * intc->n_words + word) * sizeof(u32); in reg_enable()
100 static inline unsigned int reg_status(struct bcm6345_l1_chip *intc, in reg_status() argument
104 return (2 * intc->n_words - word - 1) * sizeof(u32); in reg_status()
106 return (1 * intc->n_words + word) * sizeof(u32); in reg_status()
110 static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, in cpu_for_irq() argument
113 return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d)); in cpu_for_irq()
118 struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm6345_l1_irq_handle() local
124 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm6345_l1_irq_handle()
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| D | irq-ingenic.c | 36 struct ingenic_intc_data *intc = irq_get_handler_data(irq); in intc_cascade() local
37 struct irq_domain *domain = intc->domain; in intc_cascade()
42 for (i = 0; i < intc->num_chips; i++) { in intc_cascade()
64 struct ingenic_intc_data *intc; in ingenic_intc_of_init() local
71 intc = kzalloc(sizeof(*intc), GFP_KERNEL); in ingenic_intc_of_init()
72 if (!intc) { in ingenic_intc_of_init()
83 err = irq_set_handler_data(parent_irq, intc); in ingenic_intc_of_init()
87 intc->num_chips = num_chips; in ingenic_intc_of_init()
88 intc->base = of_iomap(node, 0); in ingenic_intc_of_init()
89 if (!intc->base) { in ingenic_intc_of_init()
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| D | irq-bcm2836.c | 23 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_mask_per_cpu_irq()
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_unmask_per_cpu_irq()
65 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR); in bcm2836_arm_irqchip_mask_pmu_irq()
70 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET); in bcm2836_arm_irqchip_unmask_pmu_irq()
142 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu); in bcm2836_arm_irqchip_handle_irq()
146 handle_domain_irq(intc.domain, hwirq, regs); in bcm2836_arm_irqchip_handle_irq()
161 mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu); in bcm2836_arm_irqchip_handle_ipi()
175 intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu); in bcm2836_arm_irqchip_ipi_eoi()
182 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0; in bcm2836_arm_irqchip_ipi_send_mask()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
51 intc: interrupt-controller@1e000000 { label
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
90 interrupt-parent = <&intc>;
95 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
105 interrupt-parent = <&intc>;
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| D | arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
109 intc: interrupt-controller@1f000000 { label
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
135 interrupt-parent = <&intc>;
140 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
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| D | arm-realview-eb.dts | 51 intc: interrupt-controller@10040000 { label
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
104 interrupt-parent = <&intc>;
109 interrupt-parent = <&intc>;
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| D | arm-realview-eb-mp.dtsi | 41 intc: interrupt-controller@1f000100 { label
58 interrupt-parent = <&intc>;
65 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
101 interrupt-parent = <&intc>;
108 interrupt-parent = <&intc>;
123 interrupt-parent = <&intc>;
128 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
138 interrupt-parent = <&intc>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mrvl,intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
21 const: marvell,orion-intc
24 - mrvl,intc-nr-irqs
30 - mrvl,mmp-intc
31 - mrvl,mmp2-intc
41 - marvell,mmp3-intc
42 - mrvl,mmp2-mux-intc
51 const: mrvl,mmp2-mux-intc
72 - mrvl,mmp-intc
73 - mrvl,mmp2-intc
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| D | ingenic,intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/ingenic,intc.yaml#
19 - ingenic,jz4740-intc
20 - ingenic,jz4760-intc
21 - ingenic,jz4780-intc
24 - ingenic,jz4775-intc
25 - ingenic,jz4770-intc
26 - const: ingenic,jz4760-intc
28 - const: ingenic,x1000-intc
29 - const: ingenic,jz4780-intc
31 - const: ingenic,jz4725b-intc
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| D | csky,apb-intc.txt | 8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
13 intc node bindings definition
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
25 "csky,gx6605s-intc"
43 intc: interrupt-controller@500000 {
44 compatible = "csky,apb-intc";
50 intc: interrupt-controller@500000 {
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| D | ti,omap-intc-irq.txt | 1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
16 source, should be 1 for intc
23 intc: interrupt-controller@48200000 {
24 compatible = "ti,omap3-intc";
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| D | amlogic,meson-gpio-intc.txt | 12 - compatible : must have "amlogic,meson8-gpio-intc" and either
13 "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
14 "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
15 "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
16 "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
17 "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
18 "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
19 "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
20 "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
31 compatible = "amlogic,meson-gxbb-gpio-intc",
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| D | renesas,intc-irqpin.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
7 title: Renesas Interrupt Controller (INTC) for external pins
16 - renesas,intc-irqpin-r8a7740 # R-Mobile A1
17 - renesas,intc-irqpin-r8a7778 # R-Car M1A
18 - renesas,intc-irqpin-r8a7779 # R-Car H1
19 - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
20 - const: renesas,intc-irqpin
73 - renesas,intc-irqpin-r8a7740
74 - renesas,intc-irqpin-sh73a0
89 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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| D | renesas,irqc.yaml | 27 - renesas,intc-ex-r8a774a1 # RZ/G2M
28 - renesas,intc-ex-r8a774b1 # RZ/G2N
29 - renesas,intc-ex-r8a774c0 # RZ/G2E
30 - renesas,intc-ex-r8a7795 # R-Car H3
31 - renesas,intc-ex-r8a7796 # R-Car M3-W
32 - renesas,intc-ex-r8a77965 # R-Car M3-N
33 - renesas,intc-ex-r8a77970 # R-Car V3M
34 - renesas,intc-ex-r8a77980 # R-Car V3H
35 - renesas,intc-ex-r8a77990 # R-Car E3
36 - renesas,intc-ex-r8a77995 # R-Car D3
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| /kernel/linux/linux-5.10/arch/mips/pci/ |
| D | fixup-sni.c | 26 #define INTC PCIMT_IRQ_INTC macro
44 /* INTA INTB INTC INTD */
50 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
51 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
52 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
61 /* INTA INTB INTC INTD */
64 { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
67 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
68 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
69 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
[all …]
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| /kernel/linux/linux-5.10/arch/m68k/coldfire/ |
| D | Makefile | 19 obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o
20 obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
21 obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
22 obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
23 obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
24 obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
25 obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
26 obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
27 obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
28 obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
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| /kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/ |
| D | microdev.h | 17 * controller (INTC) on the CPU-board FPGA. should be noted that there
18 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
23 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
24 …INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
25 …NTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
26 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-bo…
27 …(MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
29 …(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
30 …TSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */
31 …REQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | irq-s3c24xx.c | 47 struct s3c_irq_intc *intc; member
55 * @reg_intpnd special register intpnd in main intc
81 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_mask() local
82 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_mask()
87 mask = readl_relaxed(intc->reg_mask); in s3c_irq_mask()
89 writel_relaxed(mask, intc->reg_mask); in s3c_irq_mask()
109 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_unmask() local
110 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_unmask()
114 mask = readl_relaxed(intc->reg_mask); in s3c_irq_unmask()
116 writel_relaxed(mask, intc->reg_mask); in s3c_irq_unmask()
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/ |
| D | jz4770.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4770-intc";
92 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
155 interrupt-parent = <&intc>;
170 interrupt-parent = <&intc>;
185 interrupt-parent = <&intc>;
200 interrupt-parent = <&intc>;
215 interrupt-parent = <&intc>;
230 interrupt-parent = <&intc>;
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| D | x1000.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
81 interrupt-parent = <&intc>;
97 interrupt-parent = <&intc>;
121 interrupt-parent = <&intc>;
136 interrupt-parent = <&intc>;
151 interrupt-parent = <&intc>;
166 interrupt-parent = <&intc>;
175 interrupt-parent = <&intc>;
188 interrupt-parent = <&intc>;
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| D | x1830.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
81 interrupt-parent = <&intc>;
97 interrupt-parent = <&intc>;
121 interrupt-parent = <&intc>;
136 interrupt-parent = <&intc>;
151 interrupt-parent = <&intc>;
166 interrupt-parent = <&intc>;
175 interrupt-parent = <&intc>;
188 interrupt-parent = <&intc>;
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| /kernel/linux/linux-5.10/arch/arc/boot/dts/ |
| D | axc003_idu.dtsi | 7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
45 core_intc: archs-intc@cpu {
46 compatible = "snps,archs-intc";
52 compatible = "snps,archs-idu-intc";
60 * to uplink only 1 IRQ to ARC core intc
127 * This INTC is actually connected to DW APB GPIO
128 * which acts as a wire between MB INTC and CPU INTC.
129 * GPIO INTC is configured in platform init code
130 * and here we mimic direct connection from MB INTC to
131 * CPU INTC, thus we set "interrupts = <0 1>" instead of
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| D | axc001.dtsi | 37 core_intc: arc700-intc@cpu {
38 compatible = "snps,arc700-intc";
45 * to uplink only 1 IRQ to ARC core intc
83 * This INTC is actually connected to DW APB GPIO
84 * which acts as a wire between MB INTC and CPU INTC.
85 * GPIO INTC is configured in platform init code
86 * and here we mimic direct connection from MB INTC to
87 * CPU INTC, thus we set "interrupts = <7>" instead of
90 * This intc actually resides on MB, but we move it here to
92 * this intc to cpu intc are different for axs101 and axs103
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