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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dclock-bindings.txt1 This binding is a work-in-progress, and are based on some experimental
10 value of a #clock-cells property in the clock provider node.
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
22 clock-output-names: Recommended to be a list of strings of clock output signal
24 However, the meaning of clock-output-names is domain
33 the provider's clock-output-names property.
38 #clock-cells = <1>;
39 clock-output-names = "ckil", "ckih";
42 - this node defines a device with two clock outputs, the first named
44 clocks by index. The names should reflect the clock output signal
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Dqcom,gcc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-sm8250.h
22 const: qcom,gcc-sm8250
24 clocks:
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Dqcom,gcc-sc7180.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-sc7180.h
22 const: qcom,gcc-sc7180
24 clocks:
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Dqcom,gcc-sm8150.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-sm8150.h
22 const: qcom,gcc-sm8150
24 clocks:
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Dqcom,gcc-msm8998.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-msm8998.h
22 const: qcom,gcc-msm8998
24 clocks:
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Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <jhugo@codeaurora.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm multimedia clock control module which supports the clocks, resets and
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8660
23 - qcom,mmcc-msm8960
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Dqcom,gcc-msm8996.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-msm8996.h
22 const: qcom,gcc-msm8996
24 clocks:
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Dqcom,gcc-qcs404.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-qcs404.h
22 const: qcom,gcc-qcs404
24 '#clock-cells':
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Dqcom,gcc-ipq8074.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-ipq8074.h
22 const: qcom,gcc-ipq8074
24 '#clock-cells':
[all …]
Dqcom,gcc-apq8064.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-msm8960.h
19 - dt-bindings/reset/qcom,gcc-msm8960.h
23 const: qcom,gcc-apq8064
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Dqcom,gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-apq8084.h
19 - dt-bindings/reset/qcom,gcc-apq8084.h
20 - dt-bindings/clock/qcom,gcc-ipq4019.h
21 - dt-bindings/clock/qcom,gcc-ipq6018.h
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/kernel/linux/linux-5.10/drivers/clk/qcom/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/reset-controller.h>
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
32 if (!f->freq) in qcom_find_freq()
35 for (; f->freq; f++) in qcom_find_freq()
36 if (rate <= f->freq) in qcom_find_freq()
40 return f - 1; in qcom_find_freq()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/
Drenesas,sysc-rmobile.txt1 DT bindings for the Renesas R-Mobile System Controller
5 The R-Mobile System Controller provides the following functions:
6 - Boot mode management,
7 - Reset generation,
8 - Power management.
11 - compatible: Should be "renesas,sysc-<soctype>", "renesas,sysc-rmobile" as
14 - "renesas,sysc-r8a73a4" (R-Mobile APE6)
15 - "renesas,sysc-r8a7740" (R-Mobile A1)
16 - "renesas,sysc-sh73a0" (SH-Mobile AG5)
17 - reg: Two address start and address range blocks for the device:
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/kernel/linux/linux-5.10/sound/pci/echoaudio/
Dechoaudio.h3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
34 +-----------+
35 record | |<-------------------- Inputs
36 <-------| | |
39 ------->| | +-------+
40 play | |--->|monitor|-------> Outputs
41 +-----------+ | mixer |
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dqcs404-evb.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 stdout-path = "serial0";
20 vph_pwr: vph-pwr-regulator {
21 compatible = "regulator-fixed";
22 regulator-name = "vph_pwr";
23 regulator-always-on;
24 regulator-boot-on;
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Dsdm850-lenovo-yoga-c630.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include <dt-bindings/sound/qcom,q6afe.h>
13 #include <dt-bindings/sound/qcom,q6asm.h>
19 compatible = "lenovo,yoga-c630", "qcom,sdm845";
27 firmware-name = "qcom/LENOVO/81JL/qcadsp850.mbn";
32 pm8998-rpmh-regulators {
33 compatible = "qcom,pm8998-rpmh-regulators";
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Dsdm845-xiaomi-beryllium.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
7 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
16 /delete-node/ &tz_mem;
17 /delete-node/ &adsp_mem;
18 /delete-node/ &wlan_msa_mem;
19 /delete-node/ &mpss_region;
20 /delete-node/ &venus_mem;
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Dsdm845-db845c.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/sound/qcom,q6afe.h>
12 #include <dt-bindings/sound/qcom,q6asm.h>
27 stdout-path = "serial0:115200n8";
30 dc12v: dc12v-regulator {
31 compatible = "regulator-fixed";
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/kernel/linux/linux-5.10/Documentation/driver-api/
Dclk.rst22 clk which unifies the framework-level accounting and infrastructure that
28 The second half of the interface is comprised of the hardware-specific
30 hardware-specific structures needed to model a particular clock. For
32 clk_ops, such as .enable or .set_rate, implies the hardware-specific
35 hardware-specific bits for the hypothetical "foo" hardware.
62 api itself defines several driver-facing functions which operate on
66 clk_ops pointer in struct clk_core to perform the hardware-specific parts of
67 the operations defined in clk-provider.h::
107 which abstract the details of struct clk from the hardware-specific bits, and
109 drivers/clk/clk-gate.c::
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/kernel/linux/linux-5.10/include/drm/
Ddrm_connector.h50 DRM_FORCE_ON_DIGITAL, /* for DVI-I use digital connector */
54 * enum drm_connector_status - status for a &drm_connector
69 * nothing there. It is driver-dependent whether a connector with this
76 * flicker (like load-detection when the connector is in use), or when a
77 * hardware resource isn't available (like when load-detection needs a
87 * enum drm_connector_registration_status - userspace registration status for
120 * - An unregistered connector may only have its DPMS changed from
121 * On->Off. Once DPMS is changed to Off, it may not be switched back
123 * - Modesets are not allowed on unregistered connectors, unless they
127 * - Removing a CRTC from an unregistered connector is OK, but new
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/kernel/linux/linux-5.10/drivers/clk/
Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
113 if (!core->rpm_enabled) in clk_pm_runtime_get()
116 ret = pm_runtime_get_sync(core->dev); in clk_pm_runtime_get()
118 pm_runtime_put_noidle(core->dev); in clk_pm_runtime_get()
126 if (!core->rpm_enabled) in clk_pm_runtime_put()
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Dclk-stm32h7.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/stm32h7-clks.h>
139 /* Micro-controller output clock parent */
178 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_enable()
183 } while (bit_status && --timeout); in ready_gate_clk_enable()
201 bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_disable()
206 } while (bit_status && --timeout); in ready_gate_clk_disable()
227 return ERR_PTR(-ENOMEM); in clk_register_ready_gate()
235 rgate->bit_rdy = bit_rdy; in clk_register_ready_gate()
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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dradeon.h32 * - surface allocator & initializer : (bit like scratch reg) should
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
69 #include <linux/dma-fence.h>
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
Da2xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0
15 struct msm_drm_private *priv = gpu->dev->dev_private; in a2xx_submit()
16 struct msm_ringbuffer *ring = submit->ring; in a2xx_submit()
19 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
20 switch (submit->cmd[i].type) { in a2xx_submit()
22 /* ignore IB-targets */ in a2xx_submit()
26 if (priv->lastctx == submit->queue->ctx) in a2xx_submit()
31 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a2xx_submit()
32 OUT_RING(ring, submit->cmd[i].size); in a2xx_submit()
39 OUT_RING(ring, submit->seqno); in a2xx_submit()
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/kernel/linux/linux-5.10/include/linux/
Dti_wilink_st.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * and also serves the sub-modules of the shared transport driver.
8 * Copyright (C) 2009-2010 Texas Instruments
18 * enum proto-type - The protocol on WiLink chips which share a
29 * struct st_proto_s - Per Protocol structure from BT/FM/GPS to ST
94 * struct st_data_s - ST core internal structure
104 * This needs to be protected, hence the lock inside wakeup func.
152 * wrapper around tty->ops->write_room to check
157 * st_int_write -
158 * point this to tty->driver->write or tty->ops->write
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