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/kernel/linux/linux-5.10/drivers/pwm/
DKconfig2 menuconfig PWM config
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
14 This framework provides a generic interface to PWM devices
16 to register and unregister a PWM chip, an abstraction of a PWM
17 controller, that supports one or more PWM devices. Client
18 drivers can request PWM devices and use the generic framework
21 This generic framework replaces the legacy PWM framework which
30 if PWM
37 bool "PWM lowlevel drivers additional checks and debug messages"
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Dcore.c11 #include <linux/pwm.h>
21 #include <dt-bindings/pwm/pwm.h>
24 #include <trace/events/pwm.h>
35 static struct pwm_device *pwm_to_device(unsigned int pwm) in pwm_to_device() argument
37 return radix_tree_lookup(&pwm_tree, pwm); in pwm_to_device()
40 static int alloc_pwms(int pwm, unsigned int count) in alloc_pwms() argument
45 if (pwm >= MAX_PWMS) in alloc_pwms()
48 if (pwm >= 0) in alloc_pwms()
49 from = pwm; in alloc_pwms()
54 if (pwm >= 0 && start != pwm) in alloc_pwms()
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DMakefile4 obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
5 obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
6 obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
7 obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
8 obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o
9 obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
10 obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o
11 obj-$(CONFIG_PWM_BERLIN) += pwm-berlin.o
12 obj-$(CONFIG_PWM_BRCMSTB) += pwm-brcmstb.o
13 obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o
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Dpwm-renesas-tpu.c3 * R-Mobile TPU PWM driver
18 #include <linux/pwm.h>
63 TPU_PIN_PWM, /* Pin is driven by PWM */
92 static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value) in tpu_pwm_write() argument
94 void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET in tpu_pwm_write()
95 + pwm->channel * TPU_CHANNEL_SIZE; in tpu_pwm_write()
100 static void tpu_pwm_set_pin(struct tpu_pwm_device *pwm, in tpu_pwm_set_pin() argument
103 static const char * const states[] = { "inactive", "PWM", "active" }; in tpu_pwm_set_pin()
105 dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n", in tpu_pwm_set_pin()
106 pwm->channel, states[state]); in tpu_pwm_set_pin()
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Dpwm-berlin.c2 * Marvell Berlin PWM driver
18 #include <linux/pwm.h>
72 static int berlin_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in berlin_pwm_request() argument
80 return pwm_set_chip_data(pwm, channel); in berlin_pwm_request()
83 static void berlin_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) in berlin_pwm_free() argument
85 struct berlin_pwm_channel *channel = pwm_get_chip_data(pwm); in berlin_pwm_free()
93 struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip); in berlin_pwm_config() local
98 cycles = clk_get_rate(pwm->clk); in berlin_pwm_config()
115 value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_config()
120 berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_config()
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Dpwm-pxa.c3 * drivers/pwm/pwm-pxa.c
5 * simple driver for PWM (Pulse Width Modulator) controller
18 #include <linux/pwm.h>
26 /* PWM has_secondary_pwm? */
27 { "pxa25x-pwm", 0 },
28 { "pxa27x-pwm", HAS_SECONDARY_PWM },
29 { "pxa168-pwm", 0 },
30 { "pxa910-pwm", 0 },
35 /* PWM registers and bits definitions */
60 static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in pxa_pwm_config() argument
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Dpwm-tegra.c3 * drivers/pwm/pwm-tegra.c
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
28 * - When PWM is disabled, the output is driven to inactive.
29 * - It does not allow the current PWM period to complete and
32 * - If the register is reconfigured while PWM is running,
45 #include <linux/pwm.h>
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Dpwm-sun4i.c8 * - When outputing the source clock directly, the PWM logic will be bypassed
22 #include <linux/pwm.h>
113 struct pwm_device *pwm, in sun4i_pwm_get_state() argument
126 * PWM chapter in H6 manual has a diagram which explains that if bypass in sun4i_pwm_get_state()
130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
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Dpwm-twl.c12 #include <linux/pwm.h>
32 #define TWL4030_PWM_TOGGLE(pwm, x) ((x) << (pwm)) argument
46 #define TWL6030_PWM_TOGGLE(pwm, x) ((x) << (pwm * 3)) argument
60 static int twl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in twl_pwm_config() argument
76 * When on cycle == off cycle the PWM will be always on in twl_pwm_config()
83 base = pwm->hwpwm * 3; in twl_pwm_config()
89 dev_err(chip->dev, "%s: Failed to configure PWM\n", pwm->label); in twl_pwm_config()
94 static int twl4030_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in twl4030_pwm_enable() argument
103 dev_err(chip->dev, "%s: Failed to read GPBR1\n", pwm->label); in twl4030_pwm_enable()
107 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_enable()
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Dsysfs.c3 * A simple sysfs interface for the generic PWM framework
15 #include <linux/pwm.h>
19 struct pwm_device *pwm; member
33 return export->pwm; in child_to_pwm_device()
40 const struct pwm_device *pwm = child_to_pwm_device(child); in period_show() local
43 pwm_get_state(pwm, &state); in period_show()
53 struct pwm_device *pwm = export->pwm; in period_store() local
63 pwm_get_state(pwm, &state); in period_store()
65 ret = pwm_apply_state(pwm, &state); in period_store()
75 const struct pwm_device *pwm = child_to_pwm_device(child); in duty_cycle_show() local
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Dpwm-stmpe.c15 #include <linux/pwm.h>
39 static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in stmpe_24xx_pwm_enable() argument
47 dev_err(chip->dev, "error reading PWM#%u control\n", in stmpe_24xx_pwm_enable()
48 pwm->hwpwm); in stmpe_24xx_pwm_enable()
52 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable()
56 dev_err(chip->dev, "error writing PWM#%u control\n", in stmpe_24xx_pwm_enable()
57 pwm->hwpwm); in stmpe_24xx_pwm_enable()
65 struct pwm_device *pwm) in stmpe_24xx_pwm_disable() argument
73 dev_err(chip->dev, "error reading PWM#%u control\n", in stmpe_24xx_pwm_disable()
74 pwm->hwpwm); in stmpe_24xx_pwm_disable()
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Dpwm-lpss.c3 * Intel Low Power Subsystem PWM controller driver
21 #include "pwm-lpss.h"
23 #define PWM 0x00000000 macro
29 /* Size of each PWM register space if multiple */
37 static inline u32 pwm_lpss_read(const struct pwm_device *pwm) in pwm_lpss_read() argument
39 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); in pwm_lpss_read()
41 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); in pwm_lpss_read()
44 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) in pwm_lpss_write() argument
46 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); in pwm_lpss_write()
48 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); in pwm_lpss_write()
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Dpwm-img.c7 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
19 #include <linux/pwm.h>
23 /* PWM registers */
43 * PWM period is specified with a timebase register,
44 * in number of step periods. The PWM duty cycle is also
49 * Imposing a minimum timebase, will impose a maximum PWM frequency.
92 static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in img_pwm_config() argument
138 val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm)); in img_pwm_config()
140 PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm); in img_pwm_config()
145 img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val); in img_pwm_config()
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/kernel/linux/linux-5.10/include/linux/
Dpwm.h15 * enum pwm_polarity - polarity of a PWM signal
29 * struct pwm_args - board-dependent PWM arguments
33 * This structure describes board-dependent arguments attached to a PWM
34 * device. These arguments are usually retrieved from the PWM lookup table or
37 * Do not confuse this with the PWM state: PWM arguments represent the initial
38 * configuration that users want to use on this PWM device rather than the
39 * current PWM hardware state.
52 * struct pwm_state - state of a PWM channel
53 * @period: PWM period (in nanoseconds)
54 * @duty_cycle: PWM duty cycle (in nanoseconds)
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
18 An optional property "pwm-names" may contain a list of strings to label
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Dpwm-samsung.yaml4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
7 title: Samsung SoC PWM timers
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
24 - samsung,s3c2410-pwm # 16-bit, S3C24xx
25 - samsung,s3c6400-pwm # 32-bit, S3C64xx
26 - samsung,s5p6440-pwm # 32-bit, S5P64x0
27 - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs
28 - samsung,exynos4210-pwm # 32-bit, Exynos
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Drenesas,pwm-rcar.yaml4 $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
7 title: Renesas R-Car PWM Timer Controller
16 - renesas,pwm-r8a7742 # RZ/G1H
17 - renesas,pwm-r8a7743 # RZ/G1M
18 - renesas,pwm-r8a7744 # RZ/G1N
19 - renesas,pwm-r8a7745 # RZ/G1E
20 - renesas,pwm-r8a77470 # RZ/G1C
21 - renesas,pwm-r8a774a1 # RZ/G2M
22 - renesas,pwm-r8a774b1 # RZ/G2N
23 - renesas,pwm-r8a774c0 # RZ/G2E
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Dimx-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
7 title: Freescale i.MX PWM controller
13 "#pwm-cells":
15 Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
24 - fsl,imx1-pwm
25 - fsl,imx27-pwm
28 - fsl,imx25-pwm
29 - fsl,imx31-pwm
30 - fsl,imx50-pwm
31 - fsl,imx51-pwm
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Dallwinner,sun4i-a10-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
7 title: Allwinner A10 PWM Device Tree Bindings
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
21 - const: allwinner,sun5i-a13-pwm
22 - const: allwinner,sun7i-a20-pwm
23 - const: allwinner,sun8i-h3-pwm
25 - const: allwinner,sun8i-a83t-pwm
26 - const: allwinner,sun8i-h3-pwm
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Dnvidia,tegra20-pwm.txt5 - "nvidia,tegra20-pwm": for Tegra20
6 - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
7 - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
8 - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
9 - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
10 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
11 - "nvidia,tegra186-pwm": for Tegra186
12 - "nvidia,tegra194-pwm": for Tegra194
14 - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
21 - pwm
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Dpwm-sifive.yaml5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
16 Unlike most other PWM controllers, the SiFive PWM controller currently
17 only supports one period for all channels in the PWM. All PWMs need to
20 achievable period. PWM RTL that corresponds to the IP block version
23 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
28 - const: sifive,fu540-c000-pwm
31 Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
32 compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
34 SiFive PWM v0 IP block with no chip integration tweaks.
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Dpwm-mediatek.txt1 MediaTek PWM controller
4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt7622-pwm": found on mt7622 SoC.
7 - "mediatek,mt7623-pwm": found on mt7623 SoC.
8 - "mediatek,mt7628-pwm": found on mt7628 SoC.
9 - "mediatek,mt7629-pwm": found on mt7629 SoC.
10 - "mediatek,mt8516-pwm": found on mt8516 SoC.
12 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
14 - clocks: phandle and clock specifier of the PWM reference clock.
[all …]
/kernel/linux/linux-5.10/drivers/clocksource/
Dsamsung_pwm_timer.c80 static struct samsung_pwm_clocksource pwm; variable
93 reg = readl(pwm.base + REG_TCFG0); in samsung_timer_set_prescale()
96 writel(reg, pwm.base + REG_TCFG0); in samsung_timer_set_prescale()
108 bits = (fls(divisor) - 1) - pwm.variant.div_base; in samsung_timer_set_divisor()
112 reg = readl(pwm.base + REG_TCFG1); in samsung_timer_set_divisor()
115 writel(reg, pwm.base + REG_TCFG1); in samsung_timer_set_divisor()
130 tcon = readl_relaxed(pwm.base + REG_TCON); in samsung_time_stop()
132 writel_relaxed(tcon, pwm.base + REG_TCON); in samsung_time_stop()
148 tcon = readl_relaxed(pwm.base + REG_TCON); in samsung_time_setup()
153 writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel)); in samsung_time_setup()
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/kernel/linux/linux-5.10/Documentation/driver-api/
Dpwm.rst2 Pulse Width Modulation (PWM) interface
5 This provides an overview about the Linux PWM interface
9 the Linux PWM API (although they could). However, PWMs are often
12 this kind of flexibility the generic PWM API exists.
17 Users of the legacy PWM API use unique IDs to refer to PWM devices.
19 Instead of referring to a PWM device via its unique ID, board setup code
20 should instead register a static mapping that can be used to match PWM
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
38 Legacy users can request a PWM device using pwm_request() and free it
42 device or a consumer name. pwm_put() is used to free the PWM device. Managed
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/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-class-pwm1 What: /sys/class/pwm/
6 The pwm/ class sub-directory belongs to the Generic PWM
7 Framework and provides a sysfs interface for using PWM
10 What: /sys/class/pwm/pwmchipN/
15 A /sys/class/pwm/pwmchipN directory is created for each
16 probed PWM controller/chip where N is the base of the
17 PWM chip.
19 What: /sys/class/pwm/pwmchipN/npwm
24 The number of PWM channels supported by the PWM chip.
26 What: /sys/class/pwm/pwmchipN/export
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