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Searched refs:CLK_TOP_MUX_MSDC30_1 (Results 1 – 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dmt6797-clk.h28 #define CLK_TOP_MUX_MSDC30_1 18 macro
Dmt8183-clk.h45 #define CLK_TOP_MUX_MSDC30_1 9 macro
/kernel/linux/linux-5.10/drivers/clk/mediatek/
Dclk-mt6797.c349 MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
Dclk-mt8183.c583 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt8183-kukui.dtsi323 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
Dmt8183.dtsi716 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,