1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 }; 17 18 chosen { 19 stdout-path = "serial0:115200n8"; 20 }; 21 22 memory@40000000 { 23 device_type = "memory"; 24 reg = <0 0x40000000 0 0x80000000>; 25 }; 26 27 clk32k: oscillator1 { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32768>; 31 clock-output-names = "clk32k"; 32 }; 33 34 it6505_pp18_reg: regulator0 { 35 compatible = "regulator-fixed"; 36 regulator-name = "it6505_pp18"; 37 regulator-min-microvolt = <1800000>; 38 regulator-max-microvolt = <1800000>; 39 gpio = <&pio 178 0>; 40 enable-active-high; 41 }; 42 43 lcd_pp3300: regulator1 { 44 compatible = "regulator-fixed"; 45 regulator-name = "lcd_pp3300"; 46 regulator-min-microvolt = <3300000>; 47 regulator-max-microvolt = <3300000>; 48 regulator-always-on; 49 regulator-boot-on; 50 }; 51 52 bl_pp5000: regulator2 { 53 compatible = "regulator-fixed"; 54 regulator-name = "bl_pp5000"; 55 regulator-min-microvolt = <5000000>; 56 regulator-max-microvolt = <5000000>; 57 regulator-always-on; 58 regulator-boot-on; 59 }; 60 61 mmc1_fixed_power: regulator3 { 62 compatible = "regulator-fixed"; 63 regulator-name = "mmc1_power"; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 }; 67 68 mmc1_fixed_io: regulator4 { 69 compatible = "regulator-fixed"; 70 regulator-name = "mmc1_io"; 71 regulator-min-microvolt = <1800000>; 72 regulator-max-microvolt = <1800000>; 73 }; 74 75 pp1800_alw: regulator5 { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_alw"; 78 regulator-always-on; 79 regulator-boot-on; 80 regulator-min-microvolt = <1800000>; 81 regulator-max-microvolt = <1800000>; 82 }; 83 84 pp3300_alw: regulator6 { 85 compatible = "regulator-fixed"; 86 regulator-name = "pp3300_alw"; 87 regulator-always-on; 88 regulator-boot-on; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 }; 92 93 reserved_memory: reserved-memory { 94 #address-cells = <2>; 95 #size-cells = <2>; 96 ranges; 97 98 scp_mem_reserved: scp_mem_region { 99 compatible = "shared-dma-pool"; 100 reg = <0 0x50000000 0 0x2900000>; 101 no-map; 102 }; 103 }; 104 105 max98357a: codec0 { 106 compatible = "maxim,max98357a"; 107 sdmode-gpios = <&pio 175 0>; 108 }; 109 110 btsco: codec1 { 111 compatible = "linux,bt-sco"; 112 }; 113 114 wifi_pwrseq: wifi-pwrseq { 115 compatible = "mmc-pwrseq-simple"; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&wifi_pins_pwrseq>; 118 119 /* Toggle WIFI_ENABLE to reset the chip. */ 120 reset-gpios = <&pio 119 1>; 121 }; 122 123 wifi_wakeup: wifi-wakeup { 124 compatible = "gpio-keys"; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&wifi_pins_wakeup>; 127 128 wowlan { 129 label = "Wake on WiFi"; 130 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 131 linux,code = <KEY_WAKEUP>; 132 wakeup-source; 133 }; 134 }; 135 136 tboard_thermistor1: thermal-sensor1 { 137 compatible = "generic-adc-thermal"; 138 #thermal-sensor-cells = <0>; 139 io-channels = <&auxadc 0>; 140 io-channel-names = "sensor-channel"; 141 temperature-lookup-table = < (-5000) 4241 142 0 4063 143 5000 3856 144 10000 3621 145 15000 3364 146 20000 3091 147 25000 2810 148 30000 2526 149 35000 2247 150 40000 1982 151 45000 1734 152 50000 1507 153 55000 1305 154 60000 1122 155 65000 964 156 70000 827 157 75000 710 158 80000 606 159 85000 519 160 90000 445 161 95000 382 162 100000 330 163 105000 284 164 110000 245 165 115000 213 166 120000 183 167 125000 161>; 168 }; 169 170 tboard_thermistor2: thermal-sensor2 { 171 compatible = "generic-adc-thermal"; 172 #thermal-sensor-cells = <0>; 173 io-channels = <&auxadc 1>; 174 io-channel-names = "sensor-channel"; 175 temperature-lookup-table = < (-5000) 4241 176 0 4063 177 5000 3856 178 10000 3621 179 15000 3364 180 20000 3091 181 25000 2810 182 30000 2526 183 35000 2247 184 40000 1982 185 45000 1734 186 50000 1507 187 55000 1305 188 60000 1122 189 65000 964 190 70000 827 191 75000 710 192 80000 606 193 85000 519 194 90000 445 195 95000 382 196 100000 330 197 105000 284 198 110000 245 199 115000 213 200 120000 183 201 125000 161>; 202 }; 203}; 204 205&auxadc { 206 status = "okay"; 207}; 208 209&cpu0 { 210 proc-supply = <&mt6358_vproc12_reg>; 211}; 212 213&cpu1 { 214 proc-supply = <&mt6358_vproc12_reg>; 215}; 216 217&cpu2 { 218 proc-supply = <&mt6358_vproc12_reg>; 219}; 220 221&cpu3 { 222 proc-supply = <&mt6358_vproc12_reg>; 223}; 224 225&cpu4 { 226 proc-supply = <&mt6358_vproc11_reg>; 227}; 228 229&cpu5 { 230 proc-supply = <&mt6358_vproc11_reg>; 231}; 232 233&cpu6 { 234 proc-supply = <&mt6358_vproc11_reg>; 235}; 236 237&cpu7 { 238 proc-supply = <&mt6358_vproc11_reg>; 239}; 240 241&i2c0 { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&i2c0_pins>; 244 status = "okay"; 245 clock-frequency = <400000>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248}; 249 250&i2c1 { 251 pinctrl-names = "default"; 252 pinctrl-0 = <&i2c1_pins>; 253 status = "okay"; 254 clock-frequency = <100000>; 255}; 256 257&i2c3 { 258 pinctrl-names = "default"; 259 pinctrl-0 = <&i2c3_pins>; 260 status = "okay"; 261 clock-frequency = <100000>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264}; 265 266&i2c5 { 267 pinctrl-names = "default"; 268 pinctrl-0 = <&i2c5_pins>; 269 status = "okay"; 270 clock-frequency = <100000>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273}; 274 275&i2c6 { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&i2c6_pins>; 278 status = "okay"; 279 clock-frequency = <100000>; 280}; 281 282&mmc0 { 283 status = "okay"; 284 pinctrl-names = "default", "state_uhs"; 285 pinctrl-0 = <&mmc0_pins_default>; 286 pinctrl-1 = <&mmc0_pins_uhs>; 287 bus-width = <8>; 288 max-frequency = <200000000>; 289 cap-mmc-highspeed; 290 mmc-hs200-1_8v; 291 mmc-hs400-1_8v; 292 cap-mmc-hw-reset; 293 no-sdio; 294 no-sd; 295 hs400-ds-delay = <0x12814>; 296 vmmc-supply = <&mt6358_vemc_reg>; 297 vqmmc-supply = <&mt6358_vio18_reg>; 298 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 299 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 300 non-removable; 301}; 302 303&mmc1 { 304 status = "okay"; 305 pinctrl-names = "default", "state_uhs"; 306 pinctrl-0 = <&mmc1_pins_default>; 307 pinctrl-1 = <&mmc1_pins_uhs>; 308 vmmc-supply = <&mmc1_fixed_power>; 309 vqmmc-supply = <&mmc1_fixed_io>; 310 mmc-pwrseq = <&wifi_pwrseq>; 311 bus-width = <4>; 312 max-frequency = <200000000>; 313 drv-type = <2>; 314 cap-sd-highspeed; 315 sd-uhs-sdr50; 316 sd-uhs-sdr104; 317 keep-power-in-suspend; 318 enable-sdio-wakeup; 319 cap-sdio-irq; 320 non-removable; 321 no-mmc; 322 no-sd; 323 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 324 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 328 qca_wifi: qca-wifi@1 { 329 compatible = "qcom,ath10k"; 330 reg = <1>; 331 }; 332}; 333 334&mt6358_vdram2_reg { 335 regulator-always-on; 336}; 337 338&mt6358codec { 339 Avdd-supply = <&mt6358_vaud28_reg>; 340}; 341 342&mt6358_vsim1_reg { 343 regulator-min-microvolt = <2700000>; 344 regulator-max-microvolt = <2700000>; 345}; 346 347&mt6358_vsim2_reg { 348 regulator-min-microvolt = <2700000>; 349 regulator-max-microvolt = <2700000>; 350}; 351 352&pio { 353 bt_pins: bt-pins { 354 pins_bt_en { 355 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 356 output-low; 357 }; 358 }; 359 360 ec_ap_int_odl: ec_ap_int_odl { 361 pins1 { 362 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 363 input-enable; 364 bias-pull-up; 365 }; 366 }; 367 368 h1_int_od_l: h1_int_od_l { 369 pins1 { 370 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 371 input-enable; 372 }; 373 }; 374 375 i2c0_pins: i2c0 { 376 pins_bus { 377 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 378 <PINMUX_GPIO83__FUNC_SCL0>; 379 mediatek,pull-up-adv = <3>; 380 mediatek,drive-strength-adv = <00>; 381 }; 382 }; 383 384 i2c1_pins: i2c1 { 385 pins_bus { 386 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 387 <PINMUX_GPIO84__FUNC_SCL1>; 388 mediatek,pull-up-adv = <3>; 389 mediatek,drive-strength-adv = <00>; 390 }; 391 }; 392 393 i2c2_pins: i2c2 { 394 pins_bus { 395 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 396 <PINMUX_GPIO104__FUNC_SDA2>; 397 bias-disable; 398 mediatek,drive-strength-adv = <00>; 399 }; 400 }; 401 402 i2c3_pins: i2c3 { 403 pins_bus { 404 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 405 <PINMUX_GPIO51__FUNC_SDA3>; 406 mediatek,pull-up-adv = <3>; 407 mediatek,drive-strength-adv = <00>; 408 }; 409 }; 410 411 i2c4_pins: i2c4 { 412 pins_bus { 413 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 414 <PINMUX_GPIO106__FUNC_SDA4>; 415 bias-disable; 416 mediatek,drive-strength-adv = <00>; 417 }; 418 }; 419 420 i2c5_pins: i2c5 { 421 pins_bus { 422 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 423 <PINMUX_GPIO49__FUNC_SDA5>; 424 mediatek,pull-up-adv = <3>; 425 mediatek,drive-strength-adv = <00>; 426 }; 427 }; 428 429 i2c6_pins: i2c6 { 430 pins_bus { 431 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 432 <PINMUX_GPIO12__FUNC_SDA6>; 433 bias-disable; 434 }; 435 }; 436 437 mmc0_pins_default: mmc0-pins-default { 438 pins_cmd_dat { 439 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 440 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 441 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 442 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 443 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 444 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 445 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 446 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 447 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 448 input-enable; 449 drive-strength = <MTK_DRIVE_14mA>; 450 mediatek,pull-up-adv = <01>; 451 }; 452 453 pins_clk { 454 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 455 drive-strength = <MTK_DRIVE_14mA>; 456 mediatek,pull-down-adv = <10>; 457 }; 458 459 pins_rst { 460 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 461 drive-strength = <MTK_DRIVE_14mA>; 462 mediatek,pull-down-adv = <01>; 463 }; 464 }; 465 466 mmc0_pins_uhs: mmc0-pins-uhs { 467 pins_cmd_dat { 468 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 469 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 470 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 471 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 472 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 473 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 474 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 475 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 476 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 477 input-enable; 478 drive-strength = <MTK_DRIVE_14mA>; 479 mediatek,pull-up-adv = <01>; 480 }; 481 482 pins_clk { 483 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 484 drive-strength = <MTK_DRIVE_14mA>; 485 mediatek,pull-down-adv = <10>; 486 }; 487 488 pins_ds { 489 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 490 drive-strength = <MTK_DRIVE_14mA>; 491 mediatek,pull-down-adv = <10>; 492 }; 493 494 pins_rst { 495 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 496 drive-strength = <MTK_DRIVE_14mA>; 497 mediatek,pull-up-adv = <01>; 498 }; 499 }; 500 501 mmc1_pins_default: mmc1-pins-default { 502 pins_cmd_dat { 503 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 504 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 505 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 506 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 507 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 508 input-enable; 509 mediatek,pull-up-adv = <10>; 510 }; 511 512 pins_clk { 513 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 514 input-enable; 515 mediatek,pull-down-adv = <10>; 516 }; 517 }; 518 519 mmc1_pins_uhs: mmc1-pins-uhs { 520 pins_cmd_dat { 521 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 522 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 523 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 524 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 525 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 526 drive-strength = <MTK_DRIVE_6mA>; 527 input-enable; 528 mediatek,pull-up-adv = <10>; 529 }; 530 531 pins_clk { 532 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 533 drive-strength = <MTK_DRIVE_8mA>; 534 mediatek,pull-down-adv = <10>; 535 input-enable; 536 }; 537 }; 538 539 scp_pins: scp { 540 pins_scp_uart { 541 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 542 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 543 }; 544 }; 545 546 spi0_pins: spi0 { 547 pins_spi{ 548 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 549 <PINMUX_GPIO86__FUNC_GPIO86>, 550 <PINMUX_GPIO87__FUNC_SPI0_MO>, 551 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 552 bias-disable; 553 }; 554 }; 555 556 spi1_pins: spi1 { 557 pins_spi{ 558 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 559 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 560 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 561 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 562 bias-disable; 563 }; 564 }; 565 566 spi2_pins: spi2 { 567 pins_spi{ 568 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 569 <PINMUX_GPIO1__FUNC_SPI2_MO>, 570 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 571 bias-disable; 572 }; 573 pins_spi_mi { 574 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 575 mediatek,pull-down-adv = <00>; 576 }; 577 }; 578 579 spi3_pins: spi3 { 580 pins_spi{ 581 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 582 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 583 <PINMUX_GPIO23__FUNC_SPI3_MO>, 584 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 585 bias-disable; 586 }; 587 }; 588 589 spi4_pins: spi4 { 590 pins_spi{ 591 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 592 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 593 <PINMUX_GPIO19__FUNC_SPI4_MO>, 594 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 595 bias-disable; 596 }; 597 }; 598 599 spi5_pins: spi5 { 600 pins_spi{ 601 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 602 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 603 <PINMUX_GPIO15__FUNC_SPI5_MO>, 604 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 605 bias-disable; 606 }; 607 }; 608 609 uart0_pins_default: uart0-pins-default { 610 pins_rx { 611 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 612 input-enable; 613 bias-pull-up; 614 }; 615 pins_tx { 616 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 617 }; 618 }; 619 620 uart1_pins_default: uart1-pins-default { 621 pins_rx { 622 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 623 input-enable; 624 bias-pull-up; 625 }; 626 pins_tx { 627 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 628 }; 629 pins_rts { 630 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 631 output-enable; 632 }; 633 pins_cts { 634 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 635 input-enable; 636 }; 637 }; 638 639 uart1_pins_sleep: uart1-pins-sleep { 640 pins_rx { 641 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 642 input-enable; 643 bias-pull-up; 644 }; 645 pins_tx { 646 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 647 }; 648 pins_rts { 649 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 650 output-enable; 651 }; 652 pins_cts { 653 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 654 input-enable; 655 }; 656 }; 657 658 wifi_pins_pwrseq: wifi-pins-pwrseq { 659 pins_wifi_enable { 660 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 661 output-low; 662 }; 663 }; 664 665 wifi_pins_wakeup: wifi-pins-wakeup { 666 pins_wifi_wakeup { 667 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 668 input-enable; 669 }; 670 }; 671}; 672 673&scp { 674 status = "okay"; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&scp_pins>; 677 678 cros_ec { 679 compatible = "google,cros-ec-rpmsg"; 680 mtk,rpmsg-name = "cros-ec-rpmsg"; 681 }; 682}; 683 684&soc_data { 685 status = "okay"; 686}; 687 688&spi0 { 689 pinctrl-names = "default"; 690 pinctrl-0 = <&spi0_pins>; 691 mediatek,pad-select = <0>; 692 status = "okay"; 693 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 694 695 cr50@0 { 696 compatible = "google,cr50"; 697 reg = <0>; 698 spi-max-frequency = <1000000>; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&h1_int_od_l>; 701 interrupt-parent = <&pio>; 702 interrupts = <153 IRQ_TYPE_EDGE_RISING>; 703 }; 704}; 705 706&spi1 { 707 pinctrl-names = "default"; 708 pinctrl-0 = <&spi1_pins>; 709 mediatek,pad-select = <0>; 710 status = "okay"; 711 712 w25q64dw: spi-flash@0 { 713 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 714 reg = <0>; 715 spi-max-frequency = <25000000>; 716 }; 717}; 718 719&spi2 { 720 pinctrl-names = "default"; 721 pinctrl-0 = <&spi2_pins>; 722 mediatek,pad-select = <0>; 723 status = "okay"; 724 725 cros_ec: cros-ec@0 { 726 compatible = "google,cros-ec-spi"; 727 reg = <0>; 728 spi-max-frequency = <3000000>; 729 interrupt-parent = <&pio>; 730 interrupts = <151 IRQ_TYPE_LEVEL_LOW>; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&ec_ap_int_odl>; 733 734 i2c_tunnel: i2c-tunnel { 735 compatible = "google,cros-ec-i2c-tunnel"; 736 google,remote-bus = <1>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 }; 740 741 usbc_extcon: extcon0 { 742 compatible = "google,extcon-usbc-cros-ec"; 743 google,usb-port-id = <0>; 744 }; 745 }; 746}; 747 748&spi3 { 749 pinctrl-names = "default"; 750 pinctrl-0 = <&spi3_pins>; 751 mediatek,pad-select = <0>; 752 status = "disabled"; 753}; 754 755&spi4 { 756 pinctrl-names = "default"; 757 pinctrl-0 = <&spi4_pins>; 758 mediatek,pad-select = <0>; 759 status = "disabled"; 760}; 761 762&spi5 { 763 pinctrl-names = "default"; 764 pinctrl-0 = <&spi5_pins>; 765 mediatek,pad-select = <0>; 766 status = "disabled"; 767}; 768 769&ssusb { 770 dr_mode = "host"; 771 wakeup-source; 772 vusb33-supply = <&mt6358_vusb_reg>; 773 status = "okay"; 774}; 775 776&u3phy { 777 status = "okay"; 778}; 779 780&uart0 { 781 pinctrl-names = "default"; 782 pinctrl-0 = <&uart0_pins_default>; 783 status = "okay"; 784}; 785 786&uart1 { 787 pinctrl-names = "default", "sleep"; 788 pinctrl-0 = <&uart1_pins_default>; 789 pinctrl-1 = <&uart1_pins_sleep>; 790 status = "okay"; 791 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 792 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 793 794 bluetooth: bluetooth { 795 pinctrl-names = "default"; 796 pinctrl-0 = <&bt_pins>; 797 status = "okay"; 798 compatible = "qcom,qca6174-bt"; 799 enable-gpios = <&pio 120 0>; 800 clocks = <&clk32k>; 801 firmware-name = "nvm_00440302_i2s.bin"; 802 }; 803}; 804 805&usb_host { 806 #address-cells = <1>; 807 #size-cells = <0>; 808 vusb33-supply = <&mt6358_vusb_reg>; 809 status = "okay"; 810 811 hub@1 { 812 compatible = "usb5e3,610"; 813 reg = <1>; 814 }; 815}; 816 817#include <arm/cros-ec-keyboard.dtsi> 818#include <arm/cros-ec-sbs.dtsi> 819