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Searched refs:DSSERR (Results 1 – 25 of 39) sorted by relevance

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/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
Doverlay.c84 DSSERR("failed to create sysfs file\n"); in dss_init_overlays()
107 DSSERR("check_overlay: overlay %d doesn't support " in dss_ovl_simple_check()
113 DSSERR("check_overlay: overlay %d doesn't support " in dss_ovl_simple_check()
120 DSSERR("check_overlay: overlay %d doesn't support mode %d\n", in dss_ovl_simple_check()
126 DSSERR("check_overlay: zorder %d too high\n", info->zorder); in dss_ovl_simple_check()
131 DSSERR("check_overlay: rotation type %d not supported\n", in dss_ovl_simple_check()
164 DSSERR("overlay %d horizontally not inside the display area " in dss_ovl_check()
171 DSSERR("overlay %d vertically not inside the display area " in dss_ovl_check()
Ddispc-compat.c350 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n", in dispc_error_worker()
367 DSSERR("SYNC_LOST on channel %s, restarting the output " in dispc_error_worker()
387 DSSERR("OCP_ERR\n"); in dispc_error_worker()
439 DSSERR("dispc_request_irq failed\n"); in dss_dispc_initialize_irq()
481 DSSERR("failed to register FRAMEDONE isr\n"); in dispc_mgr_disable_lcd_out()
493 DSSERR("timeout waiting for FRAME DONE\n"); in dispc_mgr_disable_lcd_out()
498 DSSERR("failed to unregister FRAMEDONE isr\n"); in dispc_mgr_disable_lcd_out()
531 DSSERR("failed to register %x isr\n", irq_mask); in dispc_mgr_enable_digit_out()
539 DSSERR("timeout waiting for digit out to start\n"); in dispc_mgr_enable_digit_out()
544 DSSERR("failed to unregister %x isr\n", irq_mask); in dispc_mgr_enable_digit_out()
[all …]
Ddsi.c722 DSSERR("DSI error, irqstatus %x\n", irqstatus); in dsi_handle_irq_errors()
733 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", in dsi_handle_irq_errors()
742 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); in dsi_handle_irq_errors()
1170 DSSERR("can't get DSI VDD regulator\n"); in dsi_regulator_init()
1223 DSSERR("Failed to set dsi_if_enable to %d\n", enable); in dsi_if_enable()
1357 DSSERR("Failed to set DSI PLL power mode to %d\n", in dsi_pll_power()
1410 DSSERR("PLL not coming out of reset.\n"); in dsi_pll_enable()
1757 DSSERR("failed to set complexio power state to " in dsi_cio_power()
2031 DSSERR("CIO TXCLKESC%d domain not coming " \ in dsi_cio_wait_tx_clk_esc_reset()
2076 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); in dsi_cio_init()
[all …]
Dapply.c518 DSSERR("mgr(%d)->wait_for_go() not finishing\n", in dss_mgr_wait_for_go()
529 DSSERR("mgr(%d)->wait_for_go() timeout\n", mgr->id); in dss_mgr_wait_for_go()
595 DSSERR("ovl(%d)->wait_for_go() not finishing\n", in dss_mgr_wait_for_go_ovl()
606 DSSERR("ovl(%d)->wait_for_go() timeout\n", ovl->id); in dss_mgr_wait_for_go_ovl()
641 DSSERR("dispc_ovl_setup failed for ovl %d\n", ovl->id); in dss_ovl_write_regs()
742 DSSERR("cannot write registers for manager %s: " in dss_write_regs()
821 DSSERR("cannot start manual update: illegal configuration\n"); in dss_mgr_start_update_compat()
978 DSSERR("failed to apply settings: illegal configuration.\n"); in omap_dss_mgr_apply()
1081 DSSERR("failed to enable manager %d: check_settings failed\n", in dss_mgr_enable_compat()
1182 DSSERR("manager %s is already connected to an output\n", in dss_mgr_set_output()
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Dhdmi4.c102 DSSERR("can't get VDDA regulator\n"); in hdmi_init_regulator()
168 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
174 DSSERR("Failed to configure PLL\n"); in hdmi_power_on_full()
327 DSSERR("failed to enable display: no output/manager\n"); in hdmi_display_enable()
334 DSSERR("failed to power on device\n"); in hdmi_display_enable()
342 DSSERR("Error restoring audio configuration: %d", r); in hdmi_display_enable()
390 DSSERR("failed to power on device\n"); in hdmi_core_enable()
433 DSSERR("failed to connect output to new device: %s\n", in hdmi_connect()
704 DSSERR("platform_get_irq failed\n"); in hdmi4_bind()
713 DSSERR("HDMI IRQ request failed\n"); in hdmi4_bind()
[all …]
Dhdmi5.c119 DSSERR("can't get VDDA regulator\n"); in hdmi_init_regulator()
185 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
191 DSSERR("Failed to configure PLL\n"); in hdmi_power_on_full()
357 DSSERR("failed to enable display: no output/manager\n"); in hdmi_display_enable()
364 DSSERR("failed to power on device\n"); in hdmi_display_enable()
372 DSSERR("Error restoring audio configuration: %d", r); in hdmi_display_enable()
420 DSSERR("failed to power on device\n"); in hdmi_core_enable()
463 DSSERR("failed to connect output to new device: %s\n", in hdmi_connect()
745 DSSERR("platform_get_irq failed\n"); in hdmi5_bind()
754 DSSERR("HDMI IRQ request failed\n"); in hdmi5_bind()
[all …]
Dmanager.c81 DSSERR("failed to create sysfs file\n"); in dss_init_overlay_managers_sysfs()
131 DSSERR("check_manager: illegal transparency key\n"); in dss_mgr_simple_check()
161 DSSERR("overlays %d and %d have the same " in dss_mgr_check_zorder()
176 DSSERR("check_manager: invalid timings\n"); in dss_mgr_check_timings()
Ddss.c187 DSSERR("illegal DSS PLL ID %d\n", pll_id); in dss_ctrl_pll_enable()
213 DSSERR("error in PLL mux config for LCD\n"); in dss_ctrl_pll_set_control_mux()
229 DSSERR("error in PLL mux config for LCD2\n"); in dss_ctrl_pll_set_control_mux()
245 DSSERR("error in PLL mux config for LCD3\n"); in dss_ctrl_pll_set_control_mux()
251 DSSERR("error in PLL mux config\n"); in dss_ctrl_pll_set_control_mux()
295 DSSERR("PLL lock request timed out\n"); in dss_sdi_enable()
307 DSSERR("PLL lock timed out\n"); in dss_sdi_enable()
318 DSSERR("SDI reset timed out\n"); in dss_sdi_enable()
737 DSSERR("can't get clock fck\n"); in dss_get_clocks()
746 DSSERR("Failed to get %s\n", dss.feat->parent_clk_name); in dss_get_clocks()
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Doutput.c28 DSSERR("output already has device %s connected to it\n", in omapdss_output_set_device()
35 DSSERR("output type and display type don't match\n"); in omapdss_output_set_device()
60 DSSERR("output doesn't have a device connected to it\n"); in omapdss_output_unset_device()
66 DSSERR("device %s is not disabled, cannot unset device\n", in omapdss_output_unset_device()
Dhdmi_pll.c185 DSSERR("can't get sys_clk\n"); in dsi_init_pll_data()
229 DSSERR("can't get PLL mem resource\n"); in hdmi_pll_init()
235 DSSERR("can't ioremap PLLCTRL\n"); in hdmi_pll_init()
241 DSSERR("failed to init HDMI PLL\n"); in hdmi_pll_init()
Dhdmi4_core.c50 DSSERR("Timeout aborting DDC transaction\n"); in hdmi_core_ddc_init()
61 DSSERR("Timeout starting SCL clock\n"); in hdmi_core_ddc_init()
71 DSSERR("Timeout clearing DDC fifo\n"); in hdmi_core_ddc_init()
89 DSSERR("Timeout waiting DDC to be ready\n"); in hdmi_core_ddc_edid()
117 DSSERR("I2C Bus Low?\n"); in hdmi_core_ddc_edid()
122 DSSERR("I2C No Ack\n"); in hdmi_core_ddc_edid()
131 DSSERR("operation stopped when reading edid\n"); in hdmi_core_ddc_edid()
139 DSSERR("timeout reading edid\n"); in hdmi_core_ddc_edid()
153 DSSERR("E-EDID checksum failed!!\n"); in hdmi_core_ddc_edid()
882 DSSERR("can't get CORE mem resource\n"); in hdmi4_core_init()
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Dhdmi_wp.c80 DSSERR("Failed to set PHY power mode to %d\n", val); in hdmi_wp_set_phy_pwr()
96 DSSERR("Failed to set PLL_PWR_STATUS\n"); in hdmi_wp_set_pll_pwr()
128 DSSERR("no HDMI FRAMEDONE when disabling output\n"); in hdmi_wp_video_stop()
264 DSSERR("can't get WP mem resource\n"); in hdmi_wp_init()
271 DSSERR("can't ioremap HDMI WP\n"); in hdmi_wp_init()
Dmanager-sysfs.c65 DSSERR("new display is already connected\n"); in manager_display_store()
71 DSSERR("new display is not disabled\n"); in manager_display_store()
80 DSSERR("old display is not disabled\n"); in manager_display_store()
91 DSSERR("failed to connect new device\n"); in manager_display_store()
97 DSSERR("failed to connect device to this manager\n"); in manager_display_store()
104 DSSERR("failed to apply dispc config\n"); in manager_display_store()
Dvenc.c332 DSSERR("Failed to reset venc\n"); in venc_reset()
456 DSSERR("Failed to enable display: no output/manager\n"); in venc_display_enable()
597 DSSERR("can't get VDDA_DAC regulator\n"); in venc_init_regulator()
667 DSSERR("can't get tv_dac_clk\n"); in venc_get_clocks()
699 DSSERR("failed to connect output to new device: %s\n", in venc_connect()
820 DSSERR("can't get IORESOURCE_MEM VENC\n"); in venc_bind()
827 DSSERR("can't ioremap VENC\n"); in venc_bind()
849 DSSERR("Invalid DT data\n"); in venc_bind()
Dpll.c296 DSSERR("DSS DPLL GO bit not going down.\n"); in dss_pll_write_config_type_a()
302 DSSERR("cannot lock DSS DPLL\n"); in dss_pll_write_config_type_a()
322 DSSERR("failed to enable HSDIV clocks\n"); in dss_pll_write_config_type_a()
368 DSSERR("DSS DPLL GO bit not going down.\n"); in dss_pll_write_config_type_b()
373 DSSERR("cannot lock DSS DPLL\n"); in dss_pll_write_config_type_b()
Dsdi.c129 DSSERR("failed to enable display: no output/manager\n"); in sdi_display_enable()
260 DSSERR("can't get VDDS_SDI regulator\n"); in sdi_init_regulator()
289 DSSERR("failed to connect output to new device: %s\n", in sdi_connect()
415 DSSERR("failed to parse datapairs\n"); in sdi_init_port()
Dhdmi_phy.c218 DSSERR("can't get PHY mem resource\n"); in hdmi_phy_init()
224 DSSERR("can't ioremap TX PHY\n"); in hdmi_phy_init()
/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/
Ddsi.c713 DSSERR("DSI error, irqstatus %x\n", irqstatus); in dsi_handle_irq_errors()
724 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", in dsi_handle_irq_errors()
733 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); in dsi_handle_irq_errors()
1173 DSSERR("Failed to set dsi_if_enable to %d\n", enable); in dsi_if_enable()
1296 DSSERR("Failed to set DSI PLL power mode to %d\n", in dsi_pll_power()
1342 DSSERR("PLL not coming out of reset.\n"); in dsi_pll_enable()
1637 DSSERR("failed to set complexio power state to " in dsi_cio_power()
1907 DSSERR("CIO TXCLKESC%d domain not coming " \ in dsi_cio_wait_tx_clk_esc_reset()
2027 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); in dsi_cio_init()
2075 DSSERR("CIO PWR clock domain not coming out of reset.\n"); in dsi_cio_init()
[all …]
Dhdmi5.c177 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
183 DSSERR("Failed to configure PLL\n"); in hdmi_power_on_full()
286 DSSERR("failed to power on device\n"); in hdmi_core_enable()
384 DSSERR("failed to power on device\n"); in hdmi5_bridge_enable()
393 DSSERR("Error restoring audio configuration: %d", ret); in hdmi5_bridge_enable()
537 DSSERR("%s: Video mode does not support audio\n", in hdmi_audio_start()
553 DSSERR("%s: Video mode does not support audio\n", __func__); in hdmi_audio_stop()
637 DSSERR("Registering HDMI audio failed %d\n", r); in hdmi5_bind()
759 DSSERR("platform_get_irq failed\n"); in hdmi5_probe()
768 DSSERR("HDMI IRQ request failed\n"); in hdmi5_probe()
[all …]
Dhdmi4.c178 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
184 DSSERR("Failed to configure PLL\n"); in hdmi_power_on_full()
286 DSSERR("failed to power on device\n"); in hdmi4_core_enable()
386 DSSERR("failed to power on device\n"); in hdmi4_bridge_enable()
395 DSSERR("Error restoring audio configuration: %d", ret); in hdmi4_bridge_enable()
554 DSSERR("%s: Video mode does not support audio\n", in hdmi_audio_start()
656 DSSERR("Registering HDMI audio failed\n"); in hdmi4_bind()
785 DSSERR("platform_get_irq failed\n"); in hdmi4_probe()
794 DSSERR("HDMI IRQ request failed\n"); in hdmi4_probe()
802 DSSERR("can't get VDDA regulator\n"); in hdmi4_probe()
Dpll.c475 DSSERR("cannot lock PLL\n"); in dss_pll_write_config_type_a()
483 DSSERR("DSS DPLL GO bit not going down.\n"); in dss_pll_write_config_type_a()
489 DSSERR("cannot lock DSS DPLL\n"); in dss_pll_write_config_type_a()
510 DSSERR("failed to enable HSDIV clocks\n"); in dss_pll_write_config_type_a()
556 DSSERR("DSS DPLL GO bit not going down.\n"); in dss_pll_write_config_type_b()
561 DSSERR("cannot lock DSS DPLL\n"); in dss_pll_write_config_type_b()
Dhdmi4_core.c49 DSSERR("Timeout aborting DDC transaction\n"); in hdmi4_core_ddc_init()
60 DSSERR("Timeout starting SCL clock\n"); in hdmi4_core_ddc_init()
70 DSSERR("Timeout clearing DDC fifo\n"); in hdmi4_core_ddc_init()
86 DSSERR("Timeout waiting DDC to be ready\n"); in hdmi4_core_ddc_read()
111 DSSERR("I2C Bus Low?\n"); in hdmi4_core_ddc_read()
116 DSSERR("I2C No Ack\n"); in hdmi4_core_ddc_read()
125 DSSERR("operation stopped when reading edid\n"); in hdmi4_core_ddc_read()
133 DSSERR("timeout reading edid\n"); in hdmi4_core_ddc_read()
Ddss.c167 DSSERR("illegal DSS PLL ID %d\n", pll->id); in dss_ctrl_pll_enable()
195 DSSERR("error in PLL mux config for LCD\n"); in dss_ctrl_pll_set_control_mux()
211 DSSERR("error in PLL mux config for LCD2\n"); in dss_ctrl_pll_set_control_mux()
227 DSSERR("error in PLL mux config for LCD3\n"); in dss_ctrl_pll_set_control_mux()
233 DSSERR("error in PLL mux config\n"); in dss_ctrl_pll_set_control_mux()
279 DSSERR("PLL lock request timed out\n"); in dss_sdi_enable()
291 DSSERR("PLL lock timed out\n"); in dss_sdi_enable()
302 DSSERR("SDI reset timed out\n"); in dss_sdi_enable()
826 DSSERR("can't get clock fck\n"); in dss_get_clocks()
835 DSSERR("Failed to get %s\n", in dss_get_clocks()
[all …]
Dhdmi_pll.c138 DSSERR("can't get sys_clk\n"); in hdmi_init_pll_data()
177 DSSERR("failed to init HDMI PLL\n"); in hdmi_pll_init()
Dhdmi_wp.c79 DSSERR("Failed to set PHY power mode to %d\n", val); in hdmi_wp_set_phy_pwr()
95 DSSERR("Failed to set PLL_PWR_STATUS\n"); in hdmi_wp_set_pll_pwr()
127 DSSERR("no HDMI FRAMEDONE when disabling output\n"); in hdmi_wp_video_stop()

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