Searched refs:ETH_PLL_CTL0 (Results 1 – 1 of 1) sorted by relevance
18 #define ETH_PLL_CTL0 0x44 macro76 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_recalc_rate()86 u32 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()90 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()94 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()101 return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, in g12a_ephy_pll_enable()110 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()113 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()121 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_is_enabled()131 writel(0x29c0040a, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_init()[all …]