Searched refs:PLL_CTL0_LOCK_DIG (Results 1 – 1 of 1) sorted by relevance
19 #define PLL_CTL0_LOCK_DIG BIT(30) macro102 val & PLL_CTL0_LOCK_DIG, 0, PLL_LOCK_TIMEOUT); in g12a_ephy_pll_enable()123 return (val & PLL_CTL0_LOCK_DIG) ? 1 : 0; in g12a_ephy_pll_is_enabled()