| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gmu.c | 17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
26 gmu->hung = true; in a6xx_gmu_fault()
37 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
40 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
41 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
44 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
46 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
50 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
53 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
[all …]
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| D | a6xx_hfi.c | 26 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
55 if (!gmu->legacy) in a6xx_hfi_queue_read()
62 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
84 if (!gmu->legacy) { in a6xx_hfi_queue_write()
92 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
96 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, in a6xx_hfi_wait_for_ack() argument
99 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; in a6xx_hfi_wait_for_ack()
104 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_ack()
108 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
115 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, in a6xx_hfi_wait_for_ack()
[all …]
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| D | a6xx_gmu.h | 90 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) in gmu_read() argument
92 return msm_readl(gmu->mmio + (offset << 2)); in gmu_read()
95 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) in gmu_write() argument
97 return msm_writel(value, gmu->mmio + (offset << 2)); in gmu_write()
101 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) in gmu_write_bulk() argument
103 memcpy_toio(gmu->mmio + (offset << 2), data, size); in gmu_write_bulk()
107 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) in gmu_rmw() argument
109 u32 val = gmu_read(gmu, reg); in gmu_rmw()
113 gmu_write(gmu, reg, val | or); in gmu_rmw()
116 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) in gmu_read64() argument
[all …]
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| D | a6xx_gpu.h | 33 struct a6xx_gmu gmu; member
75 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
77 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
79 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
80 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
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| D | a6xx_gpu.c | 21 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
431 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
451 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
457 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
715 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in a6xx_hw_init()
934 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in a6xx_hw_init()
936 if (a6xx_gpu->gmu.legacy) { in a6xx_hw_init()
938 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); in a6xx_hw_init()
973 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); in a6xx_recover()
1049 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); in a6xx_fault_detect_irq()
[all …]
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| D | a6xx_gpu_state.c | 136 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
744 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
764 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
766 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
793 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
925 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_gpu_state_get()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | gpu.txt | 30 - qcom,gmu: For GMU attached devices a phandle to the GMU device that will
143 qcom,gmu = <&gmu>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | sm8150.dtsi | 628 qcom,gmu = <&gmu>;
670 gmu: gmu@2c6a000 { label
671 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
676 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
680 interrupt-names = "hfi", "gmu";
687 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sm8250.dtsi | 1264 qcom,gmu = <&gmu>;
1311 gmu: gmu@3d6a000 { label
1312 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1318 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1322 interrupt-names = "hfi", "gmu";
1329 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
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| D | sc7180.dtsi | 1909 qcom,gmu = <&gmu>;
1984 gmu: gmu@506a000 { label
1985 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
1988 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1991 interrupt-names = "hfi", "gmu";
1996 clock-names = "gmu", "cxo", "axi", "memnoc";
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| D | sdm845.dtsi | 4054 qcom,gmu = <&gmu>;
4128 gmu: gmu@506a000 { label
4129 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4134 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4138 interrupt-names = "hfi", "gmu";
4144 clock-names = "gmu", "cxo", "axi", "memnoc";
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | qcom-msm8974.dtsi | 1343 gmu_sram: gmu-sram@0 {
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