/kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/ |
D | etnaviv_gpu.c | 43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument 45 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param() 49 *value = gpu->identity.model; in etnaviv_gpu_get_param() 53 *value = gpu->identity.revision; in etnaviv_gpu_get_param() 57 *value = gpu->identity.features; in etnaviv_gpu_get_param() 61 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param() 65 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param() 69 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param() 73 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param() 77 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param() [all …]
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D | etnaviv_buffer.c | 89 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, in etnaviv_cmd_select_pipe() argument 94 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe() 102 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe() 104 else if (gpu->exec_state == ETNA_PIPE_3D) in etnaviv_cmd_select_pipe() 115 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, in etnaviv_buffer_dump() argument 121 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n", in etnaviv_buffer_dump() 123 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_dump() 151 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, in etnaviv_buffer_reserve() argument 158 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_reserve() 162 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) in etnaviv_buffer_init() argument [all …]
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D | etnaviv_sched.c | 80 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job() 88 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local 93 drm_sched_stop(&gpu->sched, sched_job); in etnaviv_sched_timedout_job() 107 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job() 108 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job() 109 if (gpu->completed_fence != gpu->hangcheck_fence || in etnaviv_sched_timedout_job() 111 gpu->hangcheck_dma_addr = dma_addr; in etnaviv_sched_timedout_job() 112 gpu->hangcheck_fence = gpu->completed_fence; in etnaviv_sched_timedout_job() 121 etnaviv_gpu_recover_hang(gpu); in etnaviv_sched_timedout_job() 123 drm_sched_resubmit_jobs(&gpu->sched); in etnaviv_sched_timedout_job() [all …]
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D | etnaviv_perfmon.c | 18 u32 (*sample)(struct etnaviv_gpu *gpu, 40 static u32 perf_reg_read(struct etnaviv_gpu *gpu, in perf_reg_read() argument 44 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read() 46 return gpu_read(gpu, domain->profile_read); in perf_reg_read() 49 static u32 pipe_reg_read(struct etnaviv_gpu *gpu, in pipe_reg_read() argument 53 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read() 57 for (i = 0; i < gpu->identity.pixel_pipes; i++) { in pipe_reg_read() 60 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_reg_read() 61 gpu_write(gpu, domain->profile_config, signal->data); in pipe_reg_read() 62 value += gpu_read(gpu, domain->profile_read); in pipe_reg_read() [all …]
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D | etnaviv_drv.c | 37 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu() 44 priv->gpu[i] = NULL; in load_gpu() 67 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local 70 if (gpu) { in etnaviv_open() 71 sched = &gpu->sched; in etnaviv_open() 94 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local 96 if (gpu) in etnaviv_postclose() 130 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_mmu_show() argument 135 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); in etnaviv_mmu_show() 142 mutex_lock(&gpu->lock); in etnaviv_mmu_show() [all …]
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D | etnaviv_iommu_v2.c | 165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_nonsec() argument 172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec() 175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec() 176 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_nonsec() 177 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_nonsec() 179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec() 182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec() 184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec() 186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec() 189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument [all …]
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D | etnaviv_gpu.h | 85 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event); 152 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument 154 writel(data, gpu->mmio + reg); in gpu_write() 157 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument 159 return readl(gpu->mmio + reg); in gpu_read() 162 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value); 164 int etnaviv_gpu_init(struct etnaviv_gpu *gpu); 165 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu); 168 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m); 171 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu); [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/ |
D | msm_gpu.c | 27 struct msm_gpu *gpu = dev_to_gpu(dev); in msm_devfreq_target() local 37 if (gpu->funcs->gpu_set_freq) in msm_devfreq_target() 38 gpu->funcs->gpu_set_freq(gpu, opp); in msm_devfreq_target() 40 clk_set_rate(gpu->core_clk, *freq); in msm_devfreq_target() 50 struct msm_gpu *gpu = dev_to_gpu(dev); in msm_devfreq_get_dev_status() local 53 if (gpu->funcs->gpu_get_freq) in msm_devfreq_get_dev_status() 54 status->current_frequency = gpu->funcs->gpu_get_freq(gpu); in msm_devfreq_get_dev_status() 56 status->current_frequency = clk_get_rate(gpu->core_clk); in msm_devfreq_get_dev_status() 58 status->busy_time = gpu->funcs->gpu_busy(gpu); in msm_devfreq_get_dev_status() 61 status->total_time = ktime_us_delta(time, gpu->devfreq.time); in msm_devfreq_get_dev_status() [all …]
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D | msm_gpu.h | 45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 46 int (*hw_init)(struct msm_gpu *gpu); 47 int (*pm_suspend)(struct msm_gpu *gpu); 48 int (*pm_resume)(struct msm_gpu *gpu); 49 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit); 50 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 52 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu); 53 void (*recover)(struct msm_gpu *gpu); 54 void (*destroy)(struct msm_gpu *gpu); 57 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state, [all …]
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D | msm_debugfs.c | 29 struct msm_gpu *gpu = priv->gpu; in msm_gpu_show() local 36 drm_printf(&p, "%s Status:\n", gpu->name); in msm_gpu_show() 37 gpu->funcs->show(gpu, show_priv->state, &p); in msm_gpu_show() 49 struct msm_gpu *gpu = priv->gpu; in msm_gpu_release() local 52 gpu->funcs->gpu_state_put(show_priv->state); in msm_gpu_release() 64 struct msm_gpu *gpu = priv->gpu; in msm_gpu_open() local 68 if (!gpu || !gpu->funcs->gpu_state_get) in msm_gpu_open() 79 pm_runtime_get_sync(&gpu->pdev->dev); in msm_gpu_open() 80 msm_gpu_hw_init(gpu); in msm_gpu_open() 81 show_priv->state = gpu->funcs->gpu_state_get(gpu); in msm_gpu_open() [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/ |
D | a3xx_gpu.c | 28 static void a3xx_dump(struct msm_gpu *gpu); 29 static bool a3xx_idle(struct msm_gpu *gpu); 31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit() argument 33 struct msm_drm_private *priv = gpu->dev->dev_private; in a3xx_submit() 83 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit() 86 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument 88 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init() 109 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init() 110 return a3xx_idle(gpu); in a3xx_me_init() 113 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument [all …]
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D | a5xx_gpu.c | 17 static void a5xx_dump(struct msm_gpu *gpu); 21 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument 24 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush() 54 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush() 57 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb() argument 59 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_submit_in_rb() 104 a5xx_flush(gpu, ring, true); in a5xx_submit_in_rb() 105 a5xx_preempt_trigger(gpu); in a5xx_submit_in_rb() 111 a5xx_idle(gpu, ring); in a5xx_submit_in_rb() 113 msm_gpu_retire(gpu); in a5xx_submit_in_rb() [all …]
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D | a4xx_gpu.c | 22 static void a4xx_dump(struct msm_gpu *gpu); 23 static bool a4xx_idle(struct msm_gpu *gpu); 25 static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a4xx_submit() argument 27 struct msm_drm_private *priv = gpu->dev->dev_private; in a4xx_submit() 70 adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR); in a4xx_submit() 77 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg() argument 79 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a4xx_enable_hwcg() 82 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg() 84 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg() 86 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg() [all …]
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D | a5xx_power.c | 103 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument 105 struct drm_device *dev = gpu->dev; in _get_mvolts() 122 static void a530_lm_setup(struct msm_gpu *gpu) in a530_lm_setup() argument 124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a530_lm_setup() 130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup() 134 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a530_lm_setup() 135 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a530_lm_setup() 136 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a530_lm_setup() 139 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a530_lm_setup() 141 gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage); in a530_lm_setup() [all …]
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D | a6xx_gpu.c | 15 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument 17 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle() 25 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle() 29 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle() 33 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument 36 if (!adreno_idle(gpu, ring)) in a6xx_idle() 39 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle() 41 gpu->name, __builtin_return_address(0), in a6xx_idle() 42 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle() 43 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle() [all …]
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D | a2xx_gpu.c | 10 static void a2xx_dump(struct msm_gpu *gpu); 11 static bool a2xx_idle(struct msm_gpu *gpu); 13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a2xx_submit() argument 15 struct msm_drm_private *priv = gpu->dev->dev_private; in a2xx_submit() 52 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit() 55 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init() argument 57 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init() 98 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init() 99 return a2xx_idle(gpu); in a2xx_me_init() 102 static int a2xx_hw_init(struct msm_gpu *gpu) in a2xx_hw_init() argument [all …]
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D | adreno_gpu.h | 47 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 141 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) in adreno_is_a2xx() argument 143 return (gpu->revn < 300); in adreno_is_a2xx() 146 static inline bool adreno_is_a20x(struct adreno_gpu *gpu) in adreno_is_a20x() argument 148 return (gpu->revn < 210); in adreno_is_a20x() 151 static inline bool adreno_is_a225(struct adreno_gpu *gpu) in adreno_is_a225() argument 153 return gpu->revn == 225; in adreno_is_a225() 156 static inline bool adreno_is_a305(struct adreno_gpu *gpu) in adreno_is_a305() argument 158 return gpu->revn == 305; in adreno_is_a305() 161 static inline bool adreno_is_a306(struct adreno_gpu *gpu) in adreno_is_a306() argument [all …]
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D | a5xx_preempt.c | 25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument 34 atomic_set(&gpu->preempt_state, new); in set_preempt_state() 40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument 52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr() 56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument 61 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring() 63 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring() 79 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local 80 struct drm_device *dev = gpu->dev; in a5xx_preempt_timer() 86 DRM_DEV_ERROR(dev->dev, "%s: preemption timed out\n", gpu->name); in a5xx_preempt_timer() [all …]
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D | a5xx_debugfs.c | 14 static void pfp_print(struct msm_gpu *gpu, struct drm_printer *p) in pfp_print() argument 21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print() 23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print() 27 static void me_print(struct msm_gpu *gpu, struct drm_printer *p) in me_print() argument 34 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print() 36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print() 40 static void meq_print(struct msm_gpu *gpu, struct drm_printer *p) in meq_print() argument 45 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print() 49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print() 53 static void roq_print(struct msm_gpu *gpu, struct drm_printer *p) in roq_print() argument [all …]
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D | adreno_gpu.c | 24 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument 27 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt() 79 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); in zap_shader_load_mdt() 84 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt() 134 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { in zap_shader_load_mdt() 170 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument 172 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load() 173 struct platform_device *pdev = gpu->pdev; in adreno_zap_shader_load() 185 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); in adreno_zap_shader_load() 189 adreno_iommu_create_address_space(struct msm_gpu *gpu, in adreno_iommu_create_address_space() argument [all …]
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D | a6xx_gpu_state.c | 112 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument 115 dumper->ptr = msm_gem_kernel_new_locked(gpu->dev, in a6xx_crashdumper_init() 116 SZ_1M, MSM_BO_UNCACHED, gpu->aspace, in a6xx_crashdumper_init() 125 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run() argument 128 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_crashdumper_run() 142 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE_LO, in a6xx_crashdumper_run() 145 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run() 147 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, in a6xx_crashdumper_run() 150 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run() 156 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, in debugbus_read() argument [all …]
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/kernel/linux/linux-5.10/Documentation/gpu/ |
D | amdgpu.rst | 13 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 31 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 34 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 40 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c 43 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c 49 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 52 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 58 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 61 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 67 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c [all …]
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D | drm-kms-helpers.rst | 53 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c 59 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c 68 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c 74 .. kernel-doc:: drivers/gpu/drm/drm_atomic_state_helper.c 80 .. kernel-doc:: drivers/gpu/drm/drm_atomic_state_helper.c 86 .. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c 92 .. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c 98 .. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c 104 .. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c 110 .. kernel-doc:: drivers/gpu/drm/drm_format_helper.c [all …]
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D | i915.rst | 19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c 31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdkfd/ |
D | kfd_topology.c | 94 return top_dev->gpu; in kfd_device_by_id() 105 if (top_dev->gpu && top_dev->gpu->pdev == pdev) { in kfd_device_by_pci_dev() 106 device = top_dev->gpu; in kfd_device_by_pci_dev() 123 if (top_dev->gpu && top_dev->gpu->kgd == kgd) { in kfd_device_by_kgd() 124 device = top_dev->gpu; in kfd_device_by_kgd() 274 if (iolink->gpu && kfd_devcgroup_check_permission(iolink->gpu)) in iolink_show() 314 if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu)) in mem_show() 347 if (cache->gpu && kfd_devcgroup_check_permission(cache->gpu)) in kfd_cache_show() 428 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show() 437 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show() [all …]
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