Searched refs:socfpgaclk (Results 1 – 9 of 9) sorted by relevance
17 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local20 if (socfpgaclk->fixed_div) { in socfpga_gate_clk_recalc_rate()21 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()22 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()23 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()24 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()33 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_dbg_clk_recalc_rate() local36 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()37 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_dbg_clk_recalc_rate()46 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_get_parent() local[all …]
21 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_peri_c_clk_recalc_rate() local25 val = readl(socfpgaclk->hw.reg); in clk_peri_c_clk_recalc_rate()35 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_peri_cnt_clk_recalc_rate() local38 if (socfpgaclk->fixed_div) { in clk_peri_cnt_clk_recalc_rate()39 div = socfpgaclk->fixed_div; in clk_peri_cnt_clk_recalc_rate()41 if (socfpgaclk->hw.reg) in clk_peri_cnt_clk_recalc_rate()42 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_peri_cnt_clk_recalc_rate()50 struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk); in clk_periclk_get_parent() local55 if (socfpgaclk->bypass_reg) { in clk_periclk_get_parent()56 mask = (0x1 << socfpgaclk->bypass_shift); in clk_periclk_get_parent()[all …]
24 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local27 if (socfpgaclk->fixed_div) in socfpga_gate_clk_recalc_rate()28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()40 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare() local45 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()47 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()79 if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) in socfpga_clk_prepare()[all …]
37 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in agilex_clk_pll_recalc_rate() local42 reg = readl(socfpgaclk->hw.reg); in agilex_clk_pll_recalc_rate()48 reg = readl(socfpgaclk->hw.reg + 0x24); in agilex_clk_pll_recalc_rate()58 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local65 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()72 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()82 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_boot_clk_recalc_rate() local85 div = ((readl(socfpgaclk->hw.reg) & in clk_boot_clk_recalc_rate()95 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local98 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()[all …]
23 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local26 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()27 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()30 div &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()33 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_periclk_recalc_rate()41 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_get_parent() local45 clk_src = readl(socfpgaclk->hw.reg); in clk_periclk_get_parent()
20 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local23 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()24 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()28 val &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()31 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); in clk_periclk_recalc_rate()
93 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_recalc_rate() local96 if (socfpgaclk->fixed_div) in socfpga_clk_recalc_rate()97 div = socfpgaclk->fixed_div; in socfpga_clk_recalc_rate()98 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()99 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()100 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_clk_recalc_rate()102 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()113 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare() local119 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()127 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
37 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local42 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()52 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local55 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
41 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()61 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()